Test Program Generation From High-level Microprocessor Descriptions
[chapter in] Test and validation of hardware/software systems starting from system-level descriptions, Edited by M. Sonza Reorda, M. Violante, Z. Peng, Springer publisher, 2005, 179 p, ISBN: 1-85233-899-7, pp. 83-106
KEYWORDS:
Evolutionary Algorithms,
High-level descriptions,
SBST,
Simulation-Based Approaches,
microGP,
ugp
ABSTRACT
This chapter describes and analyzes a methodology for gathering together test-programs for microprocessor cores during the complete design cycle starting from early design phases. The methodology is based on an almost automatic tool and could be applied to generate test-programs for stand-alone microprocessor cores as well as for these embedded in systems-on-chip. The main idea is to take advantage of all possible microprocessor descriptions delivered through the whole design cycle to generate test-programs able to achieve a high FC% at gate-level. Most of the efforts of the methodology presented are focused on test program generation from high-level microprocessor descriptions. A case study is presented tackling a pipelined microprocessor core.
[SSSq05] E. Sanchez, M. Sonza Reorda, G. Squillero, "Test Program Generation From High-level Microprocessor Descriptions," [chapter in] Test and validation of hardware/software systems starting from system-level descriptions, Edited by M. Sonza Reorda, M. Violante, Z. Peng, Springer publisher, 2005, 179 p, ISBN: 1-85233-899-7, pp. 83-106 |
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