On the Test of Microprocessor IP Cores
DATE2001: IEEE Design, Automation & Test in Europe Conference, Munich (Germany), 13-16 March 2001, pp. 209-213
KEYWORDS:
ATPG,
Approximate Methods,
Evolutionary Algorithms,
Gate-Level,
Genetic Algorithms,
Micro-Processors,
Simulation-Based Approaches
ABSTRACT
Testing is a crucial issue in SOC development and production process. A popular solution for SOCs that include microprocessor cores is based on making them execute a test program. In this way it is possible to implement a very attracting BIST solution. This paper describes a method for the generation of effective programs for the self-test of a processor. The method can be partially automated, and combines ideas from traditional functional approaches and from the ATPG field. We assess the feasibility and effectiveness of the method by applying it to a 8051 core.
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[CSSV01] F. Corno, M. Sonza Reorda, G. Squillero, M. Violante, "On the Test of Microprocessor IP Cores," DATE2001: IEEE Design, Automation & Test in Europe Conference, Munich (Germany), 13-16 March 2001, pp. 209-213 |
