Automatic Test Program Generation for Verifyng Microprocessors
IEEE Potentials, Vol 24, Issue 1, Feb-Mar 2005, pp. 34-37
KEYWORDS:
ATPG,
Approximate Methods,
Evolutionary Algorithms,
Genetic Programming,
Micro-Processors,
MicroGP,
RT-Level,
Simulation-Based Approaches,
VHDL
ABSTRACT
A pipelined processor with a high-level behavioral HDL description is presented in this paper. It generates a set of effective test programs by using a simulator, which is able to evaluate with respect to an RTL coverage metric. The proposed optimizer is based on a technique called microGP, an evolutionary system able to automatically device and optimizes the program written in an assembly language. Quantitative coverage measurement presented will guide the test-program generation. The approach is fully automatic and broadly applicable. The minimal test set with the programmable coverage is attained.
[CSSS05] F. Corno, E. Sanchez, M. Sonza Reorda, G. Squillero, "Automatic Test Program Generation for Verifyng Microprocessors," IEEE Potentials, Vol 24, Issue 1, Feb-Mar 2005, pp. 34-37 |
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