Automatic Test Program Generation for Pipelined Processors
SAC2003: The Eighteenth Annual ACM Symposium on Applied Computing, Melbourne, Florida (USA), March 9-12, 2003, pp. 736-740
KEYWORDS:
ATPG,
Approximate Methods,
Evolutionary Algorithms,
Genetic Programming,
Micro-Processors,
MicroGP,
RT-Level,
Simulation-Based Approaches,
VHDL
ABSTRACT
The continuous advances in microelectronics design are creating a significant challenge to design validation in general, but tackling pipelined microprocessors is remarkably more demanding. This paper presents a methodology to automatically induce a test program for a microprocessor maximizing a given verification metric. The approach exploits a new evolutionary algorithm, close to Genetic Programming, able to cultivate effective assembly-language programs. The proposed methodology was used to verify the DLX/pII, an open-source processor with a 5-stage pipeline. Code-coverage was adopted in the paper, since it can be considered the required starting point for any simulation-based functional verification processes. Experimental results clearly show the effectiveness of the approach.
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[CSSq03] F. Corno, M. Sonza Reorda, G. Squillero, "Automatic Test Program Generation for Pipelined Processors," SAC2003: The Eighteenth Annual ACM Symposium on Applied Computing, Melbourne, Florida (USA), March 9-12, 2003, pp. 736-740 |
