New Static Compaction Techniques of Test Sequences for Sequential Circuits
ED&TC97: IEEE European Design and Test Conference, Paris (F), March 1997, pp. 37-43
KEYWORDS: ATPG, Approximate Methods, Evolutionary Algorithms, Gate-Level, Genetic Algorithms, Simulation-Based Approaches
This paper describes an algorithm for compacting the Test Sequences generated by an ATPG tool without reducing the number of faults they detect. The algorithm is based on re-ordering the sequences so that some of them can be shortened and some others eliminated. The problem is NP-complete, and we adopt Genetic Algorithms to obtain optimal solutions with acceptable computational requirements. As it requires just one preliminary Fault Simulation experiment, the approach is much more efficient than others proposed before; experimental results gathered with Test Sets generated by different ATPG tools show that the method is able to reduce the size of the Test Set by a factor varying between 50% and 62%.
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[CRPS97] F. Corno, M. Rebaudengo, P. Prinetto, M. Sonza Reorda, "New Static Compaction Techniques of Test Sequences for Sequential Circuits," ED&TC97: IEEE European Design and Test Conference, Paris (F), March 1997, pp. 37-43