Testability analysis and ATPG on behavioral RT-level VHDL
ITC97, IEEE International Test Conference, Washington D. C. (USA), November 1997
KEYWORDS: ATPG, Approximate Methods, Evolutionary Algorithms, Genetic Algorithms, Rt-Level, Simulation-Based Approaches, VHDL
This paper proposes an environment to address Testability Analysis and Test Pattern Generation on VHDL descriptions at the RT-level. The proposed approach, based on a suitable fault model and an ATPG algorithm, is experimentally shown to provide a good estimate of the final gate-level fault coverage, and to give test patterns with excellent fault coverage properties. The approach, being based on an abstract representation, is particularly suited for large circuits, where gate-level ATPGs are often inefficient.
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[CPSe97] F. Corno, P. Prinetto, M. Sonza Reorda, "Testability analysis and ATPG on behavioral RT-level VHDL," ITC97, IEEE International Test Conference, Washington D. C. (USA), November 1997