Publications

  1. A Novel Dual Core Architecture for the Analysis of DNA Microarray Images
    L. Sterpone
    IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, 2009
    DOI: 10.1109/TIM.2009.2015695

  2. Effective Diagnostic Pattern Generation Strategy forTransition-Delay Faults in Full-Scan SOCs
    D. Appello, P. Bernardi, M. Grosso, E. Sanchez, M. Sonza Reorda
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2009
    DOI: 10.1109/TVLSI.2008.2006177
    KEYWORDS: sbst; large-scale circuits; delay effects
    ABSTRACT: Abstract—Nanometric circuits and systems are increasingly susceptible to delay defects. This paper describes a strategy for the diagnosis of transition- delay faults in full-scan systems-on-a-chip (SOCs). The proposed methodology takes advantage of a suitably generated software-based self-test test set and of the scan-chains included in the final SOC design. Effectiveness and feasibility of the proposed approach were evaluated on a nanometric SOC test vehicle including an 8-bit microcontroller, some memory blocks and an arithmetic core, manufactured by STMicroelectronics. Results show that the proposed technique can achieve high diagnostic resolution while maintaining a reasonable application time

  3. Methodologies to study frequency-dependent Single Event Effects sensitivity in Flash-based FPGAs
    N. Battezzati, S. Gerardin, A. Manuzzato, D. Merodio, A. Paccagnella, C. Poivey, L. Sterpone, M. Violante
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2009
    DOI: 10.1109/TNS.2009.2034316

  4. New techniques for improving the performance of the lockstep architecture for SEEs mitigation in FPGA embedded processors
    F. Abate, L. Sterpone, C. Lisboa, L. Carro, M. Violante
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2009
    DOI: 10.1109/TNS.2009.2013237

  5. On Improving Automation by Integrating RFID in the Traceability Management of the Agri-Food Sector
    F. Gandino, B. Montrucchio, M. Rebaudengo, E. Sanchez
    IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 2009
    DOI: 10.1109/TIE.2009.2019569
    ABSTRACT: Traceability is a key factor for the agri-food sector. RFID technology, widely adopted for supply chain management, can be used effectively for the traceability management. In this paper, a framework for the evaluation of a traceability system for the agri-food industry is presented and the automation level in an RFID-based traceability system is analyzed and compared with respect to traditional ones. Internal and external traceability are both considered and formalized, in order to classify different environments, according to their automation level. Traceability systems used in a sample sector are experimentally analyzed, showing that by using RFID technology, agri-food enterprises increase their automation level and also their efficiency, in a sustainable way

  6. Opportunity and Constraints for Wide Adoption of RFID in Agri-Food
    F. Gandino, E. Sanchez, B. Montrucchio, M. Rebaudengo
    INTERNATIONAL JOURNAL OF ADVANCED PERVASIVE AND UBIQUITOUS COMPUTING, 2009

  7. Test Program Generation for Communication Peripherals in Processor-Based Systems-on-Chip
    A. Apostolakis, D. Gizopoulos, M. Psarakis, D. Ravotto, M. Sonza Reorda
    IEEE DESIGN & TEST OF COMPUTERS, 2009
    DOI: 10.1109/MDT.2009.43
    ABSTRACT: Testing communication peripherals in an environment of systems on a chip is particularly challenging. The authors explore two test program generation approaches-one fully automated and one deterministically guided-and propose a novel combination of the two schemes that can be applied in a generic manner on a wide set of communication cores

  8. A New Mitigation Approach For Soft Errors In Embedded Processors
    F. Abate, L. Sterpone, M. Violante
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2008
    DOI: 10.1109/TNS.2008.2000839

  9. A new Algorithm for the Analysis of the MCUs Sensitiveness of TMR Architectures in SRAM-based FPGAs
    L. Sterpone, M. Violante
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2008
    DOI: 10.1109/TNS.2008.2001858

  10. An Effective technique for the Automatic Generation of Diagnosis-oriented Programs for Processor Cores
    P. Bernardi, E. Sanchez, M. Schillaci, G. Squillero, M. Sonza Reorda
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2008
    DOI: 10.1109/TCAD.2008.915541
    ABSTRACT: A large part of microprocessor cores in use today are de- signed to be cheap and mass produced. The diagnostic process, which is fundamental to improve yield, has to be as cost effective as possible. This paper presents a novel approach to the construction of diagnosis-oriented software-based test sets for microprocessors. The methodology exploits existing manufacturing test sets designed for software-based self-test and improves them by using a new diagnosis-oriented approach. Experimental results are reported in this paper showing the feasibility, robustness, and effectiveness of the approach for diagnosing stuck-at faults on an Intel i8051 processor core

  11. Effectiveness of TMR-based techniques to mitigate alpha-induced SEU accumulation in commercial SRAM-based FPGAs
    A. Manuzzato, S. Gerardin, A. Paccagnella, L. Sterpone, M. Violante
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2008
    DOI: 10.1109/TNS.2008.2000850

  12. Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs
    E.L. Rhod, Carlos Arthur Lang Lisbôa, L. Carro, M. Sonza Reorda, M. Violante
    JOURNAL OF ELECTRONIC TESTING, 2008

  13. Monte Carlo Analysis of the Effects of Soft Errors Accumulation in SRAM-based FPGAs
    N. Battezzati, L. Sterpone, M. Violante
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2008
    DOI: 10.1109/TNS.2008.2006839

  14. Soft Errors in SRAM-FPGAs: a Comparison of Two Complementary Approaches
    M. Alderighi, F. Casini, S. D'Angelo, M. Mancini, S. Pastore, L. Sterpone, M. Violante
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2008
    DOI: 10.1109/TNS.2008.2000479

  15. Software and Hardware Techniques for SEU Detection in IP Processors
    C. Bolchini, A. Miele, M. Rebaudengo, F. Salice, L. Sterpone, M. Violante
    JOURNAL OF ELECTRONIC TESTING, 2008
    DOI: 10.1007/s10836-007-5028-0

  16. A New Partial Reconfiguration-based Fault-Injection System to Evaluate SEU Effects in SRAM-based FPGAs
    L. Sterpone, M. Violante
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2007
    DOI: 10.1109/TNS.2007.904080

  17. A System-layer Infrastructure for SoC Diagnosis
    P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda
    JOURNAL OF ELECTRONIC TESTING, 2007

  18. A new approach to estimate the effect of single event transients in complex circuits
    M. Aguirre, V. Baena, J. Tombs, M. Violante
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2007
    DOI: 10.1109/TNS.2007.895549

  19. A new hardware/software platform and a new 1/E neutron source for soft error studies: testing FPGAs at the ISIS facility
    M. Violante, L. Sterpone, A. Manuzzato, S. Gerardin, P. Rech, M. Bagatin, A. Paccagnella, C. Andreani, G. Gorini, A. Pietropaolo, G. Cardarilli, S. Pontarelli, C. Frost
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2007
    DOI: 10.1109/TNS.2007.902349

  20. Evaluating different solutions to design fault tolerant systems with SRAM-based FPGAs
    M. Sonza Reorda, L. Sterpone, M. Violante, F. Lima Kastensmidt, L. Carro
    JOURNAL OF ELECTRONIC TESTING, 2007
    DOI: 10.1007/s10836-006-0403-9

  21. Experimental Validation of a Tool for Predicting the Effects of Soft Errors in SRAM-based FPGAs
    L. Sterpone, M. Violante, R. Harboe Sorensen, D. Merodio, F. Sturesson, R. Weigand, S. Mattsson
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2007
    DOI: 10.1109/TNS.2007.910122

  22. A new hybrid fault detection technique for systems-on-a-chip
    P. Bernardi, Veiras Bolzani Lm., M. Rebaudengo, M. Sonza Reorda, F. Vargas, M. Violante
    IEEE TRANSACTIONS ON COMPUTERS, 2006
    DOI: 10.1109/TC.2006.15
    ABSTRACT: Hardening SoCs against transient faults requires new techniques able to combine high fault detection capabilities with the usual requirements of SoC design flow, e.g., reduced design-time, low area overhead, and reduced (or null) accessibility to source core descriptions. This paper proposes a new hybrid approach which combines hardening software transformations with the introduction of an Infrastructure IP with reduced memory and performance overheads. The proposed approach targets faults affecting the memory elements storing both the code and the data, independently of their location (inside or outside the processor). Extensive experimental results, including comparisons with previous approaches, are reported, which allow practically evaluating the characteristics of the method in terms of fault detection capabilities and area, memory, and performance overheads

  23. A new reliability-oriented place and route algorithm for SRAM-based FPGAs
    L. Sterpone, M. Violante
    IEEE TRANSACTIONS ON COMPUTERS, 2006
    DOI: 10.1109/TC.2006.82
    ABSTRACT: The very high integration levels reached by VLSI technologies for SRAM-based Field Programmable Gate Arrays (FPGAs) lead to high occurrence-rate of transient faults induced by Single Event Upsets (SEUs) in FPGAs' configuration memory. Since the configuration memory defines which circuit an SRAM-based FPGA implements, any modification induced by SEUs may dramatically change the implemented circuit. When such devices are used in safety-critical applications, fault-tolerant techniques are needed to mitigate the effects of SEUs in FPGAs' configuration memory. In this paper, we analyze the effects induced by the SEUs in the configuration memory of SRAM-based FPGAs. The reported analysis outlines that SEUs in the FPGA's configuration memory are particularly critical since they are able to escape well-known fault masking techniques such as Triple Modular Redundancy (TMR). We then present a reliability-oriented place and route algorithm that, coupled with TMR, is able to effectively mitigate the effects of the considered faults. The effectiveness of the new reliability-oriented place and route algorithm is demonstrated by extensive fault injection experiments showing that the capability of tolerating SEU effects in the FPGA's configuration memory increases up to 85 times with respect to a standard TMR design technique

  24. An Analysis based on Fault Injection of Hardening Techniques for SRAM-based FPGAs
    L. Sterpone, M. Violante, S. Rezgui
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2006
    DOI: 10.1109/TNS.2006.880937

  25. Early, Accurate Dependability Analysis of CAN-Based Networked Systems
    J. Perez, M. Sonza Reorda, M. Violante
    IEEE DESIGN & TEST OF COMPUTERS, 2006
    DOI: 10.1109/MDT.2006.10
    ABSTRACT: For safety-critical applications, accurately evaluating network dependability is crucial. This article, a special selection from the Symposium on Integrated Circuits and Systems Design (SBCCI), describes a fault-injection environment for assessing CAN-based networks common in the automotive field. The approach focuses particularly on revealing how soft errors within the CAN protocol controllers affect system behavior

  26. Efficient Techniques for Automatic Verification-Oriented Test Set Optimization
    E. Sanchez, M. Sonza Reorda, G. Squillero
    INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, 2006
    DOI: 10.1007/s10766-005-0005-7
    ABSTRACT: Most Systems-on-a-Chips include a custom microprocessor core, and time and resource constraints make the design of such devices a challenging task. This paper presents a simulation-based methodology for the automatic completion and refinement of verification test sets. The approach extends the µGP, an evolutionary test program generator, with the possibility to enhance existing test sets. Already devised test programs are not merely included in the new set, but assimilated and used as a starting point for a new test-program cultivation task. Reusing existing material cuts down the time required to generate a verification test set during the microprocessor design. Experimental results are reported on a small pipelined microprocessor, and show the effectiveness of the approach. Additionally, the use of the proposed methodology enabled to experimentally analyze the relationship of the different code coverage metrics used in the test program generation

  27. HYBRID FAULT DETECTION TECHNIQUE A CASE STUDY ON VIRTEX-II PRO'S POWERPC
    P. Bernardi, L. Sterpone, M. Violante, M. Portela-Garcia
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2006
    DOI: 10.1109/TNS.2006.886221

  28. Hardening FPGA-based systems against SEUs: A new design methodology
    L. Sterpone, M. Violante
    JOURNAL OF COMPUTERS, 2006

  29. System-in-package testing: problems and solutions
    D. Appello, P. Bernardi, M. Grosso, M. Sonza Reorda
    IEEE DESIGN & TEST OF COMPUTERS, 2006
    DOI: 10.1109/MDT.2006.79
    ABSTRACT: System in package integrates multiple dies in a common package. Therefore, testing SiP technology is different from system on chip, which integrates multiple vendor parts. This article provides test strategies for known good die and known good substrate in the SiP. Case studies prove feasibility using the IEEE 1500 test structure

  30. A New Analytical Approach to Estimate the Effects of SEUs in TMR Architectures Implemented Through SRAM-based FPGAs
    L. Sterpone, M. Violante
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2005
    DOI: 10.1109/TNS.2005.860745
    ABSTRACT: In order to deploy successfully commercially-off-the- shelf SRAM-based FPGA devices in safety- or mission-critical ap- plications, designers need to adopt suitable hardening techniques, as well as methods for validating the correctness of the obtained designs, as far as the system's dependability is concerned. In this paper we describe a new analytical approach to estimate the de- pendability of TMR designs implemented on SRAM-based FPGAs that, by exploiting a detailed knowledge of FPGAs architectures and configuration memory, is able to predict the effects of single event upsets with the same accuracy of fault injection but at a frac- tion of the fault-injection's execution time

  31. Analysis of the robustness of the TMR architecture in SRAM-based FPGAs
    L. Sterpone, M. Violante
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2005
    DOI: 10.1109/TNS.2005.856543
    ABSTRACT: Non radiation-hardened SRAM-based Field Pro- grammable Gate Arrays (FPGAs) are very sensitive to Single Event Upsets (SEUs) affecting their configuration memory and thus suitable hardening techniques are needed when they are intended to be deployed in critical applications. Triple Module Re- dundancy is a known solution for hardening digital logic against SEUs that is widely adopted for traditional techniques (like ASICs). In this paper we present an analysis of the SEU effects in circuits hardened according to the Triple Module Redundancy to investigate the possibilities of successfully applying TMR to designs mapped on commercial-off-the-shelf SRAM-based FPGAs, which are not radiation hardened. We performed dif- ferent fault-injection experiments in the FPGA configuration memory implementing TMR designs and we observed that the percentage of SEUs escaping TMR could reach 13%. In this paper we report detailed evaluations of the effects of the observed failure rates, and we proposed a first step toward an improved TMR implementation

  32. Automatic Test Generation for Verifying Microprocessors
    F. Corno, E. Sanchez, M. Sonza Reorda, G. Squillero
    IEEE POTENTIALS, 2005
    DOI: 10.1109/MP.2005.1405800

  33. Evolving assembly programs: how games help microprocessor validation
    F. Corno, E. Sanchez, G. Squillero
    IEEE TRANSACTIONS ON EVOLUTIONARY COMPUTATION, 2005
    DOI: 10.1109/TEVC.2005.856207
    ABSTRACT: Core War is a game where two or more programs, called warriors, are executed in the same memory area by a time-sharing processor. The final goal of each warrior is to crash the others by overwriting them with illegal instructions. The game was popularized by A. K. Dewdney in his Scientific American column in the mid-1980s. In order to automatically devise strong warriors, MicroGP, a test program generation algorithm, was extended with the ability to assimilate existing code and to detect clones; furthermore, a new selection mechanism for promoting diversity independent from fitness calculations was added. The evolved warriors are the first machine-written programs ever able to become King of the Hill (champion) in all four main international Tiny Hills. This paper shows how playing Core War may help generate effective test programs for validation and test of microprocessors. Tackling a more mundane problem, the described techniques are currently being exploited for the automatic completion and refinement of existing test programs. Preliminary experimental results are reported

  34. MicroGP - An Evolutionary Assembly Program Generator
    G. Squillero
    GENETIC PROGRAMMING AND EVOLVABLE MACHINES, 2005
    DOI: 10.1007/s10710-005-2985-x
    ABSTRACT: This paper describes µGP, an evolutionary approach for generating assembly programs tuned for a specific microprocessor. The approach is based on three clearly separated blocks: an evolutionary core, an instruction library and an external evaluator. The evolutionary core conducts adaptive population-based search. The instruction library is used to map individuals to valid assembly language programs. The external evaluator simulates the assembly program, providing the necessary feedback to the evolutionary core. µGP has some distinctive features that allow its use in specific contexts. This paper focuses on one such context: test program generation for design validation of microprocessors. Reported results show µGP being used to validate a complex 5-stage pipelined microprocessor. Its induced test programs outperform an exhaustive functional test and an instruction randomizer, showing that engineers are able to automatically obtain high-quality test programs

  35. A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques
    D. Appello, A. Fudoli, V. Tancorre, P. Bernardi, F. Corno, M. Rebaudengo, M. Sonza Reorda
    JOURNAL OF ELECTRONIC TESTING, 2004
    DOI: 10.1023/B:JETT.0000009315.57771.94

  36. A new approach to software-implemented fault tolerance
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    JOURNAL OF ELECTRONIC TESTING, 2004

  37. Automatic Test Program Generation: a Case Study
    F. Corno, E. Sanchez, M. Sonza Reorda, G. Squillero
    IEEE DESIGN & TEST OF COMPUTERS, 2004
    DOI: 10.1109/MDT.2004.1277902
    ABSTRACT: Editor's note: Comprehensive coverage measurement should guide an effective testbench generation approach. Today, feedback from coverage to test generation often requires manual work; it is desirable to implement a framework that automates this feedback process. The authors propose a genetic-algorithm- based evolution framework for testbench generation. It enables small test programs to evolve and effectively capture target corner cases based on the feedback from coverage measurement

  38. Code Generation for Functional Validation of Pipelined Microprocessors
    F. Corno, E. Sanchez, M. Sonza Reorda, G. Squillero
    JOURNAL OF ELECTRONIC TESTING, 2004

  39. Efficient analysis of single event transients
    M. Sonza Reorda, M. Violante
    JOURNAL OF SYSTEMS ARCHITECTURE, 2004
    DOI: 10.1016/j.sysarc.2003.08.008

  40. Evolutionary Simulation-Based Validation
    F. Corno, M. Sonza Reorda, G. Squillero
    INTERNATIONAL JOURNAL ON ARTIFICIAL INTELLIGENCE TOOLS, 2004

  41. Simulation-Based Analysis of SEU Effects in SRAM-Based FPGAs
    M. Violante, L. Sterpone, M. Ceschia, D. Bortolato, P. Bernardi, M. Sonza Reorda, A. Paccagnella
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2004
    DOI: 10.1109/TNS.2004.839516
    ABSTRACT: SRAM-based field programmable gate arrays (FPGAs) are particularly sensitive to single event upsets (SEUs) that, by changing the FPGA's configuration memory, may affect dramatically the functions implemented by the device. In this paper we describe a new approach for predicting SEU effects in circuits mapped on SRAM-based FPGAs that combines radiation testing with simulation. The former is used to characterize (in terms of device cross section) the technology on which the FPGA device is based, no matter which circuit it implements. The latter is used to predict the probability for a SEU to alter the expect behavior of a given circuit. By combining the two figures, we then compute the cross section of the circuit mapped on the pre-characterized device. Experimental results are presented that compare the approach we developed with a traditional one based on radiation testing only, to measure the cross section of a circuit mapped on an FPGA. The figures here reported confirm the accuracy of our approach

  42. Accurate Analysis of Single Event Upsets in a Pipelined Microprocessor
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    JOURNAL OF ELECTRONIC TESTING, 2003
    DOI: 10.1023/A:1025130131636

  43. Accurate single-event-transient analysis via zero-delay logic simulation
    M. Violante
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2003
    DOI: 10.1109/TNS.2003.820729

  44. Identification and classification of single-event upsets in the configuration memory of sram-based fpgas
    M. Ceschia, M. Violante, M. Sonza Reorda, A. Paccagnella, P. Bernardi, M. Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, A. Candelori
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2003

  45. Impact of data cache memory on the single event upset-induced error rate of microprocessors
    F. Faure, R. Velazco, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2003
    DOI: 10.1109/TNS.2003.821824

  46. New Techniques for efficiently assessing reliability of SOCs
    P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    MICROELECTRONICS JOURNAL, 2003

  47. An FPGA-based approach for speeding-up Fault Injection campaigns on safety-critical circuits
    P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    JOURNAL OF ELECTRONIC TESTING, 2002

  48. Coping With SEUs/SETs in Microprocessors by means of Low-Cost Solutions: A Comparative Study
    M. Rebaudengo, M. Sonza Reorda, M. Violante, B. Nicolescu, R. Velazco
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2002

  49. Initializability Analysis of Synchronous Sequential Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, G. Squillero
    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2002
    DOI: 10.1145/544536.544538

  50. Exploiting Circuit Emulation for Fast Hardness Evaluation
    P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2001

  51. Experimentally evaluating an automatic approach for generating safety-critical software with respect to transient errors
    P. Cheynet, B. Nicolescu, R. Velazco, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2000

  52. RT-level ITC'99 benchmarks and first ATPG results
    F. Corno, M. Sonza Reorda, G. Squillero
    IEEE DESIGN & TEST OF COMPUTERS, 2000
    DOI: 10.1109/54.867894
    ABSTRACT: New design flows require reducing work at the gate level and performing most activities before the synthesis step, including evaluation of testability of circuits. We propose a suite of RT-level benchmarks that help improve research in high-level ATPG tools. First results on the benchmarks obtained with our prototype tool show the feasibility of the approach