CAD

Papers by E. Sanchez

  1. Automatic generation of software-based functional failing test for speed debug and on-silicon timing verification
    E. Sanchez, G. Squillero, A. Tonda
    MTV11: International Workshop on Microprocessor Test and Verification
  2. Post-Silicon Failing-Test Generation through Evolutionary Computation
    E. Sanchez, G. Squillero, A. Tonda
    19th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
  3. Post-Silicon Functional Failing-Test Generation through Evolutionary Computation
    E. Sanchez, G. Squillero, A. Tonda
    ETS2005: IEEE European Test Symposium, 2005
  4. Increasing Pattern Recognition Accuracy for Chemical Sensing by Evolutionary Based Drift Compensation
    S. Di Carlo, M. Falasconi, E. Sanchez, A. Scionti, G. Squillero, A. Tonda
    Pattern Recognition Letters, pp. 1594-1603
  5. Covariance Matrix Adaptation Evolutionary Strategy for Drift Correction of Electronic Nose Data
    S. Di Carlo, M. Falasconi, E. Sanchez, A. Scionti, G. Squillero, A. Tonda
    International Symposium on Olfaction and Electronic Nose (ISOEN 2011)
  6. Evolutionary Optimization: the µGP toolkit
    E. Sanchez, M. Schillaci, G. Squillero
    Hardcover, ISBN 978-0-387-09425-0 / 1st Edition., 2011, XIII, 178 p.
  7. Microprocessor Software-Based Self-Testing.
    M. Psarakis, D. Gizopoulos, E. Sanchez, M. Sonza Reorda
    IEEE Design & Test of Computers, May/June 2010, pp. 4-18
  8. A Software-based self-test methodology for system peripherals
    M. Grosso, W.J. Perez H, D. Ravotto, E. Sanchez, M. Sonza Reorda, J. Velasco Medina
    IEEE European Test Symposium (ETS 10), May 24-28, 2010, Prague, Czech Republic (accepted for publication)
  9. Towards Drift Correction in Chemical Sensors Using an Evolutionary Strategy
    S. Di Carlo, M. Falasconi, E. Sanchez, A. Scionti, G. Squillero, A. Tonda
    GECCO 2010: Proceedings of the 2009 GECCO conference on Genetic and evolutionary computation
  10. Exploiting Evolution for an Adaptive Drift-Robust Classifier in Chemical Sensing
    S. Di Carlo, M. Falasconi, E. Sanchez, A. Scionti, G. Squillero, A. Tonda
    EVONUM 2010: Published in Lecture Notes in Computer Science, Volume 6024/2010, Applications of Evolutionary Computation, pp. 412-421
  11. Evolving Individual Behavior in a Multi-Agent Traffic Simulator
    E. Sanchez, G. Squillero, A. Tonda
    EVOCOMPLEX 2010: Published in Lecture Notes in Computer Science, Volume 6024/2010, Applications of Evolutionary Computation, pp. 11-20
  12. A hardware accelerated framework for the generation of design validation programs for SMT processors
    D. Ravotto, E. Sanchez, M. Sonza Reorda
    IEEE Design and Diagnostic of Electronic Circuits and Systems, Vienna, April 2010, pp. 289-292
  13. Automatic Detection of Software Defects: an Industrial Experience
    S. Gandini, D. Ravotto, W. Ruzzarin, E. Sanchez, G. Squillero, A. Tonda
    GECCO 2009: Proceedings of the 2009 GECCO conference on Genetic and evolutionary computation, Montreal, Quebec (Canada), pp: 1921-1922
  14. On the Generation of Functional Test Programs for the Cache Replacement Logic
    W. J. Perez H., D. Ravotto, E. Sanchez, M. Sonza Reorda, A. Tonda
    ATS 2009: Proceedings of the 2009 Asian Test Symposium, pp. 418-423
  15. Automatic Functional Stress Pattern Generation for SoC Reliability Characterization
    D. Appello, P. Bernardi, R. Cagliesi, M. Giancarlini, M. Grosso, E. Sanchez, M. Sonza Reorda
    ETS 2009: 14th IEEE European Test Symposium, Sevilla, Spain, 2009, pp. 93-98
  16. Effective Diagnostic Pattern Generation Strategy for Transition-Delay Faults in Full-scan SoCs
    D. Appello, P. Bernardi, M. Grosso, E. Sanchez, M. Sonza Reorda
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 17, NO. 11, p. 1654-1659, NOVEMBER 2009
  17. A Deterministic Methodology for Identifying Functionally Untestable Path-Delay Faults in Microprocessor Cores
    P. Bernardi, M. Grosso, E. Sanchez, M. Sonza Reorda
    MTV'08: 9th International Workshop on Microprocessor Test and Verification, Austin (TX), USA, Dec. 8-10, 2008, pp. 103-108
  18. An Automatic Functional Stress Pattern Generation Technique Suitable for SoC Reliability Characterization
    D. Appello, P. Bernardi, M. Bruno, R. Cagliesi, M. Giancarlini, M. Grosso, E. Sanchez, M. Sonza Reorda
    2nd IEEE International Workshop on Automated Test Equipment: Vision ATE 2020, Santa Clara (CA), USA, October 30-31, 2008
  19. Software-Based Self-Test Strategy for Data Cache Memories Embedded in SoCs
    W. J. Perez H., J. Velasco Medina, D. Ravotto, E. Sanchez, M. Sonza Reorda
    The IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, 2008, pp. 339 - 344
  20. A Hybrid Approach to the Test of Cache Memory Controllers Embedded in SoCs
    W. J. Perez, J. Velasco-Medina, D. Ravotto, E. Sanchez, M. Sonza Reorda
    14th IEEE International On-Line Testing Symposium, 2008, pp. 143-148
  21. An Evolutionary Methodology for Test Generation for Peripheral Cores Via Dynamic FSM Extraction
    D. Ravotto, E. Sanchez, M. Schillaci, G. Squillero
    4th European Workshop on Bio-Inspired Heuristics for Design Automation (EvoHOT2008), March 26-28, 2008, Napoli, Italy, pp. 214-223
  22. An Effective technique for the Automatic Generation of Diagnosis-oriented Programs for Processor Cores
    P. Bernardi, E. Sanchez, M. Schillaci, G. Squillero, M. Sonza Reorda
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008, Vo. 27, No. 3, pp. 570-574, March 2008
  23. Exploiting MOEA to Automatically Generate Test Programs for Path-delay Faults in Microprocessors
    P. Bernardi, K. Christou, M. Grosso, M. Michael, E. Sanchez, M. Sonza Reorda
    4th European Workshop on Bio-Inspired Heuristics for Design Automation (EvoHOT2008), March 26-28, 2008, Napoli, Italy, pp. 224-234
  24. A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions
    K. Christou, M. Michael, P. Bernardi, M. Grosso, E. Sanchez, M. Sonza Reorda
    26th IEEE VLSI Test Symposium (VTS 08), Apr. 27 - May 1, 2008, San Diego, CA, USA, pp. 389 - 394.
  25. Evolutionary Techniques Applied to Hardware Optimization Problems: Test and Verification of Advanced Processors
    E. Sanchez, G. Squillero
    [chapter in] Studies on Computational Intelligence, Vol 66, Advances in Evolutionary Computing for System Design, edited by Lakhmi C. Jain, Vasile Palade and Dipti Srinivasan, Springer publisher, 2007, ISBN 978-3-540-72376-9, pp. 83-106.
  26. Automotive Microcontroller End-of-Line Test via Software-Based Methodologies
    W. Di Palma, D. Ravotto, E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero
    MTV2007: 8th International Workshop on Microprocessor Test and Verification, Austin, December 5-6, 2007, pp. 77 - 82
  27. On Automatic Test Block Generation for Peripheral Testing in SoCs via Dynamic FSMs Extraction.
    D. Ravotto, E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero
    MTV2007: 8th International Workshop on Microprocessor Test and Verification, Austin, December 5-6, 2007, pp. 71 - 76
  28. An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains
    J. Lagos-Benites, D. Appello, P. Bernardi, M. Grosso, D. Ravotto, E. Sanchez, M. Sonza Reorda
    DFT2007, 22th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2007, pp. 291-299
  29. Co-evolution of Test Programs and Stimuli Vectors for Testing of Embedded Peripheral Cores
    L. Bolzani, E. Sanchez, M. Schillaci, G. Squillero
    CEC2007: IEEE Congress on Evolutionary Computation, Singapore, September 25-28, 2007, pp. 3474-3481
  30. A local analysis of an incremental evolutionary tool for processor diagnosis
    D. Ravotto, E. Sanchez, M. Schillaci, G. Squillero
    CEC2007: IEEE Congress on Evolutionary Computation, Singapore, September 25-28, 2007, pp. 3467-3473
  31. Coupling EA and High-level Metrics for the Automatic Generation of Test Blocks for Peripheral Cores
    L.Bolzani, E. Sanchez, M. Schillaci, G. Squillero
    GECCO2007: Genetic and Evolutionary Computation Conference, London, UK, July 7-11, 2007, pp. 1912-1919
  32. On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores
    P. Bernardi, M. Grosso, E. Sanchez, M. Sonza Reorda
    ETS2007: 12th IEEE European Test Symposium, Freiburg, Germany, 2007, pp. 179 - 184
  33. A Software-based Methodology for the Generation of Peripheral Test Sets Based on High-level Descriptions
    L. Bolzani, E. Sanchez, M. Sonza Reorda
    SBCCI2007: IEEE 20th SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, 2007, pp. 348-353
  34. An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores
    L. Bolzani, E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero
    IOLTS2007: IEEE International On-Line Testing Symposium, 2007, pp. 265-270
  35. An Extensible Evolutionary-based General-purpose Optimizer
    E. Sanchez, M. Schillaci, G. Squillero
    IOST3, IEEE International Workshop on Open Source Test Technology Tools, Claremont Resort, Berkeley (CA), USA, May 9-10, 2007
  36. An Enhanced Technique for the Automatic Generation of Effective Diagnosis-oriented Test Programs for Processors
    E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero
    DATE2007: Design, Automation and Test in Europe, April 16-20 2007, pp. 1-6
  37. On Test Program Generation for Peripheral Components in a SoC Resorting to High-Level Metrics
    L. Bolzani, E. Sanchez, M. Sonza Reorda
    LATW2007: 8th IEEE Latin American Test Workshop, Cuzco, Peru, March 11-14, 2007
  38. An Evolutionary Methodology to Enhance Processor Software-Based Diagnosis
    P. Bernardi, E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero
    CEC 2006, IEEE Congress on Evolutionary Computation, Vancouver (BC), Canada, July 16-21, 2006, pp. 859, 864
  39. Enhanced Test Program Compaction Using Genetic Programming
    E. Sanchez, M. Schillaci, G. Squillero
    CEC 2006, IEEE Congress on Evolutionary Computation, Vancouver (BC), Canada, July 16-21, 2006, pp. 865-870
  40. A survey of µGP
    E. Sanchez, M. Schillaci
    SIGEvolution, newsletter of the ACM Special Interest Group on Genetic and Evolutionary Computation, June 2006, vol.1, issue 2, pp. 17-21
  41. µGP an evolutionary test program generator
    G. Squillero, M. Schillaci, E. Sanchez
    IOST3, IEEE International Workshop on Open Source Test Technology Tools, Berkeley (CA), USA, April 30 2006
  42. Evolving Warriors for the Nano Core
    E. Sanchez, M. Schillaci, G. Squillero
    CIG 2006, IEEE Symposium on Computational Intelligence and Games, May 22-24 2006, Reno/Lake Tahoe (AZ), USA, pp. 272-278
  43. Test techniques for advanced processors
    E. Sanchez
    Doctoral Thesis
  44. Efficient Techniques for Automatic Verification-Oriented Test Set Optimization
    E. Sanchez, G. Squillero, M. Sonza Reorda
    International Journal of Parallel Programming, Vol. 34, Num. 1, March 2006, pp. 93 - 109, Ed. Springer Netherlands
  45. An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs
    P. Bernardi, E. Sanchez, M. Schillaci, G. Squillero, M. Sonza Reorda
    IEEE DATE2006: Design, Automation and Test in Europe, 2006, pp. 412-417
    BEST PAPER AWARD at IEEE DATE 2006
  46. Anatomy of an extensible evolutionary tool
    E. Sanchez, M. Schillaci, G. Squillero
    GSICE2: II Giornata di Studio Italiana sul Calcolo Evoluzionistico, 2006
  47. Test Program Generation From High-level Microprocessor Descriptions
    E. Sanchez, M. Sonza Reorda, G. Squillero
    [chapter in] Test and validation of hardware/software systems starting from system-level descriptions, Edited by M. Sonza Reorda, M. Violante, Z. Peng, Springer publisher, 2005, 179 p, ISBN: 1-85233-899-7, pp. 83-106
  48. Diagnosing faulty functional units in processors by using automatically generated test sets
    P. Bernardi, E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero
    MTV'05: 6th International Workshop on Microprocessor Test and Verification, Austin (TX), USA, Nov. 3-4, 2005, pp. 37-41
  49. On the Transformation of Manufacturing Test Sets into On-Line Test Sets for Microprocessors
    E. Sanchez, M. Sonza Reorda, G. Squillero
    DFT'05: The 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 494-502
  50. A modular Architecture for a Populationless Evolutionary Algorithm for MIP
    E. Sanchez, M. Schillaci, G. Squillero
    GSICE: Giornata di Studio Italiana sul Calcolo Evolutivo, 2005
  51. Automatic Generation of Test Sets for SBST of Microprocessor IP Cores
    E. Sanchez, M. Sonza Reorda, G. Squillero, M. Violante
    SBCCI 2005, 18th IEEE Symposium on Integrated Circuits and Systems Design, pp. 74-79
  52. New Evolutionary Techniques for Test-Program Generation for Complex Microprocessor Cores
    E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero, L. Sterpone, M. Violante
    GECCO05: Genetic and Evolutionary Computation Conference, Washington, DC, USA, June 25-29 2005, pp. 2193-2194
  53. Evolving Assembly Programs: How Games Help Microprocessor Validation
    F. Corno, E. Sanchez, G. Squillero
    IEEE Transactions on Evolutionary Computation, Special Issue on Evolutionary Computation and Games, Dec. 2005, vol. 9, pp. 695-706
    SILVER MEDAL at the Human-Competitive Awards 2005 (HUMIES)
  54. Integrating BIST techniques for on-line SoC testing
    A. Manzone, P. Bernardi, M. Grosso, M. Rebaudengo, E. Sanchez, M. Sonza Reorda
    IOLTS 2005: IEEE International On-line Testing Symposium, 2005, pp. 235-240
  55. Automatic Completion and Refinement of Verification Sets for Microprocessor Cores
    E. Sanchez, G. Squillero, M. Sonza Reorda
    Lecture Notes in Computer Science, Vol 3449, "Applications on Evolutionary Computing: EvoWorkkshops 2005", Lausanne (CH), March 2005, pp. 205-214
  56. Automatic Test Program Generation for Verifyng Microprocessors
    F. Corno, E. Sanchez, M. Sonza Reorda, G. Squillero
    IEEE Potentials, Vol 24, Issue 1, Feb-Mar 2005, pp. 34-37
  57. Automatic Verification of RT-Level Microprocessor Cores Using Behavioral Specifications: a Case Study
    L. Anghel, E. Sanchez, M. Sonza Reorda, G. Squillero, R. Velazco
    XIX Conference on Design of Circuits and Integrated Systems, Bordeaux, France, November 24-26, 2004
  58. Coupling Different Methodologies to Validate Obsolete Microprocessors
    L. Anghel, E. Sanchez, M. Sonza Reorda, G. Squillero, R. Velazco
    DFT'04: The 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
  59. Automatic Test Programs Generation Driven by Internal Performance Counters
    W. Lindsay , E. Sanchez, M. Sonza Reorda, G. Squillero
    MTV'04: 5th International Workshop on Microprocessor Test and Verification, pp. 8-13
  60. Code Generation for Functional Validation of Pipelined Microprocessors
    F. Corno, E. Sanchez, M. Sonza Reorda, G. Squillero
    Journal of Electronic Testing: Theory and Applications, Vol 20(3), June 2004, pp. 269-278
  61. A Local Analysis of the Genotype-Fitness Mapping in Hardware Optimization Problems
    E. Sanchez, G. Squillero, M. Violante
    CEC2004, Congress on Evolutionary Computation, Portland (Oregon), June 20-23, 2004, pp. 871-878
  62. On The Evolution of Corewar Warriors
    F. Corno, E. Sanchez, G. Squillero
    CEC2004, Congress on Evolutionary Computation, Portland (Oregon), June 20-23, 2004, pp. 2365-2371
  63. Automatic Test Program Generation - a Case Study
    F. Corno, E. Sanchez, M. Sonza Reorda, G. Squillero
    IEEE Design & Test, Special issue on Functional Verification and Testbench Generation, Volume: 21, Issue 2, March-April 2004, pp. 102-109
  64. Exploiting HW Acceleration for Classifying Complex Test Program Generation Problems
    E. Sanchez, G. Squillero, M. Violante
    of Evolutionary Computing: EvoWorkshops 2004 proceedings, Coimbra (Portugal), April 5-7 2004, pp. 230-239
  65. Exploiting Co-Evolution and a Modified Island Model to Climb the Core War Hill
    F. Corno, E. Sanchez, G. Squillero
    CEC03: 2003 IEEE Congress on Evolutionary Computation, Canberra, Australia, 8th - 12th December 2003, pp. 2222-2229