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Papers by F. Corno

  1. Publishing LO(D)D: Linked Open (Dynamic) Data for Smart Sensing and Measuring Environments
    F. Razzak, F. Corno
    ANT 2012, The 3rd International Conference on Ambient Systems, Networks and Technologies
  2. spChains: A Declarative Framework for Data Stream Processing in Pervasive Applications
    D. Bonino, F. Corno
    ANT 2012, The 3rd International Conference on Ambient Systems, Networks and Technologies
  3. dWatch: a Personal Wrist Watch for Smart Environments
    D. Bonino, F. Corno, L. De Russis
    ANT 2012, The 3rd International Conference on Ambient Systems, Networks and Technologies
  4. Home Energy Consumption Feedback: A User Survey.
    D. Bonino, F. Corno, L. De Russis
    Energy and Buildings, Elsevier, ISSN 0378-7788, Volume 47, April 2012, Pages 383–393
  5. DoMAIns: Domain-based Modeling for Ambient Intelligence
    D. Bonino, F. Corno
    Pervasive and Mobile Computing, IEEE
  6. DOGeye: Controlling your Home with Eye Interaction
    D. Bonino, E. Castellina, F. Corno, L. De Russis
    Interacting with Computers, Elsevier, ISSN: 0953-5438
  7. Tecnologie per la disabilità nella formazione ingegneristica di base
    M. Bellomo, F. Corno, C. Ferraresi
    Didamatica 2011, Informatica e Didattica, Torino (IT), 4-6 may 2011
  8. La formazione a distanza al Politecnico di Torino: nuovi modelli e strumenti
    S. Barbagallo, R. Bertonasco, F. Corno, M. Mezzalama, M. Sonza Reorda, E. Venuto
    Didamatica 2011, Informatica e Didattica, Torino (IT), 4-6 may 2011
  9. Formal Verification of Device State Chart Models
    F. Corno, M. Sanaullah
    IE'11, The 7th International Conference on Intelligent Environments, Nottingham (UK), 25-28 July 2011
  10. Modeling, Simulation and Emulation of Intelligent Domotic Environments
    D. Bonino, F. Corno
    Automation in Construction, ISSN: 0926-5805, ELSEVIER
  11. Enabling Machine Understandable Exchange of Energy Consumption Information in Intelligent Domotic Environments
    D. Bonino, F. Corno, F. Razzak
    Energy & Buildings 43 (2011), Elsevier, ISSN 0378-7788, pp. 1392-1402
  12. What Would You Ask to Your Home if It Were Intelligent? Exploring User Expectations about Next-Generation Homes
    D. Bonino, F. Corno
    JOURNAL OF AMBIENT INTELLIGENCE AND SMART ENVIRONMENTS, ISSN 1876-1364
  13. A User-Friendly Interface for Rules Composition in Intelligent Environments
    D. Bonino, F. Corno, L. De Russis
    ISAMI 2011, International Symposium on Ambient Intelligence, Salamanca (Spain), 6th - 8th April 2011
  14. Design time Methodology for the Formal Verification of Intelligent Domotic Environments
    F. Corno, M. Sanaullah
    ISAMI 2011, International Symposium on Ambient Intelligence, Salamanca (Spain), 6th - 8th April 2011
  15. Mobile Interaction with Smart Environments through Linked Data
    D. Bonino, F. Corno, F. Razzak
    SMC 2010, 2010 IEEE International Conference on Systems, Man, and Cybernetics, October 10-13, 2010, Istanbul, Turkey, pp. 2922-2929
  16. DogSim: A State Chart Simulator for Domotic Environments
    D. Bonino, F. Corno
    Eighth Annual IEEE International Conference on Pervasive Computing and Communications Workshops (PerCom Workshops)
  17. Rule-based Intelligence for Domotic Environments
    D. Bonino, F. Corno
    Automation in Construction, vol. 19; p. 183-196, ISSN: 0926-5805, ELSEVIER
  18. Sistema e metodo per la classificazione di contenuti
    F. Corno, P. Pellegrino, A. Ciaramella
    Italian Patent Application n. TO2009A000704, owned by Politecnico di Torino and Intellisemantic
  19. Interoperation Modeling for Intelligent Domotic Environments
    D. Bonino, F. Corno
    3rd European Conference on Ambient Intelligence
  20. FaSet: A Set Theory Model for Faceted Search
    D. Bonino, F. Corno, L. Farinetti
    Proc. 2009 IEEE/WIC/ACM International Joint Conference on Web Intelligence
  21. Automatic Domotic Device Interoperation
    D. Bonino, E. Castellina, F. Corno
    IEEE TRANSACTIONS ON CONSUMER ELECTRONICS. vol. 55/2 ISSN: 0098-3063
  22. Technology Independent Interoperation of Domotic Devices through Rules
    D. Bonino, E. Castellina, F. Corno, M. Liu
    The 13th IEEE International Symposium on Consumer Electronics, IEEE (USA), Kyoto, Japan May 25-28, 2009
  23. Speech and Gaze Control for Desktop Environments
    E. Castellina, F. Corno, P. Pellegrino
    [chapter in] Multimodal Human Computer Interaction and Pervasive Services, edited by P. Grifoni, Information Science Reference (USA), ISBN: 978-1-60566-386-9
  24. Review of the State-of-the-art in Patent Information and Forthcoming Evolutions in Intelligent Patent Informatics
    D. Bonino, F. Corno, A. Ciaramella
    World Patent Information - ISSN: 0172-2190
  25. Uniform Access to Domotic Environments through Semantics
    D. Bonino, E. Castellina, F. Corno
    SWAP 2008 - Fifth Workshop on Semantic Web Applications and Perspective
  26. The DOG Gateway: Enabling Ontology-based Intelligent Domotic Environments
    D. Bonino, E. Castellina, F. Corno
    IEEE TRANSACTIONS ON CONSUMER ELECTRONICS. vol. 54/4 ISSN: 0098-3063, pp. 1656-1664
  27. Ancore e TAG, la logica dell'interoperabilita' tra archivi eterogenei di materiale multimediale
    F. Corno, P. Pellegrino
    [chapter in] Interfacce della memoria - Social media e patrimoni documentali online, edited by M. Ricciardi, ScriptaWeb, Napoli (IT), 2008, ISBN 978-88-6381-006-6, pp. 75-88
  28. Multimodal Gaze Interaction in 3D Virtual Environments
    E. Castellina, F. Corno
    COGAIN 2008 Communication, Environment and Mobility Control by Gaze ISBN: 978-80-01-04151-2
  29. Understanding users and their needs
    M. Donegan, J.D. Morris, F. Corno, I. Signorile, A. Chio', V. Pasian, A. Vignola, M. Buchholz, E. Holmqvist
    UNIVERSAL ACCESS IN THE INFORMATION SOCIETY. vol. 8/4 ISSN: 1615-5289.
  30. A blueprint for integrated eye-controlled environments
    D. Bonino, E. Castellina, F. Corno, A. Gale, A. Garbo, K. Purdy, F. Shi
    UNIVERSAL ACCESS IN THE INFORMATION SOCIETY. vol. 8/4 ISSN: 1615-5289.
  31. DOG: an Ontology-Powered OSGi Domotic Gateway
    D. Bonino, E. Castellina, F. Corno
    20th IEEE Int'l Conference on Tools with Artificial Intelligence
  32. DogOnt - Ontology Modeling for Intelligent Domotic Environments
    D. Bonino, F. Corno
    7th International Semantic Web Conference. October 26-30, 2008. Karlsruhe, Germany. Ed. Springer-Verlag, Lecture Notes on Computer Science, pp. 790-803
  33. Self-Similarity metric for Index Pruning in Conceptual Vector Space Models
    D. Bonino, F. Corno
    19th International Conference on Database and Expert Systems Applications-DEXA 2008, 9th International Workshop on Web Semantics (WebS 2008), Ed. IEEE, pp.225-229
  34. Eye Tracking Impact on Quality-of-Life of ALS Patients
    A. Calvo, A. Chio', E. Castellina, F. Corno, L. Farinetti, P. Ghiglione, V. Pasian, A. Vignola
    11th International Conference on Computers Helping People with Special Needs, Linz, Austria 9/7/2008 - 11/7/2008
  35. Integrated Speech and Gaze Control for Realistic Desktop Environments
    E. Castellina, F. Corno, P. Pellegrino
    ETRA '08: Proceedings of the 2008 symposium on Eye Tracking Research & Applications
  36. Versatile RDF Representation for Multimedia Semantic Search
    D. Bonino, F. Corno, P. Pellegrino
    IEEE International Conference on Tools with Artificial Intelligence, ICTAI '07
  37. Accessible Web Surfing through gaze interaction
    E. Castellina, F. Corno
    COGAIN 2007: Gaze-based Creativity, Interacting with Games and On-line Communities
  38. A Reusable 3D Visualization Component for the Semantic Web
    A. Bosca, D. Bonino, M. Comerio, S. Grega, F. Corno
    Web3D 2007 Symposium, pp. 89-96
  39. On-the-fly Construction of Web Services Compositions from Natural Language Requests
    A. Bosca, F. Corno, G. Valetto, R. Maglione
    JOURNAL OF SOFTWARE, pp. 40-50, 2006, Vol. 1(1), ISSN: 1796-217X
  40. Domotic House Gateway
    P. Pellegrino, D. Bonino, F. Corno
    SAC 2006, ACM Symposium on Applied Computing, April 23-27, 2006, Dijon, France
  41. Specifying Web Service Compositions on the Basis of Natural Language Requests
    A. Bosca, G. Valetto, R. Maglione and F. Corno
    3rd International Conference on Service Oriented Computing
  42. Composing Web Services on the Basis of Natural Language Requests
    A. Bosca, A. Ferrato, F. Corno, I. Congiu, G. Valetto
    IEEE International Conference on Web Services (ICWS'05)
  43. Evolving Assembly Programs: How Games Help Microprocessor Validation
    F. Corno, E. Sanchez, G. Squillero
    IEEE Transactions on Evolutionary Computation, Special Issue on Evolutionary Computation and Games, Dec. 2005, vol. 9, pp. 695-706
    SILVER MEDAL at the Human-Competitive Awards 2005 (HUMIES)
  44. Automatic Test Program Generation for Verifyng Microprocessors
    F. Corno, E. Sanchez, M. Sonza Reorda, G. Squillero
    IEEE Potentials, Vol 24, Issue 1, Feb-Mar 2005, pp. 34-37
  45. Multiple Low-cost Cameras for Effective Head and Gaze Tracking
    F. Corno, A. Garbo
    11th International Conference on Human-Computer Interaction, Las Vegas, USA, July 2005
  46. Automatic learning of text-to-concept mappings exploiting WordNet-like lexical networks
    D. Bonino, F. Corno, F. Pescarmona
    20th Annual ACM Symposium on Applied Computing Santa Fe, New Mexico, March 13 -17, 2005
  47. Validation of the dependability of CAN-based networked systems
    F. Corno, J. Perez, M. Ramasso, M. Sonza Reorda, M. Violante
    IEEE High-level Design Validation and Test Workshop, pp. 161-164, 2004
  48. A multi-level approach to the dependability analysis of CAN networks for automotive applications
    F. Corno, J. Perez, M. Ramasso, M. Sonza Reorda, M. Violante
    International Conference Integrated Chassis Control(ICC), 10-12, Nov. 2004
  49. Evolutionary Simulation-Based Validation
    F. Corno, M. Sonza Reorda, G. Squillero
    International Journal on Artificial Intelligence Tools (IJAIT), Vol. 14, 1-2, Dec. 2004, pp. 897 916
  50. H-DOSE: an Holistic Distributed Open Semantic Elaboration Platform
    D. Bonino, A. Bosca, F. Corno, L. Farinetti, F. Pescarmona
    SWAP2004: 1st Italian Semantic Web Workshop 10th December 2004, Ancona, Italy
  51. Ontology Driven Semantic Search
    D. Bonino, F. Corno, L. Farinetti, A. Bosca
    WSEAS Transaction on Information Science and Application, Issue 6, Volume 1, December 2004, pp. 1597-1605
  52. Ontology Driven Semantic Search
    D. Bonino, F. Corno, L. Farinetti, A. Bosca
    WSEAS Conference ICAI 2004, Venice, Italy, 2004.
  53. Domain Specific Searches using Conceptual Spectra
    D. Bonino, F. Corno, L. Farinetti
    ICTAI 2004 the IEEE International Conference on Tools with Artificial Intelligence, 15-17 Nov 2004, Boca Raton, Florida, USA, pp.680-687.
  54. Evaluating the effects of transient faults on vehicle dynamic performance in automotive systems
    F. Corno, F. Esposito, M. Sonza Reorda, S.Tosato
    ITC2004: IEEE International Test Conference, Charlotte (NC), USA, October 24-30, 2004, pp. 1332-1339
  55. E-Learning Issues for Advanced Technical Topics
    F. Corno
    EduTech2004 workshop, IFIP WorldComputerCongress, August 2004, Toulouse, France
  56. Impact of Technology on Learning Paradigms and Teaching Practices
    F. Corno, T. Ebey, A. Grabowska, I. Nikolova, E. Sendova
    EduTech2004 workshop, IFIP WorldComputerCongress, August 2004, Toulouse, France
  57. A multi-level approach to the dependability analysis of networked systems based on the CAN protocol
    F. Corno, J. Perez, M. Sonza Reorda, M. Violante
    SBCCI04: IEEE Symposium on Integrated Circuits and Systems Design, 2004, pp. 71-75
  58. Code Generation for Functional Validation of Pipelined Microprocessors
    F. Corno, E. Sanchez, M. Sonza Reorda, G. Squillero
    Journal of Electronic Testing: Theory and Applications, Vol 20(3), June 2004, pp. 269-278
  59. On The Evolution of Corewar Warriors
    F. Corno, E. Sanchez, G. Squillero
    CEC2004, Congress on Evolutionary Computation, Portland (Oregon), June 20-23, 2004, pp. 2365-2371
  60. Dynamic Optimization of Semantic Annotation Relevance
    D. Bonino, F. Corno, G. Squillero
    CEC2004, Congress on Evolutionary Computation, Portland (Oregon), June 20-23, 2004
  61. An Agent Based Autonomic Semantic Platform
    D. Bonino, A. Bosca, F. Corno
    ICAC2004, First International Conference on Autonomic Computing (IEEE), New York, May 17-18, 2004
  62. Automatic Test Program Generation - a Case Study
    F. Corno, E. Sanchez, M. Sonza Reorda, G. Squillero
    IEEE Design & Test, Special issue on Functional Verification and Testbench Generation, Volume: 21, Issue 2, March-April 2004, pp. 102-109
  63. A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques
    D. Appello, A. Fudoli, V. Tancorre, P. Bernardi, F. Corno, M. Rebaudengo, M. Sonza Reorda
    Journal of Electronic Testing: Theory and Applications, Volume 20, Issue 1, Kluwer Academic Publishers, Feb 2004, pp. 79-87
  64. Multilingual Semantic Elaboration in the DOSE platform
    D. Bonino, F. Corno, L. Farinetti, A. Ferrato
    SAC 2004, ACM Symposium on Applied Computing, March 14-17, 2004, Nicosia, Cyprus
  65. Relating Vehicle-level and Network-level Reliability through High-level Fault Injection
    F. Corno, P. Gabrielli, S. Tosato
    HLDVT2003: IEEE International Workshop on High Level Design Validation and Test, 2003
  66. Exploiting Co-Evolution and a Modified Island Model to Climb the Core War Hill
    F. Corno, E. Sanchez, G. Squillero
    CEC03: 2003 IEEE Congress on Evolutionary Computation, Canberra, Australia, 8th - 12th December 2003, pp. 2222-2229
  67. Dynamic Prediction of Web Requests
    D. Bonino, F. Corno, G. Squillero
    CEC03: 2003 IEEE Congress on Evolutionary Computation, Canberra, Australia, 8th - 12th December 2003, pp. 2034-2041
  68. DOSE: a Distributed Open Semantic Elaboration Platform
    D. Bonino, F. Corno, L. Farinetti
    ICTAI 2003, The 15th IEEE International Conference on Tools with Artificial Intelligence, November 3-5, 2003, Sacramento, California
  69. Semantic annotation and search at the document substructure level
    D. Bonino, F. Corno, L. Farinetti
    poster at ISWC2003 - 2nd International Semantic Web Conference, Florida (USA), October 2003
  70. System-level Analysis of Fault Effects in an Automotive Environment
    F. Corno, P. Gabrielli, S. Tosato
    DFT2003: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
  71. Code Generation for Functional Validation of Pipelined Microprocessors
    F. Corno, G. Squillero, M. Sonza Reorda
    ETW03: 8th IEEE European Test Workshop (Formal Proceedings), The Netherlands, May 25 28, 2003, pp. 113-118
  72. A Real-Time Evolutionary Algorithm for Web Prediction
    D. Bonino, F. Corno, G. Squillero
    WI-2003, The 2003 IEEE/WIC International Conference on Web Intelligence, October 2003, Halifax, Canada
  73. UML-Based System-Level specifications for integrated systems
    F. Corno, P. Maggiore, G. Repici, A. Sorniotti, E. Suraci, S. Tosato, M. Velardocchia
    9th EAEC International Congress, "European Automotive Industry Driving Global Changes"
  74. An Evolutionary Approach to Web Request Prediction
    D. Bonino, F. Corno, G. Squillero
    poster at WWW2003 - The Twelfth International World Wide Web Conference, 20-24 May 2003, Budapest, HUNGARY
  75. New Acceleration Techniques for Simulation-Based Fault-Injection
    F. Corno, L. Entrena, C. Lopez, M. Sonza Reorda, G. Squillero
    [chapter in] Fault Injection Techniques and Tools for Embedded Systems Reliability Evaluation, edited by, A. Benso, P. Prinetto, ISBN 1 4020 7589 8, October 2003, pp. 217-230
  76. An Enhanced Framework for Microprocessor Test-Program Generation
    F. Corno, G. Squillero
    EUROGP2003: 6th European Conference on Genetic Programming, Essex (UK), April 14-16, 2003, pp. 307-315
  77. Exploiting Auto-Adaptive µGP for Highly Effective Test Programs Generation
    F. Corno, G. Squillero
    ICES2003: The 5th International Conference on Evolvable Systems: From Biology to Hardware, Trondheim (Norway), March 17-20, 2003, pp. 262-273
  78. Automatic Test Program Generation for Pipelined Processors
    F. Corno, M. Sonza Reorda, G. Squillero
    SAC2003: The Eighteenth Annual ACM Symposium on Applied Computing, Melbourne, Florida (USA), March 9-12, 2003, pp. 736-740
  79. Fully Automatic Test Program Generation for Microprocessor Cores
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    DATE2003: Design, Automation and Test in Europe, Munich, Germany, March 3-7, 2003, pp. 1006-1011
  80. A New Evolutionary Paradigm for Cultivating Cellular Automata for Built-In Self Test of Sequential Circuits
    F. Corno, M. Sonza Reorda, G. Squillero
    [chapter in] Evolutionary Algorithms for Embedded System Design , edited by R. Drechsler and N. Drechsler, Kluwer Academic Publishers, October 2002, ISBN 1-4020-7276-7, pp.? 143-173
  81. Reducing Test Application Time through Interleaved Scan
    F. Corno, M. Sonza Reorda, G. Squillero
    SBCCI2002: 15th IEEE Symposium on Integrated Circuits and Systems Design, Porto Alegre (Brasil), Septempber 2002, pp. 89-94
    Outstanding Paper Award
  82. Initializability Analysis of Synchronous Sequential Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, G. Squillero
    ACM Transactions on Design Automation of Electronic Systems, April 2002, pp. 249-264
  83. Evolutionary Test Program Induction for Microprocessor Design Verification
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    ATS2002: IEEE Asian Test Symposium, Guam (USA), November 2002, pp. 368-373
  84. Analysis of the Equivalences and Dominances of Transient Faults at the Register-Transfer Level
    L. Berrojo, F. Corno, L. Entrena, I. Gonz lez, C. Lopez, M. Sonza Reorda, G. Squillero
    IOLTW2002: IEEE International On-line Testing Workshop, 2002, pp. 193
  85. A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques
    D. Appello, A. Fudoli, V. Tancorre, F. Corno, M. Rebaudengo, M. Sonza Reorda
    IOLTW2002: IEEE International On-line Testing Workshop, 2002, pp. 112-116
  86. Hypervideo: a Parameterized Hotspot Approach
    F. Bota, F. Corno, L. Farinetti
    ICWI2002: IADIS International Conference WWW/Internet 2002, November 13-15, 2002 - Lisbon, Portugal
  87. A Cost-Effective Solution for Eye-Gaze Assistive Technology
    F. Corno, L. Farinetti, I. Signorile
    ICME2002: IEEE International Conference on Multimedia and Expo, Lausanne, Switzerland
  88. An eye-gaze input device for people with severe motor disabilities
    F. Corno, L. Farinetti, I. Signorile
    SSGRR-2002s: International Conference on Advances in Infrastructure for e-Business, e-Education, e-Science, and e-Medicine on the Internet, L'Aquila (I), August 2002
  89. Efficient Machine-Code Test-Program Induction
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    CEC2002: Congress on Evolutionary Computation, Honolulu, Hawaii (USA), pp. 1486-1491
  90. An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation
    L. Berrojo, F. Corno, L. Entrena, I. Gonz lez, C. Lopez, M. Sonza Reorda, G. Squillero
    VTS2002: 20th IEEE VLSI Test Symposium, Monterey, CA (USA), 28 April - 2 May, 2002, pp. 229-236
  91. Evolutionary Techniques for Minimizing Test Signals Application Time
    F. Corno, M. Sonza Reorda, G. Squillero
    EvoIASP2002: 4rd European Workshop on Evolutionary Computation applications to Image Analysis and Signal Processing, Kinsale (Ireland), April 2002, pp. 183-189
  92. Automatic Test Program Generation from RT-level Microprocessor Descriptions
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    ISQED2002: 3rd International Symposium on Quality Electronic Design, March 18-21, 2002, San Jose, California (USA), pp. 120-125
  93. An Evolutionary Algorithm for Reducing Integrated-Circuit Test Application Time
    F. Corno, M. Sonza Reorda, G. Squillero
    SAC2002: 17th ACM Symposium on Applied Computing, March 2002, Madrid (Spain), pp. 608-611
  94. New Techniques for Speeding-up Fault-injection Campaigns
    L. Berrojo, I. Gonz lez, F. Corno, M. Sonza Reorda, G. Squillero, L. Entrena, C. Lopez
    DATE2002: Design, Automation and Test in Europe, Conference and Exhibition, Paris, France, March 4-8, 2002, pp. 847-852
  95. An XML-based Modular Approach for Interactive E-learning
    F. Bota, F. Corno, L. Farinetti
    SSGRR-2002w: International Conference on Advances in Infrastructure for e-Business, e-Education, e-Science, and e-Medicine on the Internet, L'Aquila (I), January 2002
  96. A Transparent Search Agent for Closed Collections
    F. Bota, F. Corno, L. Farinetti, G. Squillero
    SSGRR-2002w: International Conference on Advances in Infrastructure for e-Business, e-Education, e-Science, and e-Medicine on the Internet, L'Aquila (I), January 2002
  97. Devising an RT-Level ATPG for uProcessor Cores
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    WRTLT2001: 2nd Worshop on RTL, ATPG & DFT, Nara, Japan, November 22-23, 2001
  98. A P1500 compliant BIST-based approach to embedded RAM Diagnosis
    D. Appello, F. Corno, M. Giovinetto, M. Rebaudengo, M. Sonza Reorda
    ATS, IEEE Asian Test Symposium, 2001
  99. Effective Techniques for High-Level ATPG
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    ATS2001: IEEE Asian Test Symposium, 2001, pp. 225-230
    Best Paper Award
  100. An Interpretation Framework for Evaluating High-Level Fault Models and ATPG Capabilities
    F. Corno, M. Sonza Reorda, G. Squillero
    DCIS2001: Design of Circuits and Integrated Systems, 2001, pp. 273-278
  101. ARPIA: a High-Level Evolutionary Test Signal Generator
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    EvoIASP2001: 3rd European Workshop on Evolutionary Computation applications to Image Analysis and Signal Processing, Como (Italy), April 20, 2001, pp. 298-306
  102. Interactive Visit of a Website
    F. Bota, L. Farinetti, F. Corno
    WebNet 2001 World Conference on the WWW and Internet, Florida (USA), October 2001
  103. Easy Implementation of Web-based Multimedia Courses: Using Synchronized Video Content in Distance Education
    F. Bota, L. Farinetti, F. Corno
    Romanian Internet Learning Workshop "Internet as a Vehicle for Teaching" - Fifth Edition, 11-18 August 2001, Sumuleu-Ciuc, Romania
  104. XML Based database courseware
    F. Bota, F. Corno, L. Farinetti
    ICDE 2001 - 20th world conference on open learning and distance education, Duesseldorf (Germany), 01-05 April 2001
  105. Synchronized Multimedia use in Distance Education
    F. Bota, F. Corno, L. Farinetti
    ICDE 2001 - 20th world conference on open learning and distance education, Duesseldorf (Germany), 01-05 April 2001
  106. On the Test of Microprocessor IP Cores
    F. Corno, M. Sonza Reorda, G. Squillero, M. Violante
    DATE2001: IEEE Design, Automation & Test in Europe Conference, Munich (Germany), 13-16 March 2001, pp. 209-213
  107. Evolving Effective CA/CSTP BIST Architectures for Sequential Circuits
    F. Corno, M. Sonza Reorda, G. Squillero
    SAC2001: 16th ACM Symposium on Applied Computing, March 2001, Las Vegas (USA), pp. 345-350
  108. GA-Based Verification of Network Protocols Performance
    M. Baldi, F. Corno, M. Rebaudengo, M. Sonza Reorda, G. Squillero
    [chapter in] Telecommunications Optimizations: Heuristic and Adaptive Techniques, edited by D. Corne and M. Oates, Wiley and Sons, August 2000, ISBN 0-471-98855-3, pp. 185-198
  109. A Genetic Algorithm-based System for Generating Test Programs for Microprocessor IP Cores
    F. Corno, M. Sonza Reorda, G. Squillero, M. Violante
    ICTAI2000: The Twelfth IEEE International Conference on Tools with Artificial Intelligence, Vancouver, British Columbia, Canada, November 13-15, 2000, pp. 195-198
  110. An RT-level Fault Model with High Gate Level Correlation
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    HLDVT2000: IEEE International High Level Design Validation Workshop, The Claremont Resort & Spa, Berkeley, California, November 8-10 2000
  111. RT-level Fault Simulation Techniques based on Simulation Command Scripts
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    DCIS2000: XV Conference on Design of Circuits and Integrated Systems, Le Corum, Montpellier, November 21-24, 2000, pp. 825-830
  112. RT-Level ITC 99 Benchmarks and First ATPG Results
    F. Corno, M. Sonza Reorda, G. Squillero
    IEEE Design & Test of Computers, July-August 2000, pp. 44-53
  113. An Intelligent User Interface oriented to non-expert users
    F. Corno, L. Farinetti, G. Squillero
    WebNet2000: World Conference on the WWW and Internet, San Antonio, Texas (USA), October 2000, pp. 675-676
  114. Enhancing Interactivity for Self-Evaluation in XML-Based Coureware
    F. Bota, F. Corno, L. Farinetti
    WebNet2000: World Conference on the WWW and Internet, San Antonio, Texas (USA), October 2000
  115. Student Knowledge Evaluation in Internet Environments
    F. Bota, L. Farinetti, F. Corno
    Romanian Internet Learning Workshop "Internet as a Vehicle for Teaching" - Fourth Edition, 26 June-8 July 2000, Sumuleu-Ciuc, Romania
  116. Archivi on-line fruibili da utenti inesperti: un'esperienza nel campo della disabilità
    F. Corno, G. Squillero
    Didamatica2000: Convegno AICA sull'Informatica per la Didattica, Cesena (I), May 2000, pp. 181-187
  117. Exploiting the Selfish Gene Algorithm for Evolving Cellular Automata
    F. Corno, M. Sonza Reorda, G. Squillero
    IJCNN2000: IEEE-INNS-ENNS International Joint Conference Neural Networks, Como (I), July 2000, pp. 577-581
  118. Exploiting the Selfish Gene Algorithm for Evolving Hardware Cellular Automata
    F. Corno, M. Sonza Reorda, G. Squillero
    CEC2000: Congress on Evolutionary Computation, San Diego (USA), July 2000, pp. 1401-1406
  119. An Improved Cellular Automata-Based BIST Architecture for Sequential Circuits
    F. Corno, M. Sonza Reorda, G. Squillero
    ISCAS2000: IEEE International Symposium on Circuits and Systems, Geneve (CH), May 2000, pp. 76-79
  120. CA-CSTP: A new BIST Architecture for Sequential Circuits
    F. Corno, M. Sonza Reorda, G. Squillero, M. Violante
    ETW2000: European Test Workshop, May 2000, pp. 167-172
  121. Low Power BIST via Hybrid Cellular Automata
    F. Corno, M. Rebaudengo, M. Sonza Reorda, G. Squillero, M. Violante
    VTS2000: 18th IEEE VLSI Test Symposium, Montreal, Canada, May 2000, pp. 29-34
  122. High-Level Observability for Effective High-Level ATPG
    F. Corno, M. Sonza Reorda, G. Squillero
    VTS2000: 18th IEEE VLSI Test Symposium, Montreal, Canada, May 2000, pp. 411-416
  123. Evolving Cellular Automata for Self-Testing Hardware
    F. Corno, M. Sonza Reorda, G. Squillero
    ICES2000: Third International Conference on Evolvable Systems: From Biology to Hardware, Edinburgh (UK), April 2000, pp. 31-39
  124. Prediction of Power Requirements for High-Speed Circuits
    F. Corno, M. Rebaudengo, M. Sonza Reorda, G. Squillero, M. Violante
    EvoTel2000: European Workshops on Telecommunications, Edinburgh (UK), May 2000, pp. 247-254
  125. Automatic Validation of Protocol Interfaces Described in VHDL
    F. Corno, M. Sonza Reorda, G. Squillero
    EvoTel2000: European Workshops on Telecommunications, Edinburgh (UK), May 2000, pp. 205-213
  126. Automatic Test Bench Generation for Validation of RT-level Descriptions: an Industrial Experience
    F. Corno, A. Manzone, A. Pincetti, M. Sonza Reorda, G. Squillero
    DATE2000: Design, Automation and Test in Europe, Paris (F), March 2000, pp. 385-389
  127. Optimal Vector Selection for Low Power BIST
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DFT99: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, November 1-3 1999 - Albuquerque, New Mexico (USA), pp. 219-226
  128. High Quality Test Pattern Generation for RT-level VHDL Descriptions
    F. Corno, M. Sonza Reorda, G. Squillero
    MTV99: 2nd International Workshop on Microprocessor Test and Verification Common Challenges and Solutions, Atlantic City (USA), September 1999
  129. On Reducing the Peak Power Consumption of Test Sequences
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    European Conference on Circuit Theory and Design, Stresa, Italy, August 1999, pp. 247-250
  130. A Peak-Power Estimation Algorithm for Sequential Circuits
    F. Corno, M. Rebaudengo, M. Sonza Reorda, V. Speranza, M. Violante
    European Conference on Circuit Theory and Design, Stresa, Italy, August 1999, pp. 896-899
  131. Simulation-Based Sequential Equivalence Checking of RTL VHDL
    F. Corno, M. Sonza Reorda, G. Squillero
    ICECS99: 6th IEEE International Conference on Electronics, Circuits and Systems, Paphos, Cyprus, September 1999, pp. 351-354
  132. Verifying the Equivalence of Sequential Circuits with Genetic Algorithms
    F. Corno, M. Sonza Reorda, G. Squillero
    CEC99: 1999 Congress on Evolutionary Computation, Washington DC (USA), July 1999, pp. 1293-1297
  133. Optimizing Deceptive Functions with the SG-Clans Algorithm
    F. Corno, M. Sonza Reorda, G. Squillero
    CEC99: 1999 Congress on Evolutionary Computation, Washington DC (USA), July 1999, pp. 2190-2195
  134. A New BIST Architecture for Low Power Circuits
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    ETW99: IEEE European Test Workshop, Konstanz(D), May 1999
  135. Test Pattern Generation under Low Power Constraints
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    R. Poli, H-M. Voigt, S. Cagnoni, D. Corne, G. Smith, T. Fogarty (eds.), Evolutionary Image Analysis, Signal Processing and Telecommunications First European Workshops, EvoIASP'99 and EuroEcTel'99 Goteborg, Sweden, May 1999 Joint Proceedings, Springer LNCS, 1999, pp. 162-170
  136. Approximate Equivalence Verification for Protocol Interface Implementation via Genetic Algorithms
    F. Corno, M. Sonza Reorda, G. Squillero
    EuroEcTel99: R. Poli, H-M. Voigt, S. Cagnoni, D. Corne, G. Smith, T. Fogarty (eds.), Evolutionary Image Analysis, Signal Processing and Telecommunications First European Workshops, EvoIASP'99 and EuroEcTel'99 Goteborg, Sweden, May 1999 Joint Proceedings, Springer LNCS, 1999, pp. 182-192
    Special Jury Award for Outstanding Work Presented by a Student or Young Researcher
  137. RT-level TPG Exploiting High-Level Synthesis Information
    S. Chiusano, F. Corno, P. Prinetto
    17th IEEE VLSI Test Symposium, Dana Point (USA), April 1999
  138. ALPS: A Peak Power Estimation Tool for Sequential Circuits
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    GLS-VLSI99: 8th Great Lakes Symposium on VLSI, Ypsilanti MI (USA), March 4-6 1999, pp. 350-353
  139. Transformation-based Peak Power Reduction for Test Sequences
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    poster at VOLTA99: IEEE Alessandro Volta Memorial Workshop on Low Power Design, Como (ITALY), March 3-5 1999, pp. 78-83
  140. Approximate Equivalence Verification of Sequential Circuits via Genetic Algorithms
    F. Corno, M. Sonza Reorda, G. Squillero
    DATE99: IEEE Design, Automation & Test in Europe, Munich (Germany), March 1999, pp. 754-755
  141. Integrating Symbolic Techniques in ATPG-Based Sequential Logic Optimization
    E. San Millan, L. Entrena, J. A. Espejo, S. Chiusano, F. Corno
    DATE99: IEEE Design, Automation & Test in Europe, Munich (Germany), March 1999
  142. SymFony: a Hybrid Topological-Symbolic ATPG exploiting RT-level Information
    F. Corno, P. Prinetto, M. Sonza Reorda, M. Violante, U. Glaeser, H. T. Vierhaus
    IEEE Transactions on Computer-Aided Design, February 1999, Vol. 18, No. 2, pp. 191-202
  143. Exploiting Behavioral Information in Gate-Level ATPG
    S. Chiusano, F. Corno, P. Prinetto
    JETTA: The Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers, December 1998
  144. Using BDDs to improve Structural Optimization for Sequential Logic Circuits
    E. San Millan, L. Entrena, J. A. Espejo, S. Chiusano, F. Corno
    DCIS98: XIII Design of Circuits and Integrated Systems Conference, Madrid (Spain), November 1998, pp. 284-289
  145. A Test Pattern Generation Algorithm Exploiting Behavioral Information
    S. Chiusano, F. Corno, P. Prinetto
    ATS98, Asian Test Symposium, Singapore, December 1998
  146. A System for Evaluating On-Line Testability at the RT-level
    S. Chiusano, F. Corno, M. Sonza Reorda, R. Vietti
    DFT98, 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, November 2-4 1998, Austin, Texas
  147. Enhancing Topological ATPG with High-Level Information and Symbolic Techniques
    F. Corno, J. H. Patel, E. M. Rudnick, M. Sonza Reorda, R. Vietti
    ICCD98, International Conference on Circuit Design, Austin, Texas (USA), October 1998
  148. VEGA: A Verification Tool Based on Genetic Algorithms
    F. Corno, M. Sonza Reorda, G. Squillero
    ICCD98, International Conference on Circuit Design, Austin, Texas (USA), October 1998, pp. 321-326
  149. Experiences in the use of evolutionary techniques for testing digital circuits
    F. Corno, M. Sonza Reorda, M. Rebaudengo
    Applications and Science of Neural Networks, Fuzzy Systems, and Evolutionary Computation, SPIE 1998 Annual Meeting
    Invited paper
  150. A Test Pattern Generation methodology for low power consumption
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    VTS98: 16th IEEE VLSI Test Symposium, Monterey, CA (USA), April 1998
  151. On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits
    F. Corno, N. Gaudenzi, P. Prinetto, M. Sonza Reorda
    VTS98: 16th IEEE VLSI Test Symposium, Monterey, CA (USA), April 1998
  152. Algoritmi da taglio
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, S. Bisotto
    La Rivista del Vetro, Miller Freeman ed., Milano (Italy), anno 22, n. 2, marzo 1998, pp. 86-98
  153. A New Evolutionary Algorithm Inspired by the Selfish Gene Theory
    F. Corno, M. Sonza Reorda, G. Squillero
    ICEC98: IEEE International Conference on Evolutionary Computation, May 1998, pp. 575-580
  154. Scan Chain Partitioning and Re-ordering based on Layout Information: an Industrial Experience
    S. Barbagallo, G. Borgonovo, D. Grassi, D. Medina, F. Corno, P. Prinetto, M. Sonza Reorda
    DATE98: Design, Automation and Test in Europe (User Forum), Paris (F), February 1998
  155. Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques
    E. M. Rudnick, R. Vietti, A. Ellis, F. Corno, P. Prinetto, M. Sonza Reorda
    DATE98: Design, Automation and Test in Europe, Paris (F), February 1998
  156. Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection
    F. Corno, P. Prinetto, M. Sonza Reorda, M. Violante
    DATE98: Design, Automation and Test in Europe, Paris (F), February 1998
  157. The Selfish Gene Algorithm: a New Evolutionary Optimization Strategy
    F. Corno, M. Sonza Reorda, G. Squillero
    SAC98: 13th Annual ACM Symposium on Applied Computing, Atlanta, Georgia (USA), February 1998, pp. 349-355
  158. The General Product Machine: a New Model for Symbolic FSM Traversal
    G. Cabodi, P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda
    Formal Methods in Systems Design, Kluwer Academic Publishers, N. 12, 1998, pp. 267-289
  159. Integrating Online and Offline Testing of a Switching Memory
    S. Barbagallo, F. Corno, D. Medina, P. Prinetto, M. Sonza Reorda
    IEEE Design & Test of Computers, January-March 1998
  160. GA-based Performance Analysis of Network Protocols
    M. Baldi, F. Corno, M. Rebaudengo, G. Squillero
    ICTAI97: 9th IEEE International Conference on Tools with Artificial Intelligence, Newport Beach, CA (USA), November 1997, pp. 118-124
  161. Exploiting Symbolic Techniques within Genetic Algorithms for Power Optimization
    S. Chiusano, F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    ICTAI97: 9th IEEE International Conference on Tools with Artificial Intelligence, Newport Beach, CA (USA), November 1997
    CV. Ramamoorthy Best Paper Award
  162. Simulation-Based Verification of Network Protocols Performance
    M. Baldi, F. Corno, M. Rebaudengo, P. Prinetto, M. Sonza Reorda, G. Squillero
    CHARME97: Advanced Research Working Conference on Correct Hardware Design and Verification Methods, Montr? al, Quebec, Canada, October 1997, pp. 236-251
  163. A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, G. Squillero
    ATS97: The Sixth IEEE Asian Test Symposium, Akita (JP), November 1997, pp. 56-61
    Also included in the 10th Anniversary Compedium of Papers from Asian Test Symposium
  164. Guaranteeing Testability in Re-encoding for Low Power
    S. Chiusano, F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    ATS97: The Sixth IEEE Asian Test Symposium, Akita (JP), November 1997
  165. Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, M. Violante
    ATS97: The Sixth IEEE Asian Test Symposium, Akita (JP), November 1997
  166. Il Politecnico di Torino su Internet: un'esperienza di gestione di un server web universitario
    F. Corno, L. Farinetti, M. Innocenti, F. Maino, M. Sonza Reorda
    AICA97 (Associazione Italiana Calcolo Automatico), Milano, 1997
  167. Testability analysis and ATPG on behavioral RT-level VHDL
    F. Corno, P. Prinetto, M. Sonza Reorda
    ITC97, IEEE International Test Conference, Washington D. C. (USA), November 1997
  168. Optimizing Area Loss in Flat Glass Cutting
    S. Bisotto, F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    GALESIA97, IEE/IEEE International Conference on Genetic ALgorithms in Engineering Systems: Innovations and Applications, Glasgow (UK), September 1997
  169. A New Approach for Initialization Sequences Computation for Synchronous Sequential Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, G. Squillero
    ICCD97, October 1997, Austin, Texas (USA), pp. 381-386
  170. Boolean Function Manipulation on a Parallel System using BDDs
    R. Ansaloni, F. Bianchi, F. Corno, M. Rebaudengo, M. Sonza Reorda
    HPCN Europe 1997: International Conference and exhibition on High-Performance Computing and Networking, Vienna, Austria, April 1997, in Lecture Notes in Computer Science 1225, Springer, pp. 916-928
  171. Cellular Automata for Sequential Test Pattern Generation
    S. Chiusano, F. Corno, P. Prinetto, M. Sonza Reorda
    VTS97: 15th IEEE VLSI Test Symposium, Monterey, CA (USA), April 1997, pp. 60-65
  172. Hybrid Symbolic-Explicit Techniques for the Graph Coloring Problem
    S. Chiusano, F. Corno, P. Prinetto, M. Sonza Reorda
    ED&TC97: IEEE European Design and Test Conference, Paris (F), March 1997, pp. 422-426
  173. Testable Synthesis through RT-level DfT rules
    S. Barbagallo, F. Corno, D. Medina, P. Prinetto, M. Sonza Reorda, M. Violante
    ED&TC97: IEEE European Design and Test Conference User's Forum, Paris (F), March 1997, pp. 57-61
  174. New Static Compaction Techniques of Test Sequences for Sequential Circuits
    F. Corno, M. Rebaudengo, P. Prinetto, M. Sonza Reorda
    ED&TC97: IEEE European Design and Test Conference, Paris (F), March 1997, pp. 37-43
  175. SAARA: a Simulated Annealing Algorithm for Test Pattern Generation for Digital Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    SAC97: 12th Annual ACM Symposium on Applied Computing, San Jose, CA (USA), February 1997, pp. 228-232
  176. Faulty Behavior Observation on a Microprocessor System through a VHDL Simulation-Based Fault Injection Experiment
    A. Amendola, A. Benso, F. Corno, L. Impagliazzo, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    IEEE EURO-VHDL96, Geneva (Switzerland), September 1996
  177. Fault Tolerant and BIST design of a FIFO cell
    F. Corno, P. Prinetto, M. Sonza Reorda
    IEEE EURO-VHDL96, Geneva (Switzerland), September 1996
  178. Scan Insertion Criteria for Low Design Impact
    S. Barbagallo, M. Lobetti, D. Medina, F. Corno, P. Prinetto, M. Sonza Reorda
    IEEE VLSI Test Symposium, Princeton (USA), April 1996
  179. Exploiting Competing Subpopulations for Automatic Generation of Test Sequences for Digital Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    Fourth International Conference on Parallel Problem Solving from Nature, Berlin (Germany), September 1996
  180. Partial Scan Flip Flop Selection for Simulation-based Sequential ATPGs
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    IEEE International Test Conference, Washington (USA), October 1996
  181. Comparing topological, symbolic and GA-based ATPGs: an experimental approach
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    IEEE International Test Confernce, Washington (USA), October 1996
  182. A Genetic Algorithm for Automatic Generation of Test Logic for Digital Circuits
    F. Corno, P. Prinetto, M. Sonza Reorda
    IEEE International Conference On Tools with Artificial Intelligence, Toulouse (F), November 1996
  183. A Parallel Genetic Algorithm for Automatic Generation of Test Sequences for Digital Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    International Conference on High-Performance Computing and Networking, Brussels (Belgium), April 1996
  184. Advanced Techniques for GA-based sequential ATPGs
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, R. Mosca
    IEEE Design & Test Conference, Paris (F), March 1996
  185. Il ruolo delle tecniche di fault injection nell'analisi dell'affidabilit? dei sistemi
    A. Benso, F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    AEI (Automazione Energia Informazione), Vol. 83, N. 10, Ottobre 1996, pp. 63/807-69/813
  186. On-line Testing of an Off-the-Shelf Microprocessor Board for Safety-critical Applications
    F. Corno, M. Damiani, L. Impagliazzo, P. Prinetto, M. Rebaudengo, G. Sartore, M. Sonza Reorda
    EDCC Conference, Taormina (Italy), October 1996
  187. Testable Synthesis of Control Units via Circular Self-Test Path: Problems and Solutions
    F. Corno, P. Prinetto, M. Sonza Reorda
    IEEE Design & Test of Computers, Winter 1996
  188. GATTO: a Genetic Algorithm for Automatic Test Pattern Generation for Large Synchronous Sequential Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    IEEE Transactions on Computer-Aided Design, August 1996, Vol. 15, No. 8, pp. 943-951
  189. Uso di Tecniche Evolutive per la Risoluzione di problemi di CAD Elettronico
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    Processori Dedicati, a cura di Lanfranco Lopriore, Fabrizio Luccio e Maria Marinaro, Collana CNR/Progetto Finalizzato "Sistemi Informatici e Calcolo Parallelo" diretta da Bruno Fadini, Franco Angeli Editore
  190. Improving Topological ATPG with Symbolic Techniques
    F. Corno, U. Glaeser, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, H. T. Vierhaus
    IEEE VLSI Test Symposium, Princeton (USA), April 1995
  191. A Portable ATPG tool for Parallel and Distributed Systems
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, E. Veiluva
    IEEE VLSI Test Symposium, Princeton (USA), April 1995
  192. Testing a Switching Memory in a Telecommunication System
    S. Barbagallo, F. Corno, P. Prinetto, M. Sonza Reorda
    IEEE International Test Conference, Washington (USA), October 1995
  193. Using Symbolic Techniques to find the Maximum Clique in Very Large Sparse Graphs
    F. Corno, P. Prinetto, M. Sonza Reorda
    ED&TC95: IEEE European Design and Test Conference, Paris, March 1995
  194. Proving Testing Preorders for Process Algebra Descriptions
    F. Corno, M. Cusinato, M. Ferrero, P. Prinetto
    ED&TC95: IEEE European Design and Test Conference, Paris, March 1995
  195. GARDA: a Diagnostic ATPG for Large Synchronous Sequential Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    ED&TC95: IEEE European Design and Test Conference, Paris, March 1995
  196. A PVM tool for Automatic Test Generation on Parallel and Distributed Systems
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, E. Veiluva
    International Conference on High-Performance Computing and Networking, Milan (Italy), May 1995, Lecture Notes in Computer Science, Ed. Springer
  197. A new Functional Fault Model for System-Level Descriptions
    P. Camurati, F. Corno, M. Meo, P. Prinetto
    VTS94: 12th IEEE VLSI Test Symposium, Cherry Hill, NJ (USA), April 1994
  198. Making the Circular Self-Test Path Technique Effective for Real Circuits
    F. Corno, P. Prinetto, M. Sonza Reorda
    ITC94: IEEE International Test Conference, Washington D. C. (USA), October 1994
  199. Exploiting a Workstation Network for Automatic Generation of Test Patterns for Digital Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, A. R. Meo, E. Veiluva
    AICA94: Congresso Annuale Associazione Italiana per l'Informatica ed il Calcolo Automatico, Palermo (I), September 1994
  200. A Process Algebra Interpretation of a Verification Oriented Overlanguage of VHDL
    C. Bayol, B. Soulas, F. Corno, P. Prinetto, D. Borrione
    EURO-DAC94: IEEE European Design Automation Conference, Grenoble (F), September 1994
  201. An Experimental Analysis of the Effectiveness of the Circular Self-Test Path Technique
    F. Corno, P. Prinetto, M. Sonza Reorda
    EURO-DAC94: IEEE European Design Automation Conference, Grenoble (F), September 1994
  202. System-Level Modeling and Verification: a Comprehensive Design Methodology
    P. Camurati, F. Corno, P. Prinetto, C. Bayol, B. Soulas
    ED&TC94: 1st IEEE European Design and Test Conference 1994, Paris, February 1994
  203. An Approach to Sequential Circuit Diagnosis based on Formal Verification Techniques
    G. Cabodi, P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda
    JETTA: The Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers, N. 4, January 1993, pp. 11-17
  204. Finding the Maximum Clique in a Graph Using BDDs
    F. Corno, P. Prinetto, M. Sonza Reorda
    ICVC93: IEEE 3rd International Conference on VLSI and CAD, Taejon, Korea, November 1993, pp. 269-272
  205. A verifiable design methodology at system-level
    P. Camurati, F. Corno, P. Prinetto, C. Bayol, B. Soulas
    ICVC93: IEEE 3rd International Conference on VLSI and CAD, Taejon, Korea, November 1993, pp. 364-367
  206. VOVHDL: a verification-oriented dialect of VHDL
    P. Camurati, F. Corno, P. Prinetto, C. Bayol, B. Soulas
    VFE93: VHDL-Forum for CAD in Europe, Hamburg (D), September 1993, pp. 37-47
  207. An efficient tool for system-level verification of behaviors and temporal properties
    P. Camurati, F. Corno, P. Prinetto
    EURO-DAC93: IEEE European Design Automation Conference, Hamburg (Germany), September 1993, pp. 124-129
  208. A Methodology for System-Level Design for Verifiability
    P. Camurati, F. Corno, P. Prinetto
    CHARME93: Advanced Research Workshop on Correct Hardware Design Methodologies, Arles (F), May 1991, (Lecture Notes in Computer Science, Springer Verlag, Berlin (Germany), n. 683), pp. 80-91
  209. Exploiting symbolic traversal techniques for efficient Process Algebra Manipulation
    P. Camurati, F. Corno, P. Prinetto
    CHDL93: IFIP Conference on Hardware Description Languages and their Applications, Ottawa (Canada), April 1993, in IFIP Transactions A-32, Elsevier Science Publishers (NL), pp. 31-44
  210. System-Level Fault Modeling and Test Pattern Generation with Process Algebras
    P. Camurati, F. Corno, P. Prinetto
    ETC93: IEEE European Test Conference, Rotterdam (NL), April 1993, pp. 47-56
  211. Tecniche di diagnosi per circuiti sequenziali
    G. Cabodi, P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda
    Congresso Annuale AICA'92, Torino (I), October 1992, Volume II, pp. 737-748
  212. Attraversamento simbolico di Macchine a Stati Finiti per verifica, sintesi e collaudo
    G. Cabodi, P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda
    Congresso Annuale AICA'92, Torino (I), October 1992, Volume I, pp. 133-145
  213. Sequential circuit diagnosis based on formal verification techniques
    G. Cabodi, P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda
    ITC92: IEEE International Test Conference, Baltimore, MD (USA), September 1992, pp. 187-196
  214. Cross-fertilizing FSM verification techniques and sequential diagnosis
    G. Cabodi, P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda
    EURO-DAC92: IEEE European Design Automation Conference, Hamburg (Germany), September 1992, pp. 306-311
  215. A new model for improving symbolic Product Machine traversal
    G. Cabodi, P. Camurati, F. Corno, S. Gai, P. Prinetto, M. Sonza Reorda
    DAC92: 29th ACM/IEEE Design Automation Conference, Anaheim, CA (USA), June 1992, pp. 614-619
  216. A simulation-based approach to test pattern generation for synchronous circuits
    P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda
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