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Papers by G. Squillero

  1. Artificial evolution in computer aided design: from the optimization of parameters to the creation of assembly programs
    G. Squillero
    Computing, Special Issue on Bio-inspired Computing, Volume 93, Numbers 2-4, 103-120
  2. Automatic generation of software-based functional failing test for speed debug and on-silicon timing verification
    E. Sanchez, G. Squillero, A. Tonda
    MTV11: International Workshop on Microprocessor Test and Verification
  3. Post-Silicon Failing-Test Generation through Evolutionary Computation
    E. Sanchez, G. Squillero, A. Tonda
    19th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
  4. Post-Silicon Functional Failing-Test Generation through Evolutionary Computation
    E. Sanchez, G. Squillero, A. Tonda
    ETS2005: IEEE European Test Symposium, 2005
  5. Increasing Pattern Recognition Accuracy for Chemical Sensing by Evolutionary Based Drift Compensation
    S. Di Carlo, M. Falasconi, E. Sanchez, A. Scionti, G. Squillero, A. Tonda
    Pattern Recognition Letters, pp. 1594-1603
  6. Covariance Matrix Adaptation Evolutionary Strategy for Drift Correction of Electronic Nose Data
    S. Di Carlo, M. Falasconi, E. Sanchez, A. Scionti, G. Squillero, A. Tonda
    International Symposium on Olfaction and Electronic Nose (ISOEN 2011)
  7. Evolutionary Optimization: the µGP toolkit
    E. Sanchez, M. Schillaci, G. Squillero
    Hardcover, ISBN 978-0-387-09425-0 / 1st Edition., 2011, XIII, 178 p.
  8. Towards Drift Correction in Chemical Sensors Using an Evolutionary Strategy
    S. Di Carlo, M. Falasconi, E. Sanchez, A. Scionti, G. Squillero, A. Tonda
    GECCO 2010: Proceedings of the 2009 GECCO conference on Genetic and evolutionary computation
  9. Exploiting Evolution for an Adaptive Drift-Robust Classifier in Chemical Sensing
    S. Di Carlo, M. Falasconi, E. Sanchez, A. Scionti, G. Squillero, A. Tonda
    EVONUM 2010: Published in Lecture Notes in Computer Science, Volume 6024/2010, Applications of Evolutionary Computation, pp. 412-421
  10. Evolving Individual Behavior in a Multi-Agent Traffic Simulator
    E. Sanchez, G. Squillero, A. Tonda
    EVOCOMPLEX 2010: Published in Lecture Notes in Computer Science, Volume 6024/2010, Applications of Evolutionary Computation, pp. 11-20
  11. Automatic Detection of Software Defects: an Industrial Experience
    S. Gandini, D. Ravotto, W. Ruzzarin, E. Sanchez, G. Squillero, A. Tonda
    GECCO 2009: Proceedings of the 2009 GECCO conference on Genetic and evolutionary computation, Montreal, Quebec (Canada), pp: 1921-1922
  12. EA-Based Test and Verification of Microprocessors
    G. Squillero
    GECCO 2008: Proceedings of the 2008 GECCO conference companion on Genetic and evolutionary computation, Atlanta, GA (USA)
    Tutorial
  13. A novel methodology for diversity preservation in evolutionary algorithms
    G. Squillero, A. Tonda
    GECCO 2008: Proceedings of the 2008 GECCO conference companion on Genetic and evolutionary computation, Atlanta, GA (USA)
  14. An Evolutionary Methodology for Test Generation for Peripheral Cores Via Dynamic FSM Extraction
    D. Ravotto, E. Sanchez, M. Schillaci, G. Squillero
    4th European Workshop on Bio-Inspired Heuristics for Design Automation (EvoHOT2008), March 26-28, 2008, Napoli, Italy, pp. 214-223
  15. An Effective technique for the Automatic Generation of Diagnosis-oriented Programs for Processor Cores
    P. Bernardi, E. Sanchez, M. Schillaci, G. Squillero, M. Sonza Reorda
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008, Vo. 27, No. 3, pp. 570-574, March 2008
  16. Methodologies for Test Program Generation Exploiting Simulation Feedback
    G. Squillero
    Technion - Israel Institute of Technology, Haifa, Israel
    Tutorial
  17. Evolutionary Techniques Applied to Hardware Optimization Problems: Test and Verification of Advanced Processors
    E. Sanchez, G. Squillero
    [chapter in] Studies on Computational Intelligence, Vol 66, Advances in Evolutionary Computing for System Design, edited by Lakhmi C. Jain, Vasile Palade and Dipti Srinivasan, Springer publisher, 2007, ISBN 978-3-540-72376-9, pp. 83-106.
  18. Automotive Microcontroller End-of-Line Test via Software-Based Methodologies
    W. Di Palma, D. Ravotto, E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero
    MTV2007: 8th International Workshop on Microprocessor Test and Verification, Austin, December 5-6, 2007, pp. 77 - 82
  19. On Automatic Test Block Generation for Peripheral Testing in SoCs via Dynamic FSMs Extraction.
    D. Ravotto, E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero
    MTV2007: 8th International Workshop on Microprocessor Test and Verification, Austin, December 5-6, 2007, pp. 71 - 76
  20. Co-evolution of Test Programs and Stimuli Vectors for Testing of Embedded Peripheral Cores
    L. Bolzani, E. Sanchez, M. Schillaci, G. Squillero
    CEC2007: IEEE Congress on Evolutionary Computation, Singapore, September 25-28, 2007, pp. 3474-3481
  21. A local analysis of an incremental evolutionary tool for processor diagnosis
    D. Ravotto, E. Sanchez, M. Schillaci, G. Squillero
    CEC2007: IEEE Congress on Evolutionary Computation, Singapore, September 25-28, 2007, pp. 3467-3473
  22. Coupling EA and High-level Metrics for the Automatic Generation of Test Blocks for Peripheral Cores
    L.Bolzani, E. Sanchez, M. Schillaci, G. Squillero
    GECCO2007: Genetic and Evolutionary Computation Conference, London, UK, July 7-11, 2007, pp. 1912-1919
  23. An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores
    L. Bolzani, E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero
    IOLTS2007: IEEE International On-Line Testing Symposium, 2007, pp. 265-270
  24. An Extensible Evolutionary-based General-purpose Optimizer
    E. Sanchez, M. Schillaci, G. Squillero
    IOST3, IEEE International Workshop on Open Source Test Technology Tools, Claremont Resort, Berkeley (CA), USA, May 9-10, 2007
  25. An Enhanced Technique for the Automatic Generation of Effective Diagnosis-oriented Test Programs for Processors
    E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero
    DATE2007: Design, Automation and Test in Europe, April 16-20 2007, pp. 1-6
  26. An Evolutionary Methodology to Enhance Processor Software-Based Diagnosis
    P. Bernardi, E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero
    CEC 2006, IEEE Congress on Evolutionary Computation, Vancouver (BC), Canada, July 16-21, 2006, pp. 859, 864
  27. Enhanced Test Program Compaction Using Genetic Programming
    E. Sanchez, M. Schillaci, G. Squillero
    CEC 2006, IEEE Congress on Evolutionary Computation, Vancouver (BC), Canada, July 16-21, 2006, pp. 865-870
  28. µGP an evolutionary test program generator
    G. Squillero, M. Schillaci, E. Sanchez
    IOST3, IEEE International Workshop on Open Source Test Technology Tools, Berkeley (CA), USA, April 30 2006
  29. Evolving Warriors for the Nano Core
    E. Sanchez, M. Schillaci, G. Squillero
    CIG 2006, IEEE Symposium on Computational Intelligence and Games, May 22-24 2006, Reno/Lake Tahoe (AZ), USA, pp. 272-278
  30. Efficient Techniques for Automatic Verification-Oriented Test Set Optimization
    E. Sanchez, G. Squillero, M. Sonza Reorda
    International Journal of Parallel Programming, Vol. 34, Num. 1, March 2006, pp. 93 - 109, Ed. Springer Netherlands
  31. An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs
    P. Bernardi, E. Sanchez, M. Schillaci, G. Squillero, M. Sonza Reorda
    IEEE DATE2006: Design, Automation and Test in Europe, 2006, pp. 412-417
    BEST PAPER AWARD at IEEE DATE 2006
  32. Anatomy of an extensible evolutionary tool
    E. Sanchez, M. Schillaci, G. Squillero
    GSICE2: II Giornata di Studio Italiana sul Calcolo Evoluzionistico, 2006
  33. Test Program Generation From High-level Microprocessor Descriptions
    E. Sanchez, M. Sonza Reorda, G. Squillero
    [chapter in] Test and validation of hardware/software systems starting from system-level descriptions, Edited by M. Sonza Reorda, M. Violante, Z. Peng, Springer publisher, 2005, 179 p, ISBN: 1-85233-899-7, pp. 83-106
  34. Diagnosing faulty functional units in processors by using automatically generated test sets
    P. Bernardi, E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero
    MTV'05: 6th International Workshop on Microprocessor Test and Verification, Austin (TX), USA, Nov. 3-4, 2005, pp. 37-41
  35. On the Transformation of Manufacturing Test Sets into On-Line Test Sets for Microprocessors
    E. Sanchez, M. Sonza Reorda, G. Squillero
    DFT'05: The 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 494-502
  36. A modular Architecture for a Populationless Evolutionary Algorithm for MIP
    E. Sanchez, M. Schillaci, G. Squillero
    GSICE: Giornata di Studio Italiana sul Calcolo Evolutivo, 2005
  37. Automatic Generation of Test Sets for SBST of Microprocessor IP Cores
    E. Sanchez, M. Sonza Reorda, G. Squillero, M. Violante
    SBCCI 2005, 18th IEEE Symposium on Integrated Circuits and Systems Design, pp. 74-79
  38. New Evolutionary Techniques for Test-Program Generation for Complex Microprocessor Cores
    E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero, L. Sterpone, M. Violante
    GECCO05: Genetic and Evolutionary Computation Conference, Washington, DC, USA, June 25-29 2005, pp. 2193-2194
  39. Evolving Assembly Programs: How Games Help Microprocessor Validation
    F. Corno, E. Sanchez, G. Squillero
    IEEE Transactions on Evolutionary Computation, Special Issue on Evolutionary Computation and Games, Dec. 2005, vol. 9, pp. 695-706
    SILVER MEDAL at the Human-Competitive Awards 2005 (HUMIES)
  40. MicroGP - An Evolutionary Assembly Program Generator
    G. Squillero
    Genetic Programming and Evolvable Machines, vol. 6, no. 3, 2005, pp. 247-263
  41. Automatic Completion and Refinement of Verification Sets for Microprocessor Cores
    E. Sanchez, G. Squillero, M. Sonza Reorda
    Lecture Notes in Computer Science, Vol 3449, "Applications on Evolutionary Computing: EvoWorkkshops 2005", Lausanne (CH), March 2005, pp. 205-214
  42. Automatic Test Program Generation for Verifyng Microprocessors
    F. Corno, E. Sanchez, M. Sonza Reorda, G. Squillero
    IEEE Potentials, Vol 24, Issue 1, Feb-Mar 2005, pp. 34-37
  43. Evolutionary Simulation-Based Validation
    F. Corno, M. Sonza Reorda, G. Squillero
    International Journal on Artificial Intelligence Tools (IJAIT), Vol. 14, 1-2, Dec. 2004, pp. 897 916
  44. Automatic Verification of RT-Level Microprocessor Cores Using Behavioral Specifications: a Case Study
    L. Anghel, E. Sanchez, M. Sonza Reorda, G. Squillero, R. Velazco
    XIX Conference on Design of Circuits and Integrated Systems, Bordeaux, France, November 24-26, 2004
  45. Coupling Different Methodologies to Validate Obsolete Microprocessors
    L. Anghel, E. Sanchez, M. Sonza Reorda, G. Squillero, R. Velazco
    DFT'04: The 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
  46. Automatic Test Programs Generation Driven by Internal Performance Counters
    W. Lindsay , E. Sanchez, M. Sonza Reorda, G. Squillero
    MTV'04: 5th International Workshop on Microprocessor Test and Verification, pp. 8-13
  47. Code Generation for Functional Validation of Pipelined Microprocessors
    F. Corno, E. Sanchez, M. Sonza Reorda, G. Squillero
    Journal of Electronic Testing: Theory and Applications, Vol 20(3), June 2004, pp. 269-278
  48. A Local Analysis of the Genotype-Fitness Mapping in Hardware Optimization Problems
    E. Sanchez, G. Squillero, M. Violante
    CEC2004, Congress on Evolutionary Computation, Portland (Oregon), June 20-23, 2004, pp. 871-878
  49. On The Evolution of Corewar Warriors
    F. Corno, E. Sanchez, G. Squillero
    CEC2004, Congress on Evolutionary Computation, Portland (Oregon), June 20-23, 2004, pp. 2365-2371
  50. Dynamic Optimization of Semantic Annotation Relevance
    D. Bonino, F. Corno, G. Squillero
    CEC2004, Congress on Evolutionary Computation, Portland (Oregon), June 20-23, 2004
  51. Automatic Test Program Generation - a Case Study
    F. Corno, E. Sanchez, M. Sonza Reorda, G. Squillero
    IEEE Design & Test, Special issue on Functional Verification and Testbench Generation, Volume: 21, Issue 2, March-April 2004, pp. 102-109
  52. Exploiting HW Acceleration for Classifying Complex Test Program Generation Problems
    E. Sanchez, G. Squillero, M. Violante
    of Evolutionary Computing: EvoWorkshops 2004 proceedings, Coimbra (Portugal), April 5-7 2004, pp. 230-239
  53. Exploiting Co-Evolution and a Modified Island Model to Climb the Core War Hill
    F. Corno, E. Sanchez, G. Squillero
    CEC03: 2003 IEEE Congress on Evolutionary Computation, Canberra, Australia, 8th - 12th December 2003, pp. 2222-2229
  54. Dynamic Prediction of Web Requests
    D. Bonino, F. Corno, G. Squillero
    CEC03: 2003 IEEE Congress on Evolutionary Computation, Canberra, Australia, 8th - 12th December 2003, pp. 2034-2041
  55. Code Generation for Functional Validation of Pipelined Microprocessors
    F. Corno, G. Squillero, M. Sonza Reorda
    ETW03: 8th IEEE European Test Workshop (Formal Proceedings), The Netherlands, May 25 28, 2003, pp. 113-118
  56. A Real-Time Evolutionary Algorithm for Web Prediction
    D. Bonino, F. Corno, G. Squillero
    WI-2003, The 2003 IEEE/WIC International Conference on Web Intelligence, October 2003, Halifax, Canada
  57. An Evolutionary Approach to Web Request Prediction
    D. Bonino, F. Corno, G. Squillero
    poster at WWW2003 - The Twelfth International World Wide Web Conference, 20-24 May 2003, Budapest, HUNGARY
  58. New Acceleration Techniques for Simulation-Based Fault-Injection
    F. Corno, L. Entrena, C. Lopez, M. Sonza Reorda, G. Squillero
    [chapter in] Fault Injection Techniques and Tools for Embedded Systems Reliability Evaluation, edited by, A. Benso, P. Prinetto, ISBN 1 4020 7589 8, October 2003, pp. 217-230
  59. An Enhanced Framework for Microprocessor Test-Program Generation
    F. Corno, G. Squillero
    EUROGP2003: 6th European Conference on Genetic Programming, Essex (UK), April 14-16, 2003, pp. 307-315
  60. Exploiting Auto-Adaptive µGP for Highly Effective Test Programs Generation
    F. Corno, G. Squillero
    ICES2003: The 5th International Conference on Evolvable Systems: From Biology to Hardware, Trondheim (Norway), March 17-20, 2003, pp. 262-273
  61. Automatic Test Program Generation for Pipelined Processors
    F. Corno, M. Sonza Reorda, G. Squillero
    SAC2003: The Eighteenth Annual ACM Symposium on Applied Computing, Melbourne, Florida (USA), March 9-12, 2003, pp. 736-740
  62. Fully Automatic Test Program Generation for Microprocessor Cores
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    DATE2003: Design, Automation and Test in Europe, Munich, Germany, March 3-7, 2003, pp. 1006-1011
  63. A New Evolutionary Paradigm for Cultivating Cellular Automata for Built-In Self Test of Sequential Circuits
    F. Corno, M. Sonza Reorda, G. Squillero
    [chapter in] Evolutionary Algorithms for Embedded System Design , edited by R. Drechsler and N. Drechsler, Kluwer Academic Publishers, October 2002, ISBN 1-4020-7276-7, pp.? 143-173
  64. Reducing Test Application Time through Interleaved Scan
    F. Corno, M. Sonza Reorda, G. Squillero
    SBCCI2002: 15th IEEE Symposium on Integrated Circuits and Systems Design, Porto Alegre (Brasil), Septempber 2002, pp. 89-94
    Outstanding Paper Award
  65. Initializability Analysis of Synchronous Sequential Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, G. Squillero
    ACM Transactions on Design Automation of Electronic Systems, April 2002, pp. 249-264
  66. Evolutionary Test Program Induction for Microprocessor Design Verification
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    ATS2002: IEEE Asian Test Symposium, Guam (USA), November 2002, pp. 368-373
  67. Analysis of the Equivalences and Dominances of Transient Faults at the Register-Transfer Level
    L. Berrojo, F. Corno, L. Entrena, I. Gonz lez, C. Lopez, M. Sonza Reorda, G. Squillero
    IOLTW2002: IEEE International On-line Testing Workshop, 2002, pp. 193
  68. Efficient Machine-Code Test-Program Induction
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    CEC2002: Congress on Evolutionary Computation, Honolulu, Hawaii (USA), pp. 1486-1491
  69. An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation
    L. Berrojo, F. Corno, L. Entrena, I. Gonz lez, C. Lopez, M. Sonza Reorda, G. Squillero
    VTS2002: 20th IEEE VLSI Test Symposium, Monterey, CA (USA), 28 April - 2 May, 2002, pp. 229-236
  70. Evolutionary Techniques for Minimizing Test Signals Application Time
    F. Corno, M. Sonza Reorda, G. Squillero
    EvoIASP2002: 4rd European Workshop on Evolutionary Computation applications to Image Analysis and Signal Processing, Kinsale (Ireland), April 2002, pp. 183-189
  71. Automatic Test Program Generation from RT-level Microprocessor Descriptions
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    ISQED2002: 3rd International Symposium on Quality Electronic Design, March 18-21, 2002, San Jose, California (USA), pp. 120-125
  72. An Evolutionary Algorithm for Reducing Integrated-Circuit Test Application Time
    F. Corno, M. Sonza Reorda, G. Squillero
    SAC2002: 17th ACM Symposium on Applied Computing, March 2002, Madrid (Spain), pp. 608-611
  73. New Techniques for Speeding-up Fault-injection Campaigns
    L. Berrojo, I. Gonz lez, F. Corno, M. Sonza Reorda, G. Squillero, L. Entrena, C. Lopez
    DATE2002: Design, Automation and Test in Europe, Conference and Exhibition, Paris, France, March 4-8, 2002, pp. 847-852
  74. A Transparent Search Agent for Closed Collections
    F. Bota, F. Corno, L. Farinetti, G. Squillero
    SSGRR-2002w: International Conference on Advances in Infrastructure for e-Business, e-Education, e-Science, and e-Medicine on the Internet, L'Aquila (I), January 2002
  75. Devising an RT-Level ATPG for uProcessor Cores
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    WRTLT2001: 2nd Worshop on RTL, ATPG & DFT, Nara, Japan, November 22-23, 2001
  76. Effective Techniques for High-Level ATPG
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    ATS2001: IEEE Asian Test Symposium, 2001, pp. 225-230
    Best Paper Award
  77. An Interpretation Framework for Evaluating High-Level Fault Models and ATPG Capabilities
    F. Corno, M. Sonza Reorda, G. Squillero
    DCIS2001: Design of Circuits and Integrated Systems, 2001, pp. 273-278
  78. ARPIA: a High-Level Evolutionary Test Signal Generator
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    EvoIASP2001: 3rd European Workshop on Evolutionary Computation applications to Image Analysis and Signal Processing, Como (Italy), April 20, 2001, pp. 298-306
  79. On the Test of Microprocessor IP Cores
    F. Corno, M. Sonza Reorda, G. Squillero, M. Violante
    DATE2001: IEEE Design, Automation & Test in Europe Conference, Munich (Germany), 13-16 March 2001, pp. 209-213
  80. Evolving Effective CA/CSTP BIST Architectures for Sequential Circuits
    F. Corno, M. Sonza Reorda, G. Squillero
    SAC2001: 16th ACM Symposium on Applied Computing, March 2001, Las Vegas (USA), pp. 345-350
  81. GA-Based Verification of Network Protocols Performance
    M. Baldi, F. Corno, M. Rebaudengo, M. Sonza Reorda, G. Squillero
    [chapter in] Telecommunications Optimizations: Heuristic and Adaptive Techniques, edited by D. Corne and M. Oates, Wiley and Sons, August 2000, ISBN 0-471-98855-3, pp. 185-198
  82. A Genetic Algorithm-based System for Generating Test Programs for Microprocessor IP Cores
    F. Corno, M. Sonza Reorda, G. Squillero, M. Violante
    ICTAI2000: The Twelfth IEEE International Conference on Tools with Artificial Intelligence, Vancouver, British Columbia, Canada, November 13-15, 2000, pp. 195-198
  83. An RT-level Fault Model with High Gate Level Correlation
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    HLDVT2000: IEEE International High Level Design Validation Workshop, The Claremont Resort & Spa, Berkeley, California, November 8-10 2000
  84. RT-level Fault Simulation Techniques based on Simulation Command Scripts
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    DCIS2000: XV Conference on Design of Circuits and Integrated Systems, Le Corum, Montpellier, November 21-24, 2000, pp. 825-830
  85. RT-Level ITC 99 Benchmarks and First ATPG Results
    F. Corno, M. Sonza Reorda, G. Squillero
    IEEE Design & Test of Computers, July-August 2000, pp. 44-53
  86. An Intelligent User Interface oriented to non-expert users
    F. Corno, L. Farinetti, G. Squillero
    WebNet2000: World Conference on the WWW and Internet, San Antonio, Texas (USA), October 2000, pp. 675-676
  87. Archivi on-line fruibili da utenti inesperti: un'esperienza nel campo della disabilità
    F. Corno, G. Squillero
    Didamatica2000: Convegno AICA sull'Informatica per la Didattica, Cesena (I), May 2000, pp. 181-187
  88. Exploiting the Selfish Gene Algorithm for Evolving Cellular Automata
    F. Corno, M. Sonza Reorda, G. Squillero
    IJCNN2000: IEEE-INNS-ENNS International Joint Conference Neural Networks, Como (I), July 2000, pp. 577-581
  89. Exploiting the Selfish Gene Algorithm for Evolving Hardware Cellular Automata
    F. Corno, M. Sonza Reorda, G. Squillero
    CEC2000: Congress on Evolutionary Computation, San Diego (USA), July 2000, pp. 1401-1406
  90. An Improved Cellular Automata-Based BIST Architecture for Sequential Circuits
    F. Corno, M. Sonza Reorda, G. Squillero
    ISCAS2000: IEEE International Symposium on Circuits and Systems, Geneve (CH), May 2000, pp. 76-79
  91. CA-CSTP: A new BIST Architecture for Sequential Circuits
    F. Corno, M. Sonza Reorda, G. Squillero, M. Violante
    ETW2000: European Test Workshop, May 2000, pp. 167-172
  92. Low Power BIST via Hybrid Cellular Automata
    F. Corno, M. Rebaudengo, M. Sonza Reorda, G. Squillero, M. Violante
    VTS2000: 18th IEEE VLSI Test Symposium, Montreal, Canada, May 2000, pp. 29-34
  93. High-Level Observability for Effective High-Level ATPG
    F. Corno, M. Sonza Reorda, G. Squillero
    VTS2000: 18th IEEE VLSI Test Symposium, Montreal, Canada, May 2000, pp. 411-416
  94. Evolving Cellular Automata for Self-Testing Hardware
    F. Corno, M. Sonza Reorda, G. Squillero
    ICES2000: Third International Conference on Evolvable Systems: From Biology to Hardware, Edinburgh (UK), April 2000, pp. 31-39
  95. Prediction of Power Requirements for High-Speed Circuits
    F. Corno, M. Rebaudengo, M. Sonza Reorda, G. Squillero, M. Violante
    EvoTel2000: European Workshops on Telecommunications, Edinburgh (UK), May 2000, pp. 247-254
  96. Automatic Validation of Protocol Interfaces Described in VHDL
    F. Corno, M. Sonza Reorda, G. Squillero
    EvoTel2000: European Workshops on Telecommunications, Edinburgh (UK), May 2000, pp. 205-213
  97. Automatic Test Bench Generation for Validation of RT-level Descriptions: an Industrial Experience
    F. Corno, A. Manzone, A. Pincetti, M. Sonza Reorda, G. Squillero
    DATE2000: Design, Automation and Test in Europe, Paris (F), March 2000, pp. 385-389
  98. High Quality Test Pattern Generation for RT-level VHDL Descriptions
    F. Corno, M. Sonza Reorda, G. Squillero
    MTV99: 2nd International Workshop on Microprocessor Test and Verification Common Challenges and Solutions, Atlantic City (USA), September 1999
  99. Simulation-Based Sequential Equivalence Checking of RTL VHDL
    F. Corno, M. Sonza Reorda, G. Squillero
    ICECS99: 6th IEEE International Conference on Electronics, Circuits and Systems, Paphos, Cyprus, September 1999, pp. 351-354
  100. Verifying the Equivalence of Sequential Circuits with Genetic Algorithms
    F. Corno, M. Sonza Reorda, G. Squillero
    CEC99: 1999 Congress on Evolutionary Computation, Washington DC (USA), July 1999, pp. 1293-1297
  101. Optimizing Deceptive Functions with the SG-Clans Algorithm
    F. Corno, M. Sonza Reorda, G. Squillero
    CEC99: 1999 Congress on Evolutionary Computation, Washington DC (USA), July 1999, pp. 2190-2195
  102. Approximate Equivalence Verification for Protocol Interface Implementation via Genetic Algorithms
    F. Corno, M. Sonza Reorda, G. Squillero
    EuroEcTel99: R. Poli, H-M. Voigt, S. Cagnoni, D. Corne, G. Smith, T. Fogarty (eds.), Evolutionary Image Analysis, Signal Processing and Telecommunications First European Workshops, EvoIASP'99 and EuroEcTel'99 Goteborg, Sweden, May 1999 Joint Proceedings, Springer LNCS, 1999, pp. 182-192
    Special Jury Award for Outstanding Work Presented by a Student or Young Researcher
  103. Approximate Equivalence Verification of Sequential Circuits via Genetic Algorithms
    F. Corno, M. Sonza Reorda, G. Squillero
    DATE99: IEEE Design, Automation & Test in Europe, Munich (Germany), March 1999, pp. 754-755
  104. VEGA: A Verification Tool Based on Genetic Algorithms
    F. Corno, M. Sonza Reorda, G. Squillero
    ICCD98, International Conference on Circuit Design, Austin, Texas (USA), October 1998, pp. 321-326
  105. A New Evolutionary Algorithm Inspired by the Selfish Gene Theory
    F. Corno, M. Sonza Reorda, G. Squillero
    ICEC98: IEEE International Conference on Evolutionary Computation, May 1998, pp. 575-580
  106. The Selfish Gene Algorithm: a New Evolutionary Optimization Strategy
    F. Corno, M. Sonza Reorda, G. Squillero
    SAC98: 13th Annual ACM Symposium on Applied Computing, Atlanta, Georgia (USA), February 1998, pp. 349-355
  107. GA-based Performance Analysis of Network Protocols
    M. Baldi, F. Corno, M. Rebaudengo, G. Squillero
    ICTAI97: 9th IEEE International Conference on Tools with Artificial Intelligence, Newport Beach, CA (USA), November 1997, pp. 118-124
  108. Simulation-Based Verification of Network Protocols Performance
    M. Baldi, F. Corno, M. Rebaudengo, P. Prinetto, M. Sonza Reorda, G. Squillero
    CHARME97: Advanced Research Working Conference on Correct Hardware Design and Verification Methods, Montr? al, Quebec, Canada, October 1997, pp. 236-251
  109. A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, G. Squillero
    ATS97: The Sixth IEEE Asian Test Symposium, Akita (JP), November 1997, pp. 56-61
    Also included in the 10th Anniversary Compedium of Papers from Asian Test Symposium
  110. A New Approach for Initialization Sequences Computation for Synchronous Sequential Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, G. Squillero
    ICCD97, October 1997, Austin, Texas (USA), pp. 381-386