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Papers by L. Sterpone

  1. Analysis of SEU Effects in Partially Reconfigurable SoPCs
    L. Sterpone, F. Margaglia, M. Koester, J. Hagemeyer, M. Porrman
    [accepted for publication on] IEEE NASA/ESA Conference on Adaptive Hardware Systems, June 6-9, 2011
  2. Fault Injection Analysis of Transient Faults in Clustered VLIW Processors
    L. Sterpone, D. Sabena, S. Campagna, M. Sonza Reorda
    14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, April 13-15, Cottbus, Germany, 2011
  3. An Analytical Model of the Propagation Induced Pulse Broadening (PIPB) Effects on Single Event Transient in Flash-based FPGAs
    L. Sterpone, N. Battezzati, F. Lima Kastensmidt,
    [accepted for publication on] IEEE Transactions on Nuclear Science
  4. A New Reconfigurable Clock-gating Technique for Low Power SRAM-based FPGAs
    L. Sterpone, D. Matos, L. Carro, S. Wong, F. Anjam
    DATE2011: IEEE Design, Automation and Test in Europe, Grenoble, France, pp. 1 - 6, 2011
  5. Analysis and clustering of microRNA array: a new efficient and reliable computational method
    L. Sterpone, F. Collino, G. Camussi, C. Loconsole
    chapter in "Software Tools and Algorithms for Biological Systems", Springer (The Netherlands), Vol. 696, Part 8, pp. 679 - 688, 2011
  6. An integrated flow for the design of hardened circuits on SRAM-based FPGAs
    C. Bolchini, A. Miele, C. Sandionigi, N. Battezzati, L. Sterpone, M. Violante
    15th IEEE European Test Symposium (ETS), 2010, pp. 214 - 219
  7. Advanced technologies for transient faults detection and compensation
    M. Sonza Reorda, L. Sterpone, M. Violante
    book chapter on IGI [accepted for publication on]
  8. Layout-aware Multi-Cell Upsets Effects Analysis on TMR circuits implemented on SRAM-based FPGAs
    L. Sterpone, M. Violante, A. Panariti, A. Bocquillon, F. Miller, N. Buard, A. Manuzzato, S. Gerardin, A. Paccagnella
    IEEE Transactions on Nuclear Science [accepted for publication on]
  9. Reconfigurable Field Programmable Gate Arrays for Mission-Critical Applications
    N. Battezzati, L. Sterpone, M. Violante
    Springer, 1st Edition, 240 pages, ISBN: 978-1-4419-7594-2
  10. Microvesicles Derived from Adult Human Bone Marrow Tissue an Specific Mesenchymal Stem Cell Shuttle Selected Pattern of miRNAs
    F. Collino, M. C. Deregibus, S. Bruno, L. Sterpone, G. Aghemo, L. Viltono, C. Tetta, G. Camussi
    PlosONE International Medical Journal, doi:10.1371/journal.pone.0011803
  11. A New Software Tool for Static Analysis of SET Sensitiveness in Flash-based FPGAs
    N. Battezzati, F. Decuzzi, L. Sterpone, M. Violante
    IEEE International Symposium on Very Large Scale of Integration (VLSI) and System-on-Chip (SoC), pp. 79 - 84, 2010
  12. A New Soft-Error Resilient Voltage-Mode Quaternary Latch
    E. Rhod, L. Sterpone, L.Carro
    IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 200 - 208, 2010
    Best Student Award
  13. An Analytical Model of the Propagation Induced Pulse Broadening (PIPB) Effects on Single Event Transient in Flash-based FPGAs
    L. Sterpone, N. Battezzati, F. Lima Kastensmidt
    IEEE RADECS 2010: 11th European Conference on Radiation and Its Effects on Component and Systems, 2010 [accepted for publication]
  14. Coping with the Obsolescence of Safety- or Mission-Critical Embedded Systems using FPGAs
    H. Guzman-Miranda, L. Sterpone, M. Violante, M. A. Aguirre, M. Gutierrez-Rizo M.
    IEEE Transactions on Industrial Electronics, Vol. 58, Issue 3, pp. 814 - 821, 2011
  15. On the Mitigation of SET broadening effects in Integrated Circuits
    L. Sterpone, N. Battezzati
    IEEE Design and Diagnostic of Electronic Circuits and Systems, pp. 36 - 39, 2010
  16. Analysis of SET Propagation in Flash-based FPGAs by means of Electrical Pulse Injection
    L. Sterpone, N. Battezzati, V. Ferlet-Cavrois
    IEEE Transactions on Nuclear Science, Vol. 57, Issue 4, Part 1, pp. 1820 - 1826, 2010
  17. A Novel Scalable and Reconfigurable Emulation Platform for Embedded Systems Verification
    M. Di Marzio, M. Grosso, M. Sonza Reorda, L. Sterpone, G. Audisio, M. Sabatini
    IEEE International Symposium on Circuits and Systems, pp. 865 - 868, 2010
  18. A new Timing Driven Placement Algorithm for Dependable Circuits on SRAM-based FPGAs
    L. Sterpone
    ACM Transactions on Reconfigurable Technology and Systems, Vol. 4, Issue 1, A7, pp. 1 - 21, December 2010
  19. A New Placement Algorithm for the Mitigation of Multiple Cell Upsets in SRAM-based FPGAs
    L. Sterpone, N. Battezzati
    DATE2010: IEEE Design, Automation and Test in Europe, 2010, Dresden, Germany, pp. 1231 - 1236
  20. Methodologies to study frequency-dependent Single Event Effects sensitivity in Flash-based FPGAs
    N. Battezzati, S. Gerardin, A. Manuzzato, D. Merodio, A. Paccagnella, C. Poivey, L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, December, 2009, Vol. 56, pp. 3534 - 3541
  21. A new RC design for mixed-grain based dynamically reconfigurable architectures
    E. Rhod, L. Sterpone, L. Carro
    IEEE International Conference on Electronics Circuits and Systems, December 13 - 16, pp. 984 - 987, 2009
  22. Soft Errors in Flash-based FPGAs: Analysis Methodologies and First Results
    N. Battezzati, F. Decuzzi, L. Sterpone, M. Violante
    19th IEEE International Conference on Field Programmable Logic and Applications, August 31 - September 2, 2009, pp. 723 - 724
  23. Gene expression reliability estimation through cluster-based analysis
    L. Sterpone, A. Benso, S. Di Carlo, G. Politano
    MEMEA 2009: IEEE International Conference on Medical Measurements and Applications, Cetraro, Italy, 29 - 30 May, 2009, pp. 229 - 231
  24. Timing driven placement for fault tolerant circuits implemented on SRAM-based FPGAs
    L. Sterpone
    ACM International Conference on Applied Reconfigurable Computing, Karlsruhe, March 2009, pp. 85 - 96
  25. New techniques for improving the performance of the lockstep architecture for SEEs mitigation in FPGA embedded processors
    F. Abate, C. A. Lisboa, L. Carro, L. Sterpone, M. Violante
    IEEE Transaction on Nuclear Science, Volume 56, Issue 4, Part 2, August 2009, pp. 1992 - 2000
  26. A study of the Single Event Effects Impact on Functional Mapping within Flash-based FPGAs
    F. Abate, F. Lima Kastensmidt, L. Sterpone, M. Violante
    IEEE Design, Automation and Test in Europe, Munich, Germany , 20 - 24 April 2009, pp. 1226 - 1229
  27. A Novel Dual Core Architecture for the Analysis of DNA Microarray Images
    L. Sterpone
    IEEE Transactions on Instrumentation and Measurement, 2009, pp. 2653 - 2662, DOI: 10.1109/TIM.2009.2015695
  28. On the Static Cross Section of SRAM-based FPGAs
    A. Manuzzato, S. Gerardin, A. Paccagnella, L. Sterpone, M. Violante
    IEEE Radiation Effects Data Workshop, July 2008, pp. 94 - 97
  29. Experimental Validation of Lockstep, Checkpoint, and Rollback Recovery to Detect and Correct Soft Errors in System-On-Programmable-Chips
    F. Abate, L. Sterpone, M. Violante
    IEEE Radiation Effects on Components and Systems.
  30. Monte Carlo Analysis of the Effects of Soft Error Accumulation in SRAM-based FPGAs
    N. Battezzati, L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, Volume 55, Issue 6, Part 1, December 2008, pp. 3381 - 3387
  31. Differential Gene Expression Graphs: a data structure for feature selection, clustering and classification in DNA Microarrays
    A. Benso, S. Di Carlo, G. Politano, L. Sterpone
    8th IEEE International Conference on BioInformatics and BioEngineering: BIBE, 2008, pp. 1-6
  32. Electronics System Design Techniques for Safety Critical Applications
    L. Sterpone
    Series: Lecture Notes in Electrical Engineering, Vol. 26, Springer, London (UK), ISBN 978-1-4020-8978-7
    EDAA Outstanding dissertation Award 2007
  33. FPGA PAL Design Tools
    L. Sterpone
    Wiley Encyclopedia of Computer Science and Engineering, 2008, pp. 1316 - 1326, ISBN: 9780470050132
  34. A Graph-Based Representation of Gene Expression Profiles in DNA Microarrays
    A. Benso, S. Di Carlo, G. Politano, L. Sterpone
    5th IEEE Symposium on Computational Intelligence in Bioinformatics and Computational Biology, 2008, pp. 75 - 82
  35. On the evaluation of radiation-induced transient faults in Flash-based FPGAs
    N. Battezzati, S. Gerardin, A. Manuzzato, A. Paccagnella, S. Rezgui, L. Sterpone, M. Violante
    14th IEEE International On-Line Testing Symposium , 22 - 25 June, 2008, pp. 157 - 163
  36. Soft Errors in SRAM-FPGAs: a Comparison of Two Complementary Approaches
    M. Alderighi, F. Casini, S. DAngelo, M. Mancini, S. Pastore, L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 55, Issue 4, Part 1, August 2008, pp. 2267 - 2273
  37. A Novel Design Flow for the Performance Optimization of Fault Tolerant Circuits on SRAM-based FPGAs
    L. Sterpone, N. Battezzati
    IEEE NASA/ESA Conference on Adaptive Hardware and Systems, June 22-25, 2008, Noordwijk, The Netherlands, pp. 157 - 163
  38. A new Algorithm for the Analysis of the MCUs Sensitiveness of TMR Architectures in SRAM-based FPGAs
    L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 55, Issue 4, Part 1, August 2008, pp. 2019 - 2027
  39. A new Placement Algorithm for the Optimization of Fault Tolerant Circuits on Reconfigurable Devices
    N. Battezzati, L. Sterpone, M. Violante
    CF2008: ACM International Conference on Computing Frontiers, Ischia, Italy, 5 - 7 May 2008, pp. 347 - 352
  40. A new low-cost non intrusive platform for injecting soft errors in SRAM-based FPGAs
    N. Battezzati, L. Sterpone, M. Violante
    ISIE2008: IEEE International Symposium on Industrial Electronics, Cambridge, UK, 30 June - 2 July 2008, pp. 2282 - 2287
  41. Effectiveness of TMR-based techniques to mitigate alpha-induced SEU accumulation in commercial SRAM-based FPGAs
    A. Manuzzato, S. Gerardin, A. Paccagnella, L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 55, Issue 4, Part 1, August 2008, pp. 1968 - 1973
  42. A New Mitigation Approach For Soft Errors In Embedded Processors
    F. Abate, L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 55, Issue 4, Part 1, August 2008, pp. 2063 - 2069
  43. Software and Hardware Techniques for SEU Detection in IP Processors
    C. Bolchini, A. Miele, M. Rebaudengo, F. Salice, D. Sciuto, L. Sterpone, M. Violante
    JETTA: The Journal of Electronic Testing: Theory and Applications, Springer Netherlands, 2008, pp. 35 - 44
  44. On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications
    L. Sterpone, M. Aguirre, J. Tombs, H. Guzman
    DATE 2008: IEEE Design, Automation and Test in Europe, 2008, pp. 336 - 341
  45. Experimental Validation of a Tool for Predicting the Effects of Soft Errors in SRAM-based FPGAs
    L. Sterpone, M. Violante, R. Harboe Sorensen, D. Merodio, F. Sturesson, R. Weigand, S. Mattsson
    IEEE Transactions on Nuclear Science, Vol. 54, No. 6, Part 1, December 2007, pp. 2576-2583
  46. Optimization of Self Checking FIR filters by means of Fault Injection Analysis
    S. Pontarelli, L. Sterpone, G.C. Cardarilli, M. Re, M. Sonza Reorda, A. Salsano, M. Violante
    DFT2007, 22th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2007, pp. 96 - 104
  47. Sensitivity evaluation of TMR-hardened circuits to multiple SEUs induced by alpha particles in commercial SRAM-based FPGAs
    A. Manuzzato, P. Rech, S. Gerardin, A. Paccagnella, L. Sterpone, M. Violante
    DFT2007, 22th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2007, pp. 79 - 86
  48. Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders
    S. Pontarelli, L. Sterpone, G.C. Cardarilli, M. Re, M. Sonza Reorda, A. Salsano, M. Violante
    IOLTS2007: IEEE International On-Line Testing Symposium, 2007, pp. 194 - 196
  49. A new hardware/software platform and a new 1/E neutron source for soft error studies: testing FPGAs at the ISIS facility
    M. Violante, L. Sterpone, A. Manuzzato, S. Gerardin, P. Rech, M. Bagatin, A. Paccagnella, C. Andreani, G. Gorini, A. Pietropaolo, G. Cardarilli, S. Pontarelli, C. Frost
    IEEE Transactions on Nuclear Science, 2007, Volume 54, Issue 4, Part 2, August 2007, pages 965 - 970
  50. An experimental analysis of SEU sensitiveness of recursive-oriented hardening techniques
    L. Sterpone, P. Reyes Moreno, J. A. Maestro, O. Ruano, P. Reviriego
    DDECS2007: IEEE Design & Diagnostic of Electronic Circuits & Systems, 2007, pp. 261 - 266
  51. Static and Dynamic Analysis of SEU effects in SRAM-based FPGAs
    L. Sterpone, M. Violante
    ETS2007: IEEE European Test Symposium, Freiburg, Germany, 2007, pp. 159 - 164
  52. A New Partial Reconfiguration-based Fault-Injection System to Evaluate SEU Effects in SRAM-based FPGAs
    L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, 2007, Volume 54, Issue 4, Part 2, August 2007, Pages 965 - 970
  53. An Analysis of SEU Effects in Embedded Operating Systems for Real-Time Applications
    L. Sterpone, M. Violante
    ISIE2007: IEEE International Symposium on Industrial Electronics, Vigo, Spain, June 4-7, 2007, pp. 3345 - 3349
  54. A new hardware/software platform for the soft-error sensitivity evaluation of FPGA devices
    M. Violante, M. Sonza Reorda, L. Sterpone, A. Manuzzato, S. Gerardin, P. Rech, M. Bagatin, A. Paccagnella, C. Andreani, G. Gorini, A. Pietropaolo, G. Cardarilli, A. Salsano, S. Pontarelli, C. Frost
    LATW2007: 8th IEEE Latin American Test Workshop, Cuzco, Peru, March 11-14, 2007
  55. A new FPGA-based edge detection system for the gridding of DNA microarray images
    L. Sterpone, M. Violante
    IMTC2007: IEEE Instrumentation and Measurement Technology Conference, Warsaw, Poland, May 1-3, 2007, pp. 1 - 6
  56. A new hardware architecture for performing the gridding of DNA microarray images
    L. Sterpone, M. Violante
    GLSVLSI2007: ACM 17th Great Lake Symposium on VLSI, Stresa, Italy, March 11-13, 2007, pp. 341 - 346
  57. A new decompression system for the configuration process of SRAM-based FPGAs
    L. Sterpone, M. Violante
    GLSVLSI2007: ACM 17th Great Lake Symposium on VLSI, Stresa, Italy, March 11-13, 2007, pp. 241 - 246
  58. Evaluating different solutions to design fault tolerant systems with SRAM-based FPGAs
    M. Sonza Reorda, L. Sterpone, M. Violante, F. Lima Kastensmidt, L. Carro
    JETTA: The Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers, Vol. 23, No. 1, February, 2007, pp. 47 - 54
  59. Hybrid Fault Detection Technique: A Case Study on Virtex-II Pro s PowerPC 405
    P. Bernardi, L. Sterpone, M. Violante, M. Portela-Garcia
    IEEE Transactions on Nuclear Science, 2006, Vol. 53, No. 6, December 2006, pp. 3550 - 3557
  60. An Experimental Analysis of a New Mixed Grain-Based Dynamically Reconfigurable Architecture
    L. Sterpone
    ICECS2006: 13th IEEE International Conference on Electronics, Circuits and Systems, 2006, Nice, France, pp. 152-155
  61. Combined software and hardware techniques for the design of reliable IP processors
    M. Rebaudengo, L. Sterpone, M. Violante, C. Bolchini, A. Miele, D. Sciuto
    DFT2006, 21th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2006, pp. 265 - 273
  62. Hardening FPGA-based systems against SEUs: A new design methodology
    L. Sterpone, M. Violante
    Academy Publisher Journal of Computers, Vol. 1, No. 1, April 2006, pp. 22 - 30
  63. Dependability evaluation of transient fault effects in Reconfigurable Compute Fabric devices
    L. Sterpone, M. Violante
    IOLTS2006, IEEE 12th International On-Line Testing Symposium , 2006, pp. 189 - 190
  64. An Analysis based on Fault Injection of Hardening Techniques for SRAM-based FPGAs
    L. Sterpone, M. Violante, S. Rezgui
    IEEE Transactions on Nuclear Science, Vol. 53, Issue 4, August 2006, pp. 2054 - 2059
  65. ReCoM: A new Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications
    L. Sterpone, M. Violante
    DDECS2006: IEEE Workshop Design and Diagnostic of Electronic circuits and systems, 2006, pp. 54 - 58
  66. Fault Injection-based Reliability Evaluation of SoPCs
    M. Sonza Reorda, L. Sterpone, M. Violante, M. Portela-Garcia, C. Lopez-Ongil, L. Entrena
    ETS2006: IEEE European Test Symposium, 2006, pp. 75 - 82
  67. A new reliability-oriented place and route algorithm for SRAM-based FPGAs
    L. Sterpone, M. Violante
    IEEE Transactions on Computers, Vol. 55, No. 6, June 2006, pp. 732 - 744
  68. A Fault Injection Environment for SoPC's Embedded Microprocessors
    M. Portela-Garcia, L. Sterpone, C. Lopez-Ongil, M. Sonza Reorda, M. Violante
    LATW2006, 7th IEEE Latin-American Test Workshop, Buenos Aires, Argentina, March 26-29 2006, pp. 68-73
  69. A new approach to compress the configuration information of programmable devices
    L. Sterpone, M. Violante, M. Martina, G. Masera, A. Molino, F. Vacca
    DATE2006: IEEE Design, Automation and Test in Europe, 2006, pp. 1 - 4
  70. A design flow for protecting FPGA-based systems against single event upsets
    L. Sterpone, M. Violante
    DFT2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 436 - 444
  71. A New Analytical Approach to Estimate the Effects of SEUs in TMR Architectures Implemented Through SRAM-based FPGAs
    L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, 2005, Vol. 52, No. 6, December 2005, pp. 2217 - 2223
  72. Analysis of the robustness of the TMR architecture in SRAM-based FPGAs
    L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, 2005, Vol. 52, No. 5, October 2005, pp. 1545 - 1549
  73. An experimental analysis of hardening techniques for SRAM-based FPGAs
    L. Sterpone, M. Violante, S. Rezgui
    RADECS 2005: 8th European Conference on Radiation and Its Effects on Component and Systems, 2005, pp. J5-1 - J5-4
  74. New Evolutionary Techniques for Test-Program Generation for Complex Microprocessor Cores
    E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero, L. Sterpone, M. Violante
    GECCO05: Genetic and Evolutionary Computation Conference, Washington, DC, USA, June 25-29 2005, pp. 2193-2194
  75. RoRA: Reliability-oriented Place and Route for SRAM-based FPGAs
    L. Sterpone, M. Sonza Reorda, M. Violante
    PRIME05: IEEE Ph.D. Research In Micro-Electronics & Electronics, 2005, pp. 147-150
  76. Efficient Estimation of SEU effects in SRAM-based FPGAs
    M. Sonza Reorda, L. Sterpone, M. Violante
    IOLTS 2005: IEEE International On-line Testing Symposium, 2005, pp. 54-59
  77. Multiple errors produced by single upsets in FPGA configuration memory: a possible solution
    M. Sonza Reorda, L. Sterpone, M. Violante
    ETS2005: IEEE European Test Symposium, 2005, pp. 136-141
    BEST PAPER AWARD at IEEE ETS 2005
  78. On the Optimal Design of Triple Modular Redundancy Logic for SRAM-Based FPGAs
    F. Kastensmidt, L. Sterpone, M. Sonza Reorda, L. Carro
    DATE2005: IEEE Design, Automation and Test in Europe, 2005, pp. 1290-1295
  79. Simulation-Based Analysis of SEU Effects in SRAM-Based FPGAs
    M. Violante, L. Sterpone, M. Ceschia, D. Bortolato, P. Bernardi, M. Sonza Reorda, A. Paccagnella
    IEEE Transactions on Nuclear Science, Vol. 51, No. 6, December 2004, pp. 3354-3359
  80. On the evaluation of SEU sensitiveness in SRAM-based FPGAs
    P. Bernardi, M. Sonza Reorda, L. Sterpone, M. Violante
    IOLTS2004: IEEE International On-Line Testing Symposium, 2004, pp. 115-120