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Papers by M. Rebaudengo

  1. Performance Evaluation of Reliable and Unreliable Opportunistic Flooding in Wireless Sensor Network
    L. Zhang, E.R. Sanchez, M. Rebaudengo
    17th IEEE International Conference On Networks (ICON 2011)
  2. Evaluation Framework of Opportunistic Flooding in Sensor Networks
    L. Zhang, E.R. Sanchez, M. Rebaudengo
    2011 Ninth IEEE/IFIP International Conference on Embedded and Ubiquitous Computing
  3. Introducing probability in Colorwave
    F. Gandino, R. Ferrero, B. Montrucchio, M. Rebaudengo
    Technical Report n. 01-2011-UC
  4. Probabilistic DCS: an RFID Reader-to-Reader Anti-collision Protocol
    F. Gandino, R. Ferrero, B. Montrucchio, M. Rebaudengo
    Journal of Network and Computer Applications, Vol. 34, 2011, pp. 821-832, ISSN: 1084-8045, DOI: 10.1016/j.jnca.2010.04.007
  5. Increasing Throughput in RFID Multi-Reader Environments Avoiding Reader-to-Reader Collisions
    F. Gandino, R. Ferrero, B. Montrucchio, M. Rebaudengo
    29th International Conference on Consumer Electronics, Las Vegas, 9-12 Gennaio 2011
  6. Fair Anti-Collision Protocol in Dense RFID Networks
    R. Ferrero, F. Gandino, B. Montrucchio, M. Rebaudengo
    The Third International EURASIP Workshop on RFID Technology, La Manga del Mar Menor, Cartagena, Spain, 6-7 September 2010
  7. Tampering in RFID: A Survey on Risks and Defenses
    F. GANDINO, B. MONTRUCCHIO, M. REBAUDENGO
    Mobile Networks and Applications, pp. 502-516, Vol. 15(4), ISSN: 1383-469X, 2010
  8. Random Key Pre-Distribution with Transitory Master Key for Wireless Sensor Networks
    F. GANDINO, B. MONTRUCCHIO, M. REBAUDENGO
    CoNEXT Student Workshop 2009, Roma, Italy 1 - December 2009
  9. Opportunity and Constraints for Wide Adoption of RFID in Agri-Food
    F. Gandino, E.R. Sanchez, B. Montrucchio, M. Rebaudengo
    INTERNATIONAL JOURNAL OF ADVANCED PERVASIVE AND UBIQUITOUS COMPUTING, vol. 1 (2), 2009, p. 49-67, ISSN: 1937-965X
  10. RFID Technology for Agri-food Traceability Management
    F. Gandino, E.R. Sanchez, B. Montrucchio, M. Rebaudengo
    Chpater in: J.A. SYMONDS, D. PARRY, J AYOADE. Auto-Identification and Ubiquitous Computing Applications: RFID and Smart Technologies for Information Convergence. p. 54-73, 2009, Information Science Reference, ISBN/ISSN: 978-1-60566-298-5
  11. Public-key in RFIDs: Appeal for Asymmetry
    F. Gandino, E.R. Sanchez, B. Montrucchio, M. Rebaudengo
    Chapter in: ZHANG YAN, KITSOS PARIS. Security in RFID and Sensor Networks. p. 195-216, 2009, CRC Press, Taylor & Francis Group, ISBN/ISSN: 9781420068399
  12. Introducing Probability in RFID Reader-to-Reader Anti-collision
    F. Gandino, R. Ferrero, B. Montrucchio, M. Rebaudengo
    IEEE International Symposium on Network Computing and Applications. Cambridge, MA, USA, 9-11 July 2009
  13. Curricula Design Flow with Embedded Accreditation
    D. Del Corso, M. Gola, M. Rebaudengo
    20th EAEEIE (European Association for Education in Electrical and Information Engineering) Annual Conference. Valencia, Spain, 22-24 giugno 2009
  14. On Improving Automation by Integrating RFID in the Traceability Management of the Agri-Food Sector
    F. Gandino, B. Montrucchio, M. Rebaudengo, E.R. Sanchez
    IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS. vol. 56, Issue: 7, ISSN: 0278-0046, pages: 2357-2365
  15. Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug
    P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda
    IET Computers & Digital Techniques, Vol. 4, N. 2, pp. 104-113, March 2010
  16. Improving Preamble Sampling Performance in Wireless Sensor Networks with State Information
    E. R. Sanchez, C. Chaudet, M. Rebaudengo
    The 6th International Conference on Wireless On-demand Network Systems and Services, Snowbird, UT, USA, February 2-4, 2009, pp. 101-108
  17. RFID for agri-food traceability: methods for authentication, integrity and privacy
    C. Demartini, F. Gandino, B. Montrucchio, M. Rebaudengo, E. R. Sanchez
    Workshop on Emerging Technologies for Radio-frequency Identification
  18. An Anti-Counterfeit Mechanism for the Application Layer in Low-Cost RFID Devices.
    P. Bernardi, F. Gandino, F. Lamberti, B. Montrucchio, M. Rebaudengo, E. R. Sanchez
    ECCSC'08: 4th IEEE European Conference on Circuits and Systems for Communications
  19. Software and Hardware Techniques for SEU Detection in IP Processors
    C. Bolchini, A. Miele, M. Rebaudengo, F. Salice, D. Sciuto, L. Sterpone, M. Violante
    JETTA: The Journal of Electronic Testing: Theory and Applications, Springer Netherlands, 2008, pp. 35 - 44
  20. Analysis of an RFID-based Information System for Tracking and Tracing in an Agri-Food chain
    F. Gandino, B. Montrucchio, M. Rebaudengo, E. R. Sanchez
    1st Annual RFID Eurasia Conference, Istanbul, Turkey September 5-6, 2007, 2007
  21. Increasing Effective Radiated Power in Wireless Sensor Networks with Channel Coding Techniques
    E. R. Sanchez, F. Gandino, B. Montrucchio, M. Rebaudengo
    IEEE International Conference on Electromagnetics in Advanced Applications, ICEAA '07
  22. Multi-level Fault Effects Evaluation
    L. Anghel, M. Rebaudengo, M. Sonza Reorda, M. Violante
    chapter in "Radiation Effects on Embedded Systems", Springer (The Netherlands), ISBN 978-1-4020-5645-1, 2007, pp. 69-88
  23. Safety Evaluation of NanoFabrics
    M. Grosso, M. Rebaudengo, M. Sonza Reorda
    DFT2007, 22th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2007, pp. 418-426
  24. Agri-Food Traceability Management using a RFID System with Privacy Protection
    P. Bernardi, C. Demartini, F. Gandino, B. Montrucchio, M. Rebaudengo, E. R. Sanchez
    IEEE 21st International Conference on Advanced Information Networking and Applications (AINA-07) Niagara Falls, Canada, May 21-23, 2007, pp. 68-75
  25. A System-layer Infrastructure for SoC Diagnosis
    P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda
    JETTA: The Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers
  26. Design of an UHF RFID Transponder for Secure Authentication
    P. Bernardi, F. Gandino, B. Montrucchio, M. Rebaudengo, E. R. Sanchez
    GLSVLSI2007: ACM 17th Great Lake Symposium on VLSI, Stresa, Italy, March 11-13, 2007
  27. Combined software and hardware techniques for the design of reliable IP processors
    M. Rebaudengo, L. Sterpone, M. Violante, C. Bolchini, A. Miele, D. Sciuto
    DFT2006, 21th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2006, pp. 265 - 273
  28. Software-Implemented Hardware Fault Tolerance
    O. Goloubeva, M. Rebaudengo, M. Sonza Reorda, M. Violante
    Springer Science+Business Media, LLC, New York (USA), ISBN: 0-387-26060-9, pages 228
  29. Embedded Memories Diagnosis: An Industrial Workflow
    D. Appello, P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda, V. Tancorre
    ITC06: IEEE International Test Conference, 2006, Santa Clara (CA), USA
  30. On the Automation of the Test Flow of Complex SoCs
    D. Appello, P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda, V. Tancorre
    VTS06: 24th IEEE VLSI Test Symposium, 2006, Berkeley (CA), USA, pp. 166-171
  31. A pattern ordering algorithm for reducing the size of fault dictionaries
    P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda
    VTS06: 24th IEEE VLSI Test Symposium, 2006, Berkeley (CA), USA, pp. 386-391
  32. A New Hybrid Fault Detection Technique for Systems-on-a-Chip
    P. Bernardi, L. M. Veiras Bolzani, M. Rebaudengo, M. Sonza Reorda, F. L. Vargas, M. Violante
    IEEE Transactions on Computers, Vol. 55, No. 2, Feb. 2006, pp. 185-198
  33. An I-IP for the Debug of Microprocessor Cores
    D. Appello, M. Grosso, M. Rebaudengo, M. Sonza Reorda
    DCIS05: XX Conference on Design of Circuits and Integrated Systems, Lisboa, Portugal
  34. A new DFM-proactive technique
    D. Appello, P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda, V. Tancorre
    SDD'05: 2nd IEEE International Workshop on Silicon Debug and Diagnosis
  35. Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores
    P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda
    MTV'05: 6th International Workshop on Microprocessor Test and Verification, Austin (TX), USA, Nov. 3-4, 2005, pp. 55-60
  36. An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors
    P. Bernardi, L. Bolzani, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DFT2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 307-312
  37. On-line Detection of Control-Flow Errors in SoCs by means of an Infrastructure IP core
    P. Bernardi, L. Bolzani, M. Rebaudengo, M. Sonza Reorda, F. Vargas, M. Violante
    IEEE Dependable Systems and Networks Symposium, july 2005, pp. 50 -58
  38. Exploiting an Infrastructure IP to Reduce Memory Diagnosis Costs in SoCs
    P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda
    ETS 2005: IEEE European Test Symposium, 2005, pp. 202-207
  39. A Tool for Supporting and Automating the Test of Complex System-on-Chips
    P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda, D. Appello, R.Mattiuzzo, V.Tancorre
    ITSW 2005: IEEE International Test Synthesis Workshop, 2005, "Best Student Paper Award"
  40. On the Diagnosis of SoCs including multiple Memory Cores
    P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda
    DDECS 2005: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, 2005, pp. 75-80
  41. Integrating BIST techniques for on-line SoC testing
    A. Manzone, P. Bernardi, M. Grosso, M. Rebaudengo, E. Sanchez, M. Sonza Reorda
    IOLTS 2005: IEEE International On-line Testing Symposium, 2005, pp. 235-240
  42. Improved Software-Based Processor Control-Flow Errors Detection Technique
    O. Goloubeva, M. Rebaudengo, M. Sonza Reorda, M. Violante
    RAMS2005: The Annual Reliability and Maintainability Symposium, 2005, Session 14B
  43. Software Techniques for Dependable Computer-based Systems
    O. Goloubeva, M. Rebaudengo, M. Sonza Reorda, M. Violante
    chapter in "Space radiation environment and its effects on spacecraft components and systems", C padu s d., Toulouse (France), ISBN 2-85428-654-5, 2004, pp. 461-480
  44. A new approach to software-implemented fault tolerance
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    JETTA: The Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers, N. 20, August 2004, pp. 433-437
  45. Exploiting an I-IP for In-field SOC test
    P. Bernardi, M. Rebaudengo, M. Sonza Reorda
    DFT'04: The 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 404-412
  46. Using Infrastructure IPs to support SW-based Self-Test of Processor Cores
    P. Bernardi, M. Rebaudengo, M. Sonza Reorda
    MTV'04: 5th International Workshop on Microprocessor Test and Verification, 2004, pp. 22-27
  47. Hybrid Soft Error Detection by means of Infrastructure IP cores
    L. Bolzani, M. Rebaudengo, M. Sonza Reorda, F. Vargas, M. Violante
    IOLTS2004: IEEE International On-Line Testing Symposium, 2004, pp. 79-84
  48. Approaching production diagnostic for BIST-based testing
    D. Appello, P. Bernardi, D. Chindamo, M. Rebaudengo, M. Sonza Reorda, V. Tancorre
    SDD'04: 1st IEEE International Workshop on Silicon Debug and Diagnosis
  49. An Infrastructure IP for Soft Error Detection
    L. Bolzani, M. Rebaudengo, M. Sonza Reorda, F. Vargas, M. Violante
    LATW'04: IEEE Latin-American Test WorkShop
  50. On the diagnosis of embedded memory cores through Programmable BIST
    D. Appello, P. Bernardi, M. Rebaudengo, M. Sonza Reorda, V. Tancorre
    TRP'04: 5th IEEE International Workshop on Test Resource Partitioning
  51. A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques
    D. Appello, A. Fudoli, V. Tancorre, P. Bernardi, F. Corno, M. Rebaudengo, M. Sonza Reorda
    Journal of Electronic Testing: Theory and Applications, Volume 20, Issue 1, Kluwer Academic Publishers, Feb 2004, pp. 79-87
  52. Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA
    M. Bellato, P. Bernardi, D. Bortolato, A. Candelori, M. Ceschia, A. Paccagnella,, M. Rebaudengo, M. Sonza Reorda, M. Violante, P. Zambolin
    DATE2004: Design, Automation and Test in Europe, 2004, pp. 188-193
  53. Impact of data cache memory on the single event upset-induced error rate of microprocessors
    F. Faure, R. Velazco, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 50, No. 6, December 2003, pp. 2101-2106
  54. Identification and classification of single-event upsets in the configuration memory of sram-based fpgas
    M. Ceschia, M. Violante, M. Sonza Reorda, A. Paccagnella, P. Bernardi, M. Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, A. Candelori
    IEEE Transactions on Nuclear Science, Vol. 50, No. 6, December 2003, pp. 2088-2094
  55. Accurate Analysis of Single Event Upsets in a Pipelined Microprocessor
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    Journal of Electronic Testing: Theory and Applications, Vol. 19, No. 5, October 2003, pp. 577-584
  56. Soft-error Detection Using Control Flow Assertions
    O. Goloubeva, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DFT2003: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2003, pp. 581-588
  57. A programmable BIST approach for the diagnosis of embedded memory cores
    D. Appello, P. Bernardi, A. Fudoli, M. Rebaudengo, M. Sonza Reorda, V. Tancorre, M. Violante
    ETW03: 8th IEEE European Test Workshop (Formal Proceedings), The Netherlands, May 25-28, 2003, pp. 101-102
  58. An efficient algorithm for the extraction of compressed diagnostic information from embedded memory cores
    P. Bernardi, M. Rebaudengo, M. Sonza Reorda
    ETFA 2003: 9th IEEE International Conference on Emerging Technologies and Factory Automation, Lisbon, Portugal, 16-19 September 2003
  59. New Techniques for efficiently assessing reliability of SOCs
    P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    Microelectronics Journal, Vol. 34, No. 1, January 2003, pp. 53-61, Elsevier Science, Amsterdam, Netherland.
  60. Exploiting programmable BIST for the diagnosis of embedded memory cores
    D. Appello, P. Bernardi, A. Fudoli, M. Rebaudengo, M. Sonza Reorda, V. Tancorre, M. Violante
    ITC2003: IEEE International Test Conference, 2003, pp. 379-385
  61. Analyzing SEU Effects in SRAM-based FPGAs
    M. Violante, M. Ceschia, M. Sonza Reorda, A. Paccagnella, P. Bernardi, M. Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, and A. Candelori
    IOLTS2003: IEEE International On-Line Testing Symposium, 2003, pp. 119-123
  62. A P1500 compatible microprocessor-based approach for the test of Embedded Flash Memories
    P. Bernardi, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DATE2003: Design, Automation and Test in Europe, 2003, pp. 720-725
  63. An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    DATE2003: Design, Automation and Test in Europe, 2003, pp. 602-607
  64. A new Software-based technique for low-cost Fault-Tolerant application
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    RAMS2003: The Annual Reliability and Maintainability Symposium, 2003, pp. 25-28
  65. A New Methodology for Debugging Embedded Cores
    D. Appello, L. Bouzaida, A. Fudoli, R. Mattiuzzo, R. Kapur, M. Rebaudengo, M. Sonza Reorda
    TRP2002: Test Resource Partitioning Workshop 2002, Baltimore, MD (USA), October, 10-11, 2002
  66. Coping With SEUs/SETs in Microprocessors by means of Low-Cost Solutions: A Comparative Study
    M. Rebaudengo, M. Sonza Reorda, M. Violante, B. Nicolescu, R. Velazco
    IEEE Transactions on Nuclear Science, Vol. 49, No. 3, June 2002, pp. 1491-1495
  67. An FPGA-based approach for speeding-up Fault Injection campaigns on safety-critical circuits
    P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    Journal of Electronic Testing:Theory and Applications, Vol. 18, No. 3, June 2002, pp. 261-271
  68. A Software Fault Tolerance Method for Safety-Critical Systems: Effectiveness and Drawbacks
    B. Nicolescu, R. Velazco, M. Sonza Reorda, M. Rebaudengo, M. Violante
    SBCCI: 15th IEEE Symposium on Integrated Circuits and Systems Design, Porto Alegre (Brasil), Septempber 2002, pp. 101-106
  69. A new functional fault model for FPGA Application-Oriented testing
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    DFT2002: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 372-380
  70. Simulation-based analysis of SEU effects on SRAM-based FPGAs
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    FPL2002: International Conference on Field Programmable Logic and Application, 2002, pp. 607-615
  71. Initializability Analysis of Synchronous Sequential Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, G. Squillero
    ACM Transactions on Design Automation of Electronic Systems, April 2002, pp. 249-264
  72. A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques
    D. Appello, A. Fudoli, V. Tancorre, F. Corno, M. Rebaudengo, M. Sonza Reorda
    IOLTW2002: IEEE International On-line Testing Workshop, 2002, pp. 112-116
  73. Analysis of SEU effects in a pipelined processor
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    IOLTW2002: IEEE International On-line Testing Workshop, 2002, pp. 206-210
  74. A new approach to software-implemented fault tolerance
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    LATW2002: IEEE Latin American Test Workshop, 2002
  75. A P1500 compliant BIST-based approach to embedded RAM Diagnosis
    D. Appello, F. Corno, M. Giovinetto, M. Rebaudengo, M. Sonza Reorda
    ATS, IEEE Asian Test Symposium, 2001
  76. FPGA-based Fault Injection for Microprocessor Systems
    P. L. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    ATS, IEEE Asian Test Symposium, 2001, pp. 304-309
  77. Exploiting Circuit Emulation for Fast Hardness Evaluation
    P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 48, No. 6, December 2001, pp. 2210-2216
  78. A source-to-source compiler for generating dependable software
    M. Rebaudengo, M. Sonza Reorda, M. Torchiano, M. Violante
    SCAM, IEEE International Workshop on Source Code Analysis and Manipulation, 2001, pp. 33-42
  79. Exploiting FPGA-based Techniques for Fault Injection Campaigns on VLSI Circuits
    P. L. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DFT, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2001, pp. 250-258
  80. FPGA-based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits
    P. L. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    FPL 2001, 11th International Conference on Field Programmable Logic and Applications, Belfast (UK), August, 2001, pp. 493-502
  81. Exploiting FPGA for accelerating Fault Injection Experiments
    P. L. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IOLTW, IEEE On-Line Testing Workshop, Taormina (Italy), July 9-11, 2001, pp. 9-13
  82. System Safety through Automatic High-level Code Transformations: an Experimental Evaluation
    M. Rebaudengo, M. Sonza Reorda, M. Violante, P. Cheynet, B. Nicolescu, R. Velazco
    DATE: IEEE Design, Automation & Test in Europe Conference, Munich (Germany), 13-16 March 2001, pp. 297-301
  83. Experimentally evaluating an automatic approach for generating safety-critical software with respect to transient errors
    P. Cheynet, B. Nicolescu, R. Velazco, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 47, No. 6, December 2000, pp. 2231-2236
  84. Dependability Evaluation through Effective Fault Injection Techniques on VHDL Descriptions
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    ISATA 2000: Automotive and Transportation Technology, Dublin (Ireland), September 2000, pp. 171-179
  85. GA-Based Verification of Network Protocols Performance
    M. Baldi, F. Corno, M. Rebaudengo, M. Sonza Reorda, G. Squillero
    [chapter in] Telecommunications Optimizations: Heuristic and Adaptive Techniques, edited by D. Corne and M. Oates, Wiley and Sons, August 2000, ISBN 0-471-98855-3, pp. 185-198
  86. Behavioral-level Test Vector Generation for System-on-Chip Designs
    M. Lajolo, L. Lavagno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IEEE International High Level Design Validation Workshop, The Claremont Resort & Spa, Berkeley, California, November 8-10 2000, pp. 21-26
  87. Speeding-up Fault Injection Campaigns in VHDL models
    B. Parrotta, M. Rebaudengo, M. Sonza Reorda, M. Violante
    19th International Conference on Computer Safety, Reliability and Security, Safecomp 2000, Rotterdam, The Nederlands, October 2000, pp. 27-36
  88. An experimental evaluation of the effectiveness of automatic rule-based transformations for safety-critical applications
    M. Rebaudengo, M. Sonza Reorda, M. Torchiano, M. Violante
    DFT'00, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, October 2000, pp. 257-265
  89. Evaluating the effectiveness of a Software Fault-Tolerance technique on RISC- and CISC-based architectures
    M. Rebaudengo, M. Sonza Reorda, M. Violante, P. Cheynet, B. Nicolescu, R. Velazco
    IOLTW2000: International On-Line Test Workshop, Mallorca (Spain), July 2000, pp. 17-20
  90. New Techniques for Accelerating Fault Injection in VHDL descriptions
    B. Parrotta, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IOLTW2000: International On-Line Test Workshop, Mallorca (Spain), July 2000, pp. 61-66
  91. Automatic Test Bench Generation for Simulation-based Validation
    M. Lajolo, L. Lavagno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    CODES2000: IEEE International Workshop on Hardware/Software Codesign, San Diego (USA), May 2000, pp. 136-140
  92. System-level Test Bench Generation in a Co-design Framework
    M. Lajolo, L. Lavagno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    ETW2000: European Test Workshop, May 2000, pp. 25-30
  93. Low Power BIST via Hybrid Cellular Automata
    F. Corno, M. Rebaudengo, M. Sonza Reorda, G. Squillero, M. Violante
    VTS2000: 18th IEEE VLSI Test Symposium, Montreal, Canada, May 2000, pp. 29-34
  94. Prediction of Power Requirements for High-Speed Circuits
    F. Corno, M. Rebaudengo, M. Sonza Reorda, G. Squillero, M. Violante
    EvoTel2000: European Workshops on Telecommunications, Edinburgh (UK), May 2000, pp. 247-254
  95. Evaluating System Dependability in a Co-Design Framework
    M. Lajolo, L. Lavagno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DATE2000: Design, Automation and Test in Europe, Paris (F), March 2000, pp. 586-590
  96. Optimal Vector Selection for Low Power BIST
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DFT99: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, November 1-3 1999 - Albuquerque, New Mexico (USA), pp. 219-226
  97. Soft-error Detection through Software Fault-Tolerance techniques
    M. Rebaudengo, M. Sonza Reorda, M. Torchiano, M. Violante
    DFT99: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, November 1-3 1999 - Albuquerque, New Mexico (USA), pp. 210-218
  98. FlexFi: a flexible Fault Injection environment for microprocessor-based systems
    A. Benso, M. Rebaudengo, M. Sonza Reorda
    SAFECOMP 1999: 18th International Conference on Computer Safety, Reliability and Security, (Lecture Notes in Computer Science, Springer Verlag, A. Pasquini (Ed.)), pp. 323-335
  99. On Reducing the Peak Power Consumption of Test Sequences
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    European Conference on Circuit Theory and Design, Stresa, Italy, August 1999, pp. 247-250
  100. A Peak-Power Estimation Algorithm for Sequential Circuits
    F. Corno, M. Rebaudengo, M. Sonza Reorda, V. Speranza, M. Violante
    European Conference on Circuit Theory and Design, Stresa, Italy, August 1999, pp. 896-899
  101. A New BIST Architecture for Low Power Circuits
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    ETW99: IEEE European Test Workshop, Konstanz(D), May 1999
  102. Test Pattern Generation under Low Power Constraints
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    R. Poli, H-M. Voigt, S. Cagnoni, D. Corne, G. Smith, T. Fogarty (eds.), Evolutionary Image Analysis, Signal Processing and Telecommunications First European Workshops, EvoIASP'99 and EuroEcTel'99 Goteborg, Sweden, May 1999 Joint Proceedings, Springer LNCS, 1999, pp. 162-170
  103. Evaluating the Fault Tolerance Capabilities of Embedded Systems via BDM
    M. Rebaudengo, M. Sonza Reorda
    VTS99: 17th IEEE VLSI Test Symposium, Dana Point (USA), April 1999, pp. 452-457
  104. ALPS: A Peak Power Estimation Tool for Sequential Circuits
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    GLS-VLSI99: 8th Great Lakes Symposium on VLSI, Ypsilanti MI (USA), March 4-6 1999, pp. 350-353
  105. Transformation-based Peak Power Reduction for Test Sequences
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    poster at VOLTA99: IEEE Alessandro Volta Memorial Workshop on Low Power Design, Como (ITALY), March 3-5 1999, pp. 78-83
  106. A Low-Cost Programmable Board for Speeding-Up Fault Injection in Microprocessor-Based Systems
    A. Benso, P. L. Civera, M. Rebaudengo, M. Sonza Reorda
    RAMS99: Annual Reliability and Maintainability Symposium, Washington, DC (USA), January 1999, pp. 171-177
  107. Fault Injection for Embedded Microprocessor-based Systems
    A. Benso, M. Rebaudengo, M. Sonza Reorda
    Journal of Universal Computer Science (Special Issue on Dependability Evaluation and Validation), Vol. 5, No. 5, pp. 693-711
  108. A Fault Injection Environment for Microprocessor-based Boards
    A. Benso, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    ITC98: IEEE International Test Conference, Washington (USA), September 1998, pp. 768-773
  109. EXFI: a low cost Fault Injection System for embedded Microprocessor-based Boards
    A. Benso, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    ACM Transactions on Design Automation of Electronic Systems, Vol. 3, Number 4, October 1998, pp. 626-634
  110. An Integrated HW and SW Fault Injection Environment for Real-Time Systems
    A. Benso, M. Rebaudengo, M. Sonza Reorda, P. L. Civera
    DFT98, 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, November 2-4 1998, Austin, Texas, pp. 117-122
  111. Exploiting the Background Debugging Mode in a Fault Injection system
    P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    IPDS: The 3rd Annual IEEE International Computer Performance & Dependability Symposium, Durham (NC), September 7-9 1998, pag. 277
  112. Experiences in the use of evolutionary techniques for testing digital circuits
    F. Corno, M. Sonza Reorda, M. Rebaudengo
    Applications and Science of Neural Networks, Fuzzy Systems, and Evolutionary Computation, SPIE 1998 Annual Meeting
    Invited paper
  113. A Hybrid Fault Injection Methodology for Real Time Systems
    A. Benso, P. L. Civera, M. Rebaudengo, M. Sonza Reorda, A. Ferro
    Digest of FastAbstracts: FTCS-28, The 28th Annual International Symposium on Fault-Tolerant Computing, June 23-25, Munich (Germany), pp. 74-75
  114. Evaluating cost and effectiveness of software redundancy techniques for hardware errors detection
    M. Rebaudengo, M. Sonza Reorda
    Digest of FastAbstracts: FTCS-28, The 28th Annual International Symposium on Fault-Tolerant Computing, June 23-25, Munich (Germany), pp. 88-89
  115. A Test Pattern Generation methodology for low power consumption
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    VTS98: 16th IEEE VLSI Test Symposium, Monterey, CA (USA), April 1998
  116. Algoritmi da taglio
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, S. Bisotto
    La Rivista del Vetro, Miller Freeman ed., Milano (Italy), anno 22, n. 2, marzo 1998, pp. 86-98
  117. Fault-List Collapsing for Fault Injection Experiments
    A. Benso, M. Rebaudengo, L. Impagliazzo, P. Marmo
    RAMS98: Annual Reliability and Maintainability Symposium, Anaheim, CA (USA), January 1998, pp. 383-388
  118. GA-based Performance Analysis of Network Protocols
    M. Baldi, F. Corno, M. Rebaudengo, G. Squillero
    ICTAI97: 9th IEEE International Conference on Tools with Artificial Intelligence, Newport Beach, CA (USA), November 1997, pp. 118-124
  119. Exploiting Symbolic Techniques within Genetic Algorithms for Power Optimization
    S. Chiusano, F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    ICTAI97: 9th IEEE International Conference on Tools with Artificial Intelligence, Newport Beach, CA (USA), November 1997
    CV. Ramamoorthy Best Paper Award
  120. Simulation-Based Verification of Network Protocols Performance
    M. Baldi, F. Corno, M. Rebaudengo, P. Prinetto, M. Sonza Reorda, G. Squillero
    CHARME97: Advanced Research Working Conference on Correct Hardware Design and Verification Methods, Montr? al, Quebec, Canada, October 1997, pp. 236-251
  121. Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments
    A. Benso, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, J. Raik, R. Ubar
    DFT97: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Paris (F), November 1997
  122. A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, G. Squillero
    ATS97: The Sixth IEEE Asian Test Symposium, Akita (JP), November 1997, pp. 56-61
    Also included in the 10th Anniversary Compedium of Papers from Asian Test Symposium
  123. Guaranteeing Testability in Re-encoding for Low Power
    S. Chiusano, F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    ATS97: The Sixth IEEE Asian Test Symposium, Akita (JP), November 1997
  124. Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, M. Violante
    ATS97: The Sixth IEEE Asian Test Symposium, Akita (JP), November 1997
  125. Optimizing Area Loss in Flat Glass Cutting
    S. Bisotto, F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    GALESIA97, IEE/IEEE International Conference on Genetic ALgorithms in Engineering Systems: Innovations and Applications, Glasgow (UK), September 1997
  126. A New Approach for Initialization Sequences Computation for Synchronous Sequential Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, G. Squillero
    ICCD97, October 1997, Austin, Texas (USA), pp. 381-386
  127. Boolean Function Manipulation on a Parallel System using BDDs
    R. Ansaloni, F. Bianchi, F. Corno, M. Rebaudengo, M. Sonza Reorda
    HPCN Europe 1997: International Conference and exhibition on High-Performance Computing and Networking, Vienna, Austria, April 1997, in Lecture Notes in Computer Science 1225, Springer, pp. 916-928
  128. A new approach to build a low-level Malicious Fault List starting from High-level description and Alternative Graphs
    A. Benso, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, R. Ubar
    ED&TC97: IEEE European Design and Test Conference, Paris (F), March 1997
  129. New Static Compaction Techniques of Test Sequences for Sequential Circuits
    F. Corno, M. Rebaudengo, P. Prinetto, M. Sonza Reorda
    ED&TC97: IEEE European Design and Test Conference, Paris (F), March 1997, pp. 37-43
  130. SAARA: a Simulated Annealing Algorithm for Test Pattern Generation for Digital Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    SAC97: 12th Annual ACM Symposium on Applied Computing, San Jose, CA (USA), February 1997, pp. 228-232
  131. Faulty Behavior Observation on a Microprocessor System through a VHDL Simulation-Based Fault Injection Experiment
    A. Amendola, A. Benso, F. Corno, L. Impagliazzo, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    IEEE EURO-VHDL96, Geneva (Switzerland), September 1996
  132. Exploiting Competing Subpopulations for Automatic Generation of Test Sequences for Digital Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    Fourth International Conference on Parallel Problem Solving from Nature, Berlin (Germany), September 1996
  133. Partial Scan Flip Flop Selection for Simulation-based Sequential ATPGs
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    IEEE International Test Conference, Washington (USA), October 1996
  134. Comparing topological, symbolic and GA-based ATPGs: an experimental approach
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    IEEE International Test Confernce, Washington (USA), October 1996
  135. A Parallel Genetic Algorithm for Automatic Generation of Test Sequences for Digital Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    International Conference on High-Performance Computing and Networking, Brussels (Belgium), April 1996
  136. Advanced Techniques for GA-based sequential ATPGs
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, R. Mosca
    IEEE Design & Test Conference, Paris (F), March 1996
  137. Il ruolo delle tecniche di fault injection nell'analisi dell'affidabilit? dei sistemi
    A. Benso, F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    AEI (Automazione Energia Informazione), Vol. 83, N. 10, Ottobre 1996, pp. 63/807-69/813
  138. On-line Testing of an Off-the-Shelf Microprocessor Board for Safety-critical Applications
    F. Corno, M. Damiani, L. Impagliazzo, P. Prinetto, M. Rebaudengo, G. Sartore, M. Sonza Reorda
    EDCC Conference, Taormina (Italy), October 1996
  139. GALLO: a Genetic Algorithm for Floorplan Area Optimization
    M. Rebaudengo, M. Sonza Reorda
    IEEE Transactions on Computer-Aided Design, August 1996, Vol. 15, No. 8, pp. 991-1000
  140. GATTO: a Genetic Algorithm for Automatic Test Pattern Generation for Large Synchronous Sequential Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    IEEE Transactions on Computer-Aided Design, August 1996, Vol. 15, No. 8, pp. 943-951
  141. Uso di Tecniche Evolutive per la Risoluzione di problemi di CAD Elettronico
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    Processori Dedicati, a cura di Lanfranco Lopriore, Fabrizio Luccio e Maria Marinaro, Collana CNR/Progetto Finalizzato "Sistemi Informatici e Calcolo Parallelo" diretta da Bruno Fadini, Franco Angeli Editore
  142. Improving Topological ATPG with Symbolic Techniques
    F. Corno, U. Glaeser, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, H. T. Vierhaus
    IEEE VLSI Test Symposium, Princeton (USA), April 1995
  143. A Portable ATPG tool for Parallel and Distributed Systems
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, E. Veiluva
    IEEE VLSI Test Symposium, Princeton (USA), April 1995
  144. GARDA: a Diagnostic ATPG for Large Synchronous Sequential Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    ED&TC95: IEEE European Design and Test Conference, Paris, March 1995
  145. A Data Parallel Algorithm for Boolean Function Manipulation
    S. Gai, M. Rebaudengo, M. Sonza Reorda
    5th IEEE Symposium on the Frontiers of Massively Parallel Computation, McLean (USA), February 1995
  146. A PVM tool for Automatic Test Generation on Parallel and Distributed Systems
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, E. Veiluva
    International Conference on High-Performance Computing and Networking, Milan (Italy), May 1995, Lecture Notes in Computer Science, Ed. Springer
  147. Exploiting Massively Parallel Architectures for the Solution of Diffusion and Propagation Problems
    P. P. Delsanto, S. Biancotto, M. Scalerandi, M. Rebaudengo, M. Sonza Reorda
    International Conference on High-Performance Computing and Networking, Milan (Italy), May 1995, Lecture Notes in Computer Science, Ed. Springer
  148. An Improved Data Parallel Algorithm for Boolean Function Manipulation using BDDs
    S. Gai, M. Rebaudengo, M. Sonza Reorda
    3th IEEE/Euromicro Workshop on Parallel and Distributed Processing, Sanremo (Italy), January 1995
  149. Exploiting Massively Parallel Architectures for the Analysis of Growth Phenomena
    P. P. Delsanto, G. Kaniadakis, M. Scalerandi, M. Rebaudengo, M. Sonza Reorda
    AICA94: Congresso Annuale Associazione Italiana per l'Informatica ed il Calcolo Automatico, Palermo (I), September 1994
  150. Parallel Processing Analysis of the 1-D KPZ growth equation
    P. P. Delsanto, G. Kaniadakis, M. Scalerandi, M. Rebaudengo, M. Sonza Reorda
    6-th EPS-APS International Conference on Physics Computing, Lugano (CH), August 1994
  151. A Genetic Algorithm for Floorplan Area Optimization
    M. Rebaudengo, M. Sonza Reorda
    ICEC94: IEEE Conference on Evolutionary Computation, Orlando, FL (USA), June 1994
  152. GATTO: an Intelligent Tool for Automatic Test Pattern Generation for Digital Circuits
    P. Prinetto, M. Rebaudengo, M. Sonza Reorda, E. Veiluva
    IEEE International Conference on Tools with Artificial Intelligence, New Orleans (USA), November 1994
  153. An Automatic Test Pattern Generator for Large Sequential Circuits based on Genetic Algorithms
    P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    ITC94: IEEE International Test Conference, Washington D. C. (USA), October 1994
  154. A Data Parallel Approach to Boolean Function Manipulation using BDDs
    G. Cabodi, S. Gai, M. Rebaudengo, M. Sonza Reorda
    MPCS94: IEEE/EuroMicro International Conference on Massively Parallel Computing Systems, Ischia (I), May 1994
  155. Floorplan Area Optimization using Genetic Algorithms
    M. Rebaudengo, M. Sonza Reorda
    GLS94: 4th IEEE Great Lakes Symposium on VLSI, Notre Dame, IN (USA), March 1994
  156. A Package for Boolean Function Manipulation on a Massively Parallel SIMD Architecture
    G. Cabodi, S. Gai, M. Rebaudengo, M. Sonza Reorda
    EWPDP94: IEEE/EuroMicro Workshop on Parallel and Distributed Processing, Malaga (E), Gennaio 1994
  157. Exploiting a Workstation Network for Automatic Generation of Test Patterns for Digital Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, A. R. Meo, E. Veiluva
    AICA94: Congresso Annuale Associazione Italiana per l'Informatica ed il Calcolo Automatico, Palermo (I), September 1994
  158. Efficient Parallel Hash Table Methods for a Boolean Function Manipulation Package for CM-200
    M. Rebaudengo, M. Sonza Reorda
    Science on the Connection Machine System (Editors: J. M. Alimi, A. Serna, H. Scholl), Proceedings of the Second European CM Users Meeting, Meudon (F), 11-14 Ottobre 1993, pp. 59-68
  159. A BDD Package for a Massively Parallel SIMD Architectures
    G. Cabodi, S. Gai, M. Rebaudengo, M. Sonza Reorda
    ICVC93: IEEE International Conference on VLSI and CAD, Tajeon (South Korea), Novembre 1993, pp. 332-335
  160. Hybrid Genetic Algorithms for the Traveling Salesman Problem
    P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    International Conference on Neural Networks and Genetic Algorithms, Innsbruck (A), Aprile 1993, pp.559-566
  161. An Experimental Analysis of effects of Migration in Paralell Genetic Algorithms
    M. Rebaudengo, M. Sonza Reorda
    EWPDP93: IEEE/Euromicro Workshop on Parallel and Distributed Processing, Gran Canaria (E), Gennaio 1993, pp.232-238
  162. Uso di sistemi paralleli nella verifica di circuiti sequenziali
    P. Camurati, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    Congresso Annuale AICA'92, Torino (I), October 1992, Volume I, pp. 115-124
  163. Improved techniques for multiple stuck-at-fault analysis using single stuck-at fault test
    P. Camurati, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    ISCAS 92: IEEE International Symposium on Circuits and Systems, San Diego, CA (USA), Maggio 1992, pp. 383-386
  164. Centralized vs. Distributed Implementation of FSM Equivalence Verification on a Parallel System, in Parallel Computing
    P. Camurati, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    from Theory to Sound Practice, ed. by W. Joosen and E. Milgrom, IOS Press, 1992, pp. 554-557
  165. Efficient Verification of Sequential Circuits on a Parallel Systems
    P. Camurati, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    EDAC92: IEEE European Conference on Design Automation, Brussels (B), Marzo 1992, pp.64-67