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Papers by M. Sonza Reorda

  1. Fault Injection Analysis of Transient Faults in Clustered VLIW Processors
    L. Sterpone, D. Sabena, S. Campagna, M. Sonza Reorda
    14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, April 13-15, Cottbus, Germany, 2011
  2. La formazione a distanza al Politecnico di Torino: nuovi modelli e strumenti
    S. Barbagallo, R. Bertonasco, F. Corno, M. Mezzalama, M. Sonza Reorda, E. Venuto
    Didamatica 2011, Informatica e Didattica, Torino (IT), 4-6 may 2011
  3. Advanced technologies for transient faults detection and compensation
    M. Sonza Reorda, L. Sterpone, M. Violante
    book chapter on IGI [accepted for publication on]
  4. Microprocessor Software-Based Self-Testing.
    M. Psarakis, D. Gizopoulos, E. Sanchez, M. Sonza Reorda
    IEEE Design & Test of Computers, May/June 2010, pp. 4-18
  5. Analysis of Root Causes of Alpha Sensitivity Variations on Microprocessors Manufactured using Different Cell Layouts
    P. Rech, M. Grosso, F. Melchiori, D. Loparco, D. Appello, L. Dilillo, A. Paccagnella, M. Sonza Reorda
    IEEE International On-Line Testing Symposium (IOLTS), July 5-7, 2010, Corfu Island, Greece (accepted for publication)
  6. An on-line fault detection technique based on embedded debug features
    M. Grosso, M. Sonza Reorda, M. Portela-Garcia, M. Garcia Valderas, C. Lopez-Ongil, L. Entrena
    IEEE International On-Line Testing Symposium (IOLTS), July 5-7, 2010, Corfu Island, Greece (accepted for publication)
  7. A Software-based self-test methodology for system peripherals
    M. Grosso, W.J. Perez H, D. Ravotto, E. Sanchez, M. Sonza Reorda, J. Velasco Medina
    IEEE European Test Symposium (ETS 10), May 24-28, 2010, Prague, Czech Republic (accepted for publication)

  8. P. Rech, A. Paccagnella, M. Grosso, M. Sonza Reorda, F. Melchiori, D. Loparco, D. Appello
  9. A Hybrid Approach for Detection and Correction of Transient Faults in SoCs
    P. Bernardi, L. Bolzani Poehls, M. Grosso, M. Sonza Reorda
    IEEE Transactions on Dependable and Secure Computing (accepted for publication)
  10. A Hybrid Approach for Detection and Correction of Transient Faults in SoCs
    P. Bernardi, L. Bolzani Poehls, M. Grosso, M. Sonza Reorda
    IEEE Transactions on Dependable and Secure Computing (accepted for publication)
  11. A hardware accelerated framework for the generation of design validation programs for SMT processors
    D. Ravotto, E. Sanchez, M. Sonza Reorda
    IEEE Design and Diagnostic of Electronic Circuits and Systems, Vienna, April 2010, pp. 289-292
  12. Cumulative Embedded Memory Failure Bitmap Display & Analysis
    N. Campanelli, T. Kerekes, P. Bernardi, M. de Carvalho, A. Panariti, M. Sonza Reorda, D. Appello, M. Barone
    IEEE Design and Diagnostic of Electronic Circuits and Systems, Vienna, April 2010, pp. 255-260
  13. A Novel Scalable and Reconfigurable Emulation Platform for Embedded Systems Verification
    M. Di Marzio, M. Grosso, M. Sonza Reorda, L. Sterpone, G. Audisio, M. Sabatini
    IEEE International Symposium on Circuits and Systems, pp. 865 - 868, 2010
  14. Alpha-induced SEU Sensitivity Dependencies on Logic Cell Layout Configurations: Preliminary Results Analysis
    D. Appello, P. Bernardi, M. Grosso, F. Melchiori, A. Paccagnella, P. Rech, M. Sonza Reorda
    2nd IEEE Workshop on Design for Reliability and Variability (DRV 2009), November 5-6, 2009, Austin, TX, USA (in conjunction with ITC Test Week 2009)
  15. On the Generation of Functional Test Programs for the Cache Replacement Logic
    W. J. Perez H., D. Ravotto, E. Sanchez, M. Sonza Reorda, A. Tonda
    ATS 2009: Proceedings of the 2009 Asian Test Symposium, pp. 418-423
  16. Evaluating Alpha-induced Soft Errors in Embedded Microprocessors
    P. Rech, S. Gerardin, A. Paccagnella, P. Bernardi, M. Grosso, M. Sonza Reorda, D. Appello
    IOLTS 2009: 15th IEEE International On-line Testing Symposium, Sesimbra-Lisbon, Portugal, 2009, pp. 69-74
  17. Exploiting Embedded FPGA in On-line Software-based Test Strategies for Microprocessor Cores
    M. Grosso, M. Sonza Reorda
    IOLTS 2009: 15th IEEE International On-line Testing Symposium, Sesimbra-Lisbon, Portugal, 2009, pp. 95-100
  18. DfT Reuse for Low-Cost Radiation Testing of SoCs: A Case Study
    D. Appello, P. Bernardi, S. Gerardin, M. Grosso, A. Paccagnella, P. Rech, M. Sonza Reorda
    27th IEEE VLSI Test Symposium (VTS 09), May 3 - 7, 2009, Santa Cruz, CA, USA, pp. 276-281
  19. Automatic Functional Stress Pattern Generation for SoC Reliability Characterization
    D. Appello, P. Bernardi, R. Cagliesi, M. Giancarlini, M. Grosso, E. Sanchez, M. Sonza Reorda
    ETS 2009: 14th IEEE European Test Symposium, Sevilla, Spain, 2009, pp. 93-98
  20. Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug
    P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda
    IET Computers & Digital Techniques, Vol. 4, N. 2, pp. 104-113, March 2010
  21. Test Program Generation for Communication Peripherals in Processor-Based Systems-on-Chip.
    A. Apostolakis, Gizopoulos D., M. Psarakis , D. Ravotto, M. Sonza Reorda
    IEEE Design & Test of Computers
  22. Effective Diagnostic Pattern Generation Strategy for Transition-Delay Faults in Full-scan SoCs
    D. Appello, P. Bernardi, M. Grosso, E. Sanchez, M. Sonza Reorda
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 17, NO. 11, p. 1654-1659, NOVEMBER 2009
  23. A Deterministic Methodology for Identifying Functionally Untestable Path-Delay Faults in Microprocessor Cores
    P. Bernardi, M. Grosso, E. Sanchez, M. Sonza Reorda
    MTV'08: 9th International Workshop on Microprocessor Test and Verification, Austin (TX), USA, Dec. 8-10, 2008, pp. 103-108
  24. A Case Study on SoC Low-Cost Silicon Debug and Diagnosis
    D. Appello, P. Bernardi, M. Grosso, M. Rotigni, M. Sonza Reorda, V. Tancorre
    SDD08: 5th IEEE International Workshop on Silicon Debug and Diagnosis, San Diego (CA), USA, April 30th - May 1st, 2008
  25. An Automatic Functional Stress Pattern Generation Technique Suitable for SoC Reliability Characterization
    D. Appello, P. Bernardi, M. Bruno, R. Cagliesi, M. Giancarlini, M. Grosso, E. Sanchez, M. Sonza Reorda
    2nd IEEE International Workshop on Automated Test Equipment: Vision ATE 2020, Santa Clara (CA), USA, October 30-31, 2008
  26. Software-Based Self-Test Strategy for Data Cache Memories Embedded in SoCs
    W. J. Perez H., J. Velasco Medina, D. Ravotto, E. Sanchez, M. Sonza Reorda
    The IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, 2008, pp. 339 - 344
  27. A Hybrid Approach to the Test of Cache Memory Controllers Embedded in SoCs
    W. J. Perez, J. Velasco-Medina, D. Ravotto, E. Sanchez, M. Sonza Reorda
    14th IEEE International On-Line Testing Symposium, 2008, pp. 143-148
  28. An Effective technique for the Automatic Generation of Diagnosis-oriented Programs for Processor Cores
    P. Bernardi, E. Sanchez, M. Schillaci, G. Squillero, M. Sonza Reorda
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008, Vo. 27, No. 3, pp. 570-574, March 2008
  29. Exploiting MOEA to Automatically Generate Test Programs for Path-delay Faults in Microprocessors
    P. Bernardi, K. Christou, M. Grosso, M. Michael, E. Sanchez, M. Sonza Reorda
    4th European Workshop on Bio-Inspired Heuristics for Design Automation (EvoHOT2008), March 26-28, 2008, Napoli, Italy, pp. 224-234
  30. A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions
    K. Christou, M. Michael, P. Bernardi, M. Grosso, E. Sanchez, M. Sonza Reorda
    26th IEEE VLSI Test Symposium (VTS 08), Apr. 27 - May 1, 2008, San Diego, CA, USA, pp. 389 - 394.
  31. Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs
    E. L. Rhod, C. A. Lang Lisb?a, L. Carro, M. Sonza Reorda, M. Violante
    JETTA: The Journal of Electronic Testing: Theory and Applications, Springer Netherlands, Volume 24, Numbers 1-3, June 2008, pp. 45 - 56
  32. A Novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers
    P. Bernardi, M. Sonza Reorda
    DATE 2008: IEEE Design, Automation and Test in Europe, 2008, pp. 194 - 199
  33. Automotive Microcontroller End-of-Line Test via Software-Based Methodologies
    W. Di Palma, D. Ravotto, E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero
    MTV2007: 8th International Workshop on Microprocessor Test and Verification, Austin, December 5-6, 2007, pp. 77 - 82
  34. On Automatic Test Block Generation for Peripheral Testing in SoCs via Dynamic FSMs Extraction.
    D. Ravotto, E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero
    MTV2007: 8th International Workshop on Microprocessor Test and Verification, Austin, December 5-6, 2007, pp. 71 - 76
  35. Multi-level Fault Effects Evaluation
    L. Anghel, M. Rebaudengo, M. Sonza Reorda, M. Violante
    chapter in "Radiation Effects on Embedded Systems", Springer (The Netherlands), ISBN 978-1-4020-5645-1, 2007, pp. 69-88
  36. An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains
    J. Lagos-Benites, D. Appello, P. Bernardi, M. Grosso, D. Ravotto, E. Sanchez, M. Sonza Reorda
    DFT2007, 22th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2007, pp. 291-299
  37. Safety Evaluation of NanoFabrics
    M. Grosso, M. Rebaudengo, M. Sonza Reorda
    DFT2007, 22th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2007, pp. 418-426
  38. On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores
    P. Bernardi, M. Grosso, E. Sanchez, M. Sonza Reorda
    ETS2007: 12th IEEE European Test Symposium, Freiburg, Germany, 2007, pp. 179 - 184
  39. Optimization of Self Checking FIR filters by means of Fault Injection Analysis
    S. Pontarelli, L. Sterpone, G.C. Cardarilli, M. Re, M. Sonza Reorda, A. Salsano, M. Violante
    DFT2007, 22th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2007, pp. 96 - 104
  40. An optimized hybrid approach to provide fault detection and correction in SoCs
    L. Bolzani, P. Bernardi, M. Sonza Reorda
    SBCCI2007: IEEE 20th SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, 2007, pp. 342-347
  41. A Software-based Methodology for the Generation of Peripheral Test Sets Based on High-level Descriptions
    L. Bolzani, E. Sanchez, M. Sonza Reorda
    SBCCI2007: IEEE 20th SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, 2007, pp. 348-353
  42. A Hybrid Approach to Fault Detection and Correction in SoCs
    P. Bernardi, L. Bolzani, M. Sonza Reorda
    IOLTS2007: IEEE International On-Line Testing Symposium, 2007, pp. 107-112
  43. An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores
    L. Bolzani, E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero
    IOLTS2007: IEEE International On-Line Testing Symposium, 2007, pp. 265-270
  44. Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders
    S. Pontarelli, L. Sterpone, G.C. Cardarilli, M. Re, M. Sonza Reorda, A. Salsano, M. Violante
    IOLTS2007: IEEE International On-Line Testing Symposium, 2007, pp. 194 - 196
  45. Extended Fault Detection Techniques for Systems-on-Chip
    P. Bernardi, L. Bolzani, M. Sonza Reorda
    DDECS2007: IEEE Design & Diagnostic of Electronic Circuits & Systems, 2007, pp. 55-60
  46. An Enhanced Technique for the Automatic Generation of Effective Diagnosis-oriented Test Programs for Processors
    E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero
    DATE2007: Design, Automation and Test in Europe, April 16-20 2007, pp. 1-6
  47. On Test Program Generation for Peripheral Components in a SoC Resorting to High-Level Metrics
    L. Bolzani, E. Sanchez, M. Sonza Reorda
    LATW2007: 8th IEEE Latin American Test Workshop, Cuzco, Peru, March 11-14, 2007
  48. A new hardware/software platform for the soft-error sensitivity evaluation of FPGA devices
    M. Violante, M. Sonza Reorda, L. Sterpone, A. Manuzzato, S. Gerardin, P. Rech, M. Bagatin, A. Paccagnella, C. Andreani, G. Gorini, A. Pietropaolo, G. Cardarilli, A. Salsano, S. Pontarelli, C. Frost
    LATW2007: 8th IEEE Latin American Test Workshop, Cuzco, Peru, March 11-14, 2007
  49. Hardware-Accelerated Path-Delay Fault Grading of Functional Test Programs for Processor-based Systems
    P. Bernardi, M. Grosso, M. Sonza Reorda
    GLSVLSI2007: 17th ACM Great Lake Symposium on VLSI, Stresa, Italy, March 11-13, 2007, pp. 411-416
  50. A System-layer Infrastructure for SoC Diagnosis
    P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda
    JETTA: The Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers
  51. An Evolutionary Methodology to Enhance Processor Software-Based Diagnosis
    P. Bernardi, E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero
    CEC 2006, IEEE Congress on Evolutionary Computation, Vancouver (BC), Canada, July 16-21, 2006, pp. 859, 864
  52. Evaluating different solutions to design fault tolerant systems with SRAM-based FPGAs
    M. Sonza Reorda, L. Sterpone, M. Violante, F. Lima Kastensmidt, L. Carro
    JETTA: The Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers, Vol. 23, No. 1, February, 2007, pp. 47 - 54
  53. Online hardening of programs against SEUs and SETs
    C.A.L. Lisboa, L. Carro, M. Sonza Reorda, M. Violante
    DFT2006, 21th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2006, pp. 280 - 290
  54. Software-Implemented Hardware Fault Tolerance
    O. Goloubeva, M. Rebaudengo, M. Sonza Reorda, M. Violante
    Springer Science+Business Media, LLC, New York (USA), ISBN: 0-387-26060-9, pages 228
  55. Embedded Memories Diagnosis: An Industrial Workflow
    D. Appello, P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda, V. Tancorre
    ITC06: IEEE International Test Conference, 2006, Santa Clara (CA), USA
  56. System-in-Package Testing: Problems and Solutions
    D. Appello, P. Bernardi, M. Grosso, M. Sonza Reorda
    IEEE Design & Test of Computers, vol. 23, no. 3, pp. 203-211, May-Jun 2006
  57. Hardware-in-the-loop-based Dependability Analysis of Automotive Systems
    M. Sonza Reorda, M. Violante
    IOLTS06: IEEE International On-Line Testing Symposium, 2006, Como, Italy, pp. 229-234
  58. On the Automation of the Test Flow of Complex SoCs
    D. Appello, P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda, V. Tancorre
    VTS06: 24th IEEE VLSI Test Symposium, 2006, Berkeley (CA), USA, pp. 166-171
  59. A pattern ordering algorithm for reducing the size of fault dictionaries
    P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda
    VTS06: 24th IEEE VLSI Test Symposium, 2006, Berkeley (CA), USA, pp. 386-391
  60. Efficient Techniques for Automatic Verification-Oriented Test Set Optimization
    E. Sanchez, G. Squillero, M. Sonza Reorda
    International Journal of Parallel Programming, Vol. 34, Num. 1, March 2006, pp. 93 - 109, Ed. Springer Netherlands
  61. Fault Injection-based Reliability Evaluation of SoPCs
    M. Sonza Reorda, L. Sterpone, M. Violante, M. Portela-Garcia, C. Lopez-Ongil, L. Entrena
    ETS2006: IEEE European Test Symposium, 2006, pp. 75 - 82
  62. Early, Accurate Dependability Analysis of CAN-Based Networked Systems
    J. Perez, M. Sonza Reorda, M. Violante
    IEEE Design & Test of Computers, Vol. 23, No. 1, Jan/Feb. 2006, pp. 38-45
  63. A New Hybrid Fault Detection Technique for Systems-on-a-Chip
    P. Bernardi, L. M. Veiras Bolzani, M. Rebaudengo, M. Sonza Reorda, F. L. Vargas, M. Violante
    IEEE Transactions on Computers, Vol. 55, No. 2, Feb. 2006, pp. 185-198
  64. A new approach to cope with single event upsets in processor-based systems
    M. Schillaci, M. Sonza Reorda, M. Violante
    LATW2006, 7th IEEE Latin-American Test Workshop, Buenos Aires, Argentina, March 26-29 2006, pp. 145-150
  65. A Fault Injection Environment for SoPC's Embedded Microprocessors
    M. Portela-Garcia, L. Sterpone, C. Lopez-Ongil, M. Sonza Reorda, M. Violante
    LATW2006, 7th IEEE Latin-American Test Workshop, Buenos Aires, Argentina, March 26-29 2006, pp. 68-73
  66. An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs
    P. Bernardi, E. Sanchez, M. Schillaci, G. Squillero, M. Sonza Reorda
    IEEE DATE2006: Design, Automation and Test in Europe, 2006, pp. 412-417
    BEST PAPER AWARD at IEEE DATE 2006
  67. Test Program Generation From High-level Microprocessor Descriptions
    E. Sanchez, M. Sonza Reorda, G. Squillero
    [chapter in] Test and validation of hardware/software systems starting from system-level descriptions, Edited by M. Sonza Reorda, M. Violante, Z. Peng, Springer publisher, 2005, 179 p, ISBN: 1-85233-899-7, pp. 83-106
  68. An I-IP for the Debug of Microprocessor Cores
    D. Appello, M. Grosso, M. Rebaudengo, M. Sonza Reorda
    DCIS05: XX Conference on Design of Circuits and Integrated Systems, Lisboa, Portugal
  69. A new DFM-proactive technique
    D. Appello, P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda, V. Tancorre
    SDD'05: 2nd IEEE International Workshop on Silicon Debug and Diagnosis
  70. Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores
    P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda
    MTV'05: 6th International Workshop on Microprocessor Test and Verification, Austin (TX), USA, Nov. 3-4, 2005, pp. 55-60
  71. Diagnosing faulty functional units in processors by using automatically generated test sets
    P. Bernardi, E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero
    MTV'05: 6th International Workshop on Microprocessor Test and Verification, Austin (TX), USA, Nov. 3-4, 2005, pp. 37-41
  72. On the Transformation of Manufacturing Test Sets into On-Line Test Sets for Microprocessors
    E. Sanchez, M. Sonza Reorda, G. Squillero
    DFT'05: The 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 494-502
  73. An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors
    P. Bernardi, L. Bolzani, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DFT2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 307-312
  74. Automatic Generation of Test Sets for SBST of Microprocessor IP Cores
    E. Sanchez, M. Sonza Reorda, G. Squillero, M. Violante
    SBCCI 2005, 18th IEEE Symposium on Integrated Circuits and Systems Design, pp. 74-79
  75. On-line Detection of Control-Flow Errors in SoCs by means of an Infrastructure IP core
    P. Bernardi, L. Bolzani, M. Rebaudengo, M. Sonza Reorda, F. Vargas, M. Violante
    IEEE Dependable Systems and Networks Symposium, july 2005, pp. 50 -58
  76. New Evolutionary Techniques for Test-Program Generation for Complex Microprocessor Cores
    E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero, L. Sterpone, M. Violante
    GECCO05: Genetic and Evolutionary Computation Conference, Washington, DC, USA, June 25-29 2005, pp. 2193-2194
  77. System-level Test and Validation of Hardware/Software Systems
    M. Sonza Reorda, Z. Peng, M. Violante
    Series: Springer Series in Advanced Microelectronics, Vol. 17, Springer, London (UK), ISBN 1-85233-899-7
  78. Exploiting an Infrastructure IP to Reduce Memory Diagnosis Costs in SoCs
    P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda
    ETS 2005: IEEE European Test Symposium, 2005, pp. 202-207
  79. A Tool for Supporting and Automating the Test of Complex System-on-Chips
    P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda, D. Appello, R.Mattiuzzo, V.Tancorre
    ITSW 2005: IEEE International Test Synthesis Workshop, 2005, "Best Student Paper Award"
  80. RoRA: Reliability-oriented Place and Route for SRAM-based FPGAs
    L. Sterpone, M. Sonza Reorda, M. Violante
    PRIME05: IEEE Ph.D. Research In Micro-Electronics & Electronics, 2005, pp. 147-150
  81. On the Diagnosis of SoCs including multiple Memory Cores
    P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda
    DDECS 2005: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, 2005, pp. 75-80
  82. Integrating BIST techniques for on-line SoC testing
    A. Manzone, P. Bernardi, M. Grosso, M. Rebaudengo, E. Sanchez, M. Sonza Reorda
    IOLTS 2005: IEEE International On-line Testing Symposium, 2005, pp. 235-240
  83. Efficient Estimation of SEU effects in SRAM-based FPGAs
    M. Sonza Reorda, L. Sterpone, M. Violante
    IOLTS 2005: IEEE International On-line Testing Symposium, 2005, pp. 54-59
  84. Automatic Completion and Refinement of Verification Sets for Microprocessor Cores
    E. Sanchez, G. Squillero, M. Sonza Reorda
    Lecture Notes in Computer Science, Vol 3449, "Applications on Evolutionary Computing: EvoWorkkshops 2005", Lausanne (CH), March 2005, pp. 205-214
  85. Automatic Test Program Generation for Verifyng Microprocessors
    F. Corno, E. Sanchez, M. Sonza Reorda, G. Squillero
    IEEE Potentials, Vol 24, Issue 1, Feb-Mar 2005, pp. 34-37
  86. Multiple errors produced by single upsets in FPGA configuration memory: a possible solution
    M. Sonza Reorda, L. Sterpone, M. Violante
    ETS2005: IEEE European Test Symposium, 2005, pp. 136-141
    BEST PAPER AWARD at IEEE ETS 2005
  87. On the Optimal Design of Triple Modular Redundancy Logic for SRAM-Based FPGAs
    F. Kastensmidt, L. Sterpone, M. Sonza Reorda, L. Carro
    DATE2005: IEEE Design, Automation and Test in Europe, 2005, pp. 1290-1295
  88. Improved Software-Based Processor Control-Flow Errors Detection Technique
    O. Goloubeva, M. Rebaudengo, M. Sonza Reorda, M. Violante
    RAMS2005: The Annual Reliability and Maintainability Symposium, 2005, Session 14B
  89. Testing logic cores using a BIST P1500 compliant approach: a case of study
    P. Bernardi, G. Masera, F. Quaglio, M. Sonza Reorda
    DATE2005: Design, Automation and Test in Europe, Designer Track, 2005, pp. 228 - 233
  90. Simulation-Based Analysis of SEU Effects in SRAM-Based FPGAs
    M. Violante, L. Sterpone, M. Ceschia, D. Bortolato, P. Bernardi, M. Sonza Reorda, A. Paccagnella
    IEEE Transactions on Nuclear Science, Vol. 51, No. 6, December 2004, pp. 3354-3359
  91. Validation of the dependability of CAN-based networked systems
    F. Corno, J. Perez, M. Ramasso, M. Sonza Reorda, M. Violante
    IEEE High-level Design Validation and Test Workshop, pp. 161-164, 2004
  92. A multi-level approach to the dependability analysis of CAN networks for automotive applications
    F. Corno, J. Perez, M. Ramasso, M. Sonza Reorda, M. Violante
    International Conference Integrated Chassis Control(ICC), 10-12, Nov. 2004
  93. Evolutionary Simulation-Based Validation
    F. Corno, M. Sonza Reorda, G. Squillero
    International Journal on Artificial Intelligence Tools (IJAIT), Vol. 14, 1-2, Dec. 2004, pp. 897 916
  94. Software Techniques for Dependable Computer-based Systems
    O. Goloubeva, M. Rebaudengo, M. Sonza Reorda, M. Violante
    chapter in "Space radiation environment and its effects on spacecraft components and systems", C padu s d., Toulouse (France), ISBN 2-85428-654-5, 2004, pp. 461-480
  95. Evaluating the effects of transient faults on vehicle dynamic performance in automotive systems
    F. Corno, F. Esposito, M. Sonza Reorda, S.Tosato
    ITC2004: IEEE International Test Conference, Charlotte (NC), USA, October 24-30, 2004, pp. 1332-1339
  96. On-line Analysis and Perturbation of CAN Networks
    M. Sonza Reorda, M. Violante
    IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004, pp. 424-432
  97. A new approach to software-implemented fault tolerance
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    JETTA: The Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers, N. 20, August 2004, pp. 433-437
  98. Automatic Verification of RT-Level Microprocessor Cores Using Behavioral Specifications: a Case Study
    L. Anghel, E. Sanchez, M. Sonza Reorda, G. Squillero, R. Velazco
    XIX Conference on Design of Circuits and Integrated Systems, Bordeaux, France, November 24-26, 2004
  99. Coupling Different Methodologies to Validate Obsolete Microprocessors
    L. Anghel, E. Sanchez, M. Sonza Reorda, G. Squillero, R. Velazco
    DFT'04: The 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
  100. Exploiting an I-IP for In-field SOC test
    P. Bernardi, M. Rebaudengo, M. Sonza Reorda
    DFT'04: The 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 404-412
  101. Automatic Test Programs Generation Driven by Internal Performance Counters
    W. Lindsay , E. Sanchez, M. Sonza Reorda, G. Squillero
    MTV'04: 5th International Workshop on Microprocessor Test and Verification, pp. 8-13
  102. Using Infrastructure IPs to support SW-based Self-Test of Processor Cores
    P. Bernardi, M. Rebaudengo, M. Sonza Reorda
    MTV'04: 5th International Workshop on Microprocessor Test and Verification, 2004, pp. 22-27
  103. A multi-level approach to the dependability analysis of networked systems based on the CAN protocol
    F. Corno, J. Perez, M. Sonza Reorda, M. Violante
    SBCCI04: IEEE Symposium on Integrated Circuits and Systems Design, 2004, pp. 71-75
  104. Hybrid Soft Error Detection by means of Infrastructure IP cores
    L. Bolzani, M. Rebaudengo, M. Sonza Reorda, F. Vargas, M. Violante
    IOLTS2004: IEEE International On-Line Testing Symposium, 2004, pp. 79-84
  105. On the evaluation of SEU sensitiveness in SRAM-based FPGAs
    P. Bernardi, M. Sonza Reorda, L. Sterpone, M. Violante
    IOLTS2004: IEEE International On-Line Testing Symposium, 2004, pp. 115-120
  106. Code Generation for Functional Validation of Pipelined Microprocessors
    F. Corno, E. Sanchez, M. Sonza Reorda, G. Squillero
    Journal of Electronic Testing: Theory and Applications, Vol 20(3), June 2004, pp. 269-278
  107. Approaching production diagnostic for BIST-based testing
    D. Appello, P. Bernardi, D. Chindamo, M. Rebaudengo, M. Sonza Reorda, V. Tancorre
    SDD'04: 1st IEEE International Workshop on Silicon Debug and Diagnosis
  108. An Infrastructure IP for Soft Error Detection
    L. Bolzani, M. Rebaudengo, M. Sonza Reorda, F. Vargas, M. Violante
    LATW'04: IEEE Latin-American Test WorkShop
  109. On the diagnosis of embedded memory cores through Programmable BIST
    D. Appello, P. Bernardi, M. Rebaudengo, M. Sonza Reorda, V. Tancorre
    TRP'04: 5th IEEE International Workshop on Test Resource Partitioning
  110. Automatic Test Program Generation - a Case Study
    F. Corno, E. Sanchez, M. Sonza Reorda, G. Squillero
    IEEE Design & Test, Special issue on Functional Verification and Testbench Generation, Volume: 21, Issue 2, March-April 2004, pp. 102-109
  111. A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques
    D. Appello, A. Fudoli, V. Tancorre, P. Bernardi, F. Corno, M. Rebaudengo, M. Sonza Reorda
    Journal of Electronic Testing: Theory and Applications, Volume 20, Issue 1, Kluwer Academic Publishers, Feb 2004, pp. 79-87
  112. Efficient analysis of single event transients
    M. Sonza Reorda, M. Violante
    Journal of Systems Architecture, Elsevier Science, Amsterdam, Netherland, Vol. 50, No. 5, 2004, pp. 239-246
  113. Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA
    M. Bellato, P. Bernardi, D. Bortolato, A. Candelori, M. Ceschia, A. Paccagnella,, M. Rebaudengo, M. Sonza Reorda, M. Violante, P. Zambolin
    DATE2004: Design, Automation and Test in Europe, 2004, pp. 188-193
  114. Automatic Generation of Validation Stimuli for Application-Specific Processors
    O. Goloubeva, M. Sonza Reorda, M. Violante
    DATE2004: Design, Automation and Test in Europe, 2004, pp. 188-193
  115. Impact of data cache memory on the single event upset-induced error rate of microprocessors
    F. Faure, R. Velazco, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 50, No. 6, December 2003, pp. 2101-2106
  116. Identification and classification of single-event upsets in the configuration memory of sram-based fpgas
    M. Ceschia, M. Violante, M. Sonza Reorda, A. Paccagnella, P. Bernardi, M. Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, A. Candelori
    IEEE Transactions on Nuclear Science, Vol. 50, No. 6, December 2003, pp. 2088-2094
  117. Accurate Analysis of Single Event Upsets in a Pipelined Microprocessor
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    Journal of Electronic Testing: Theory and Applications, Vol. 19, No. 5, October 2003, pp. 577-584
  118. Accurate Dependability Analysis of CAN-based Networked Systems
    J. Perez, M. Sonza Reorda, M. Violante
    SBCCI2003: 16th IEEE Symposium on Integrated Circuits and Systems Design, 2003, pp. 337-342
  119. High-level test generation for hardware testing and software validation
    O. Goloubeva, M. Sonza Reorda, M. Violante
    HLDVT2003: IEEE International Workshop on High Level Design Validation and Test, 2003, pp- 143-148
  120. Emulation-based Analysis of Soft Errors in Deep Sub-micron Circuits
    M. Sonza Reorda, M. Violante
    FPL2003: International Conference on Field Programmable Logic and Application, 2003, pp. 616-626
  121. Detailed comparison of dependability analyses performed at RT and gate levels
    A. Ammari, R. Leveugle, M. Sonza Reorda, M. Violante
    DFT2003: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2003, pp. 336-343
  122. Soft-error Detection Using Control Flow Assertions
    O. Goloubeva, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DFT2003: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2003, pp. 581-588
  123. Dependability Analysis of CAN Networks: an emulation-based approach
    J. Perez, M. Sonza Reorda, M. Violante
    DFT2003: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2003, pp 537-544
  124. A programmable BIST approach for the diagnosis of embedded memory cores
    D. Appello, P. Bernardi, A. Fudoli, M. Rebaudengo, M. Sonza Reorda, V. Tancorre, M. Violante
    ETW03: 8th IEEE European Test Workshop (Formal Proceedings), The Netherlands, May 25-28, 2003, pp. 101-102
  125. Code Generation for Functional Validation of Pipelined Microprocessors
    F. Corno, G. Squillero, M. Sonza Reorda
    ETW03: 8th IEEE European Test Workshop (Formal Proceedings), The Netherlands, May 25 28, 2003, pp. 113-118
  126. An efficient algorithm for the extraction of compressed diagnostic information from embedded memory cores
    P. Bernardi, M. Rebaudengo, M. Sonza Reorda
    ETFA 2003: 9th IEEE International Conference on Emerging Technologies and Factory Automation, Lisbon, Portugal, 16-19 September 2003
  127. New Techniques for efficiently assessing reliability of SOCs
    P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    Microelectronics Journal, Vol. 34, No. 1, January 2003, pp. 53-61, Elsevier Science, Amsterdam, Netherland.
  128. Exploiting programmable BIST for the diagnosis of embedded memory cores
    D. Appello, P. Bernardi, A. Fudoli, M. Rebaudengo, M. Sonza Reorda, V. Tancorre, M. Violante
    ITC2003: IEEE International Test Conference, 2003, pp. 379-385
  129. Introducing SW-Based Fault Handling Mechanisms to cope with EMI in Embedded Electronics: are they a good remedy?
    F. Vargas, D. Brum, D. Prestes, L. Bolzani, E. Rhod, M. Sonza Reorda
    IOLTS2003: IEEE International On-Line Testing Symposium, 2003, pp. 101-105
  130. Accurate and Efficient Analysis of Single Event Transients in VLSI Circuits
    M. Violante, M. Sonza Reorda
    IOLTS2003: IEEE International On-Line Testing Symposium, 2003, pp. 101-105
  131. Analyzing SEU Effects in SRAM-based FPGAs
    M. Violante, M. Ceschia, M. Sonza Reorda, A. Paccagnella, P. Bernardi, M. Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, and A. Candelori
    IOLTS2003: IEEE International On-Line Testing Symposium, 2003, pp. 119-123
  132. New Acceleration Techniques for Simulation-Based Fault-Injection
    F. Corno, L. Entrena, C. Lopez, M. Sonza Reorda, G. Squillero
    [chapter in] Fault Injection Techniques and Tools for Embedded Systems Reliability Evaluation, edited by, A. Benso, P. Prinetto, ISBN 1 4020 7589 8, October 2003, pp. 217-230
  133. Automatic Test Program Generation for Pipelined Processors
    F. Corno, M. Sonza Reorda, G. Squillero
    SAC2003: The Eighteenth Annual ACM Symposium on Applied Computing, Melbourne, Florida (USA), March 9-12, 2003, pp. 736-740
  134. Fully Automatic Test Program Generation for Microprocessor Cores
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    DATE2003: Design, Automation and Test in Europe, Munich, Germany, March 3-7, 2003, pp. 1006-1011
  135. A P1500 compatible microprocessor-based approach for the test of Embedded Flash Memories
    P. Bernardi, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DATE2003: Design, Automation and Test in Europe, 2003, pp. 720-725
  136. An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    DATE2003: Design, Automation and Test in Europe, 2003, pp. 602-607
  137. A new Software-based technique for low-cost Fault-Tolerant application
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    RAMS2003: The Annual Reliability and Maintainability Symposium, 2003, pp. 25-28
  138. A New Evolutionary Paradigm for Cultivating Cellular Automata for Built-In Self Test of Sequential Circuits
    F. Corno, M. Sonza Reorda, G. Squillero
    [chapter in] Evolutionary Algorithms for Embedded System Design , edited by R. Drechsler and N. Drechsler, Kluwer Academic Publishers, October 2002, ISBN 1-4020-7276-7, pp.? 143-173
  139. A New Methodology for Debugging Embedded Cores
    D. Appello, L. Bouzaida, A. Fudoli, R. Mattiuzzo, R. Kapur, M. Rebaudengo, M. Sonza Reorda
    TRP2002: Test Resource Partitioning Workshop 2002, Baltimore, MD (USA), October, 10-11, 2002
  140. Coping With SEUs/SETs in Microprocessors by means of Low-Cost Solutions: A Comparative Study
    M. Rebaudengo, M. Sonza Reorda, M. Violante, B. Nicolescu, R. Velazco
    IEEE Transactions on Nuclear Science, Vol. 49, No. 3, June 2002, pp. 1491-1495
  141. An FPGA-based approach for speeding-up Fault Injection campaigns on safety-critical circuits
    P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    Journal of Electronic Testing:Theory and Applications, Vol. 18, No. 3, June 2002, pp. 261-271
  142. A Software Fault Tolerance Method for Safety-Critical Systems: Effectiveness and Drawbacks
    B. Nicolescu, R. Velazco, M. Sonza Reorda, M. Rebaudengo, M. Violante
    SBCCI: 15th IEEE Symposium on Integrated Circuits and Systems Design, Porto Alegre (Brasil), Septempber 2002, pp. 101-106
  143. Reducing Test Application Time through Interleaved Scan
    F. Corno, M. Sonza Reorda, G. Squillero
    SBCCI2002: 15th IEEE Symposium on Integrated Circuits and Systems Design, Porto Alegre (Brasil), Septempber 2002, pp. 89-94
    Outstanding Paper Award
  144. A Hierarchical Approach for Designing Dependable Systems
    M. Sonza Reorda, M. Violante, N. Mazzocca, S. Venticinque, A. Bobbio, G. Franceschinis
    HLDVT2002: IEEE International Workshop on High Level Design Validation and Test, 2002, pp. 63-67
  145. High-Level and Hierarchical Test Sequence Generation
    G. Jervan, Z. Peng, O. Goloubeva, M. Sonza Reorda, M. Violante
    HLDVT2002: IEEE International Workshop on High Level Design Validation and Test, 2002, pp. 169-174
  146. Fault List Compaction through Static Timing Analysis for Efficient Fault Injection Experiments
    M. Sonza Reorda, M. Violante
    DFT2002: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 263-271
  147. A new functional fault model for FPGA Application-Oriented testing
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    DFT2002: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 372-380
  148. Simulation-based analysis of SEU effects on SRAM-based FPGAs
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    FPL2002: International Conference on Field Programmable Logic and Application, 2002, pp. 607-615
  149. Initializability Analysis of Synchronous Sequential Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, G. Squillero
    ACM Transactions on Design Automation of Electronic Systems, April 2002, pp. 249-264
  150. Evolutionary Test Program Induction for Microprocessor Design Verification
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    ATS2002: IEEE Asian Test Symposium, Guam (USA), November 2002, pp. 368-373
  151. Analysis of the Equivalences and Dominances of Transient Faults at the Register-Transfer Level
    L. Berrojo, F. Corno, L. Entrena, I. Gonz lez, C. Lopez, M. Sonza Reorda, G. Squillero
    IOLTW2002: IEEE International On-line Testing Workshop, 2002, pp. 193
  152. A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques
    D. Appello, A. Fudoli, V. Tancorre, F. Corno, M. Rebaudengo, M. Sonza Reorda
    IOLTW2002: IEEE International On-line Testing Workshop, 2002, pp. 112-116
  153. Analysis of SEU effects in a pipelined processor
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    IOLTW2002: IEEE International On-line Testing Workshop, 2002, pp. 206-210
  154. Behavioral-level fault models comparison: an experimental approach
    O. Goloubeva, M. Sonza Reorda, M. Violante
    ICAM2002, Computer-aided Technologies in Applied Mathematics, September 2002, Tomsk, Russia
  155. Experimental analysis of fault models for behavioral-level test generation
    O. Goloubeva, M. Sonza Reorda, M. Violante
    DDECS2002: IEEE Design & Diagnostic of Electronic Circuits & Systems, 2002, pp. 416-419
  156. A new approach to software-implemented fault tolerance
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    LATW2002: IEEE Latin American Test Workshop, 2002
  157. Behavioral-level test vector generation: fault model selection and preliminary test generation results
    O. Goloubeva, M. Sonza Reorda, M. Violante
    Design of Circuits and Integrated Systems, 2002
  158. Efficient Machine-Code Test-Program Induction
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    CEC2002: Congress on Evolutionary Computation, Honolulu, Hawaii (USA), pp. 1486-1491
  159. An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation
    L. Berrojo, F. Corno, L. Entrena, I. Gonz lez, C. Lopez, M. Sonza Reorda, G. Squillero
    VTS2002: 20th IEEE VLSI Test Symposium, Monterey, CA (USA), 28 April - 2 May, 2002, pp. 229-236
  160. Evolutionary Techniques for Minimizing Test Signals Application Time
    F. Corno, M. Sonza Reorda, G. Squillero
    EvoIASP2002: 4rd European Workshop on Evolutionary Computation applications to Image Analysis and Signal Processing, Kinsale (Ireland), April 2002, pp. 183-189
  161. Automatic Test Program Generation from RT-level Microprocessor Descriptions
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    ISQED2002: 3rd International Symposium on Quality Electronic Design, March 18-21, 2002, San Jose, California (USA), pp. 120-125
  162. An Evolutionary Algorithm for Reducing Integrated-Circuit Test Application Time
    F. Corno, M. Sonza Reorda, G. Squillero
    SAC2002: 17th ACM Symposium on Applied Computing, March 2002, Madrid (Spain), pp. 608-611
  163. New Techniques for Speeding-up Fault-injection Campaigns
    L. Berrojo, I. Gonz lez, F. Corno, M. Sonza Reorda, G. Squillero, L. Entrena, C. Lopez
    DATE2002: Design, Automation and Test in Europe, Conference and Exhibition, Paris, France, March 4-8, 2002, pp. 847-852
  164. Devising an RT-Level ATPG for uProcessor Cores
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    WRTLT2001: 2nd Worshop on RTL, ATPG & DFT, Nara, Japan, November 22-23, 2001
  165. A P1500 compliant BIST-based approach to embedded RAM Diagnosis
    D. Appello, F. Corno, M. Giovinetto, M. Rebaudengo, M. Sonza Reorda
    ATS, IEEE Asian Test Symposium, 2001
  166. Effective Techniques for High-Level ATPG
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    ATS2001: IEEE Asian Test Symposium, 2001, pp. 225-230
    Best Paper Award
  167. FPGA-based Fault Injection for Microprocessor Systems
    P. L. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    ATS, IEEE Asian Test Symposium, 2001, pp. 304-309
  168. Exploiting Circuit Emulation for Fast Hardness Evaluation
    P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 48, No. 6, December 2001, pp. 2210-2216
  169. A source-to-source compiler for generating dependable software
    M. Rebaudengo, M. Sonza Reorda, M. Torchiano, M. Violante
    SCAM, IEEE International Workshop on Source Code Analysis and Manipulation, 2001, pp. 33-42
  170. Exploiting FPGA-based Techniques for Fault Injection Campaigns on VLSI Circuits
    P. L. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DFT, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2001, pp. 250-258
  171. An Interpretation Framework for Evaluating High-Level Fault Models and ATPG Capabilities
    F. Corno, M. Sonza Reorda, G. Squillero
    DCIS2001: Design of Circuits and Integrated Systems, 2001, pp. 273-278
  172. Exploring Test Solutions by means of System-level Design Tools
    M. Lajolo, M. Sonza Reorda, M. Violante
    DCIS, Design of Circuits and Integrated Systems, 2001
  173. FPGA-based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits
    P. L. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    FPL 2001, 11th International Conference on Field Programmable Logic and Applications, Belfast (UK), August, 2001, pp. 493-502
  174. ARPIA: a High-Level Evolutionary Test Signal Generator
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    EvoIASP2001: 3rd European Workshop on Evolutionary Computation applications to Image Analysis and Signal Processing, Como (Italy), April 20, 2001, pp. 298-306
  175. Effectiveness and limitations of various software techniques for "soft error" detection: A comparative study
    B. Nicolescu, R. Velazco, M. Sonza Reorda
    IOLTW, IEEE On-Line Testing Workshop, Taormina (Italy), July 9-11, 2001
  176. Exploiting FPGA for accelerating Fault Injection Experiments
    P. L. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IOLTW, IEEE On-Line Testing Workshop, Taormina (Italy), July 9-11, 2001, pp. 9-13
  177. System Safety through Automatic High-level Code Transformations: an Experimental Evaluation
    M. Rebaudengo, M. Sonza Reorda, M. Violante, P. Cheynet, B. Nicolescu, R. Velazco
    DATE: IEEE Design, Automation & Test in Europe Conference, Munich (Germany), 13-16 March 2001, pp. 297-301
  178. On the Test of Microprocessor IP Cores
    F. Corno, M. Sonza Reorda, G. Squillero, M. Violante
    DATE2001: IEEE Design, Automation & Test in Europe Conference, Munich (Germany), 13-16 March 2001, pp. 209-213
  179. Evolving Effective CA/CSTP BIST Architectures for Sequential Circuits
    F. Corno, M. Sonza Reorda, G. Squillero
    SAC2001: 16th ACM Symposium on Applied Computing, March 2001, Las Vegas (USA), pp. 345-350
  180. Early evaluation of bus interconnects dependability for System-on-Chip Designs
    M. Lajolo, M. Sonza Reorda, M. Violante
    14th IEEE International Conference on VLSI Design, Bangalore (India), January 2001, pp. 371-376
  181. Experimentally evaluating an automatic approach for generating safety-critical software with respect to transient errors
    P. Cheynet, B. Nicolescu, R. Velazco, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 47, No. 6, December 2000, pp. 2231-2236
  182. Dependability Evaluation through Effective Fault Injection Techniques on VHDL Descriptions
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    ISATA 2000: Automotive and Transportation Technology, Dublin (Ireland), September 2000, pp. 171-179
  183. GA-Based Verification of Network Protocols Performance
    M. Baldi, F. Corno, M. Rebaudengo, M. Sonza Reorda, G. Squillero
    [chapter in] Telecommunications Optimizations: Heuristic and Adaptive Techniques, edited by D. Corne and M. Oates, Wiley and Sons, August 2000, ISBN 0-471-98855-3, pp. 185-198
  184. A Genetic Algorithm-based System for Generating Test Programs for Microprocessor IP Cores
    F. Corno, M. Sonza Reorda, G. Squillero, M. Violante
    ICTAI2000: The Twelfth IEEE International Conference on Tools with Artificial Intelligence, Vancouver, British Columbia, Canada, November 13-15, 2000, pp. 195-198
  185. Early power estimation for System-on-Chip designs
    M. Lajolo, L. Lavagno, M. Sonza Reorda, M. Violante
    PATMOS 2000: International Workshop - Power and Timing Modeling Optimization and Simulation, G? ttingen (Germany), September 2000, pp. 108-117
  186. Behavioral-level Test Vector Generation for System-on-Chip Designs
    M. Lajolo, L. Lavagno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IEEE International High Level Design Validation Workshop, The Claremont Resort & Spa, Berkeley, California, November 8-10 2000, pp. 21-26
  187. An RT-level Fault Model with High Gate Level Correlation
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    HLDVT2000: IEEE International High Level Design Validation Workshop, The Claremont Resort & Spa, Berkeley, California, November 8-10 2000
  188. RT-level Fault Simulation Techniques based on Simulation Command Scripts
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    DCIS2000: XV Conference on Design of Circuits and Integrated Systems, Le Corum, Montpellier, November 21-24, 2000, pp. 825-830
  189. Speeding-up Fault Injection Campaigns in VHDL models
    B. Parrotta, M. Rebaudengo, M. Sonza Reorda, M. Violante
    19th International Conference on Computer Safety, Reliability and Security, Safecomp 2000, Rotterdam, The Nederlands, October 2000, pp. 27-36
  190. An experimental evaluation of the effectiveness of automatic rule-based transformations for safety-critical applications
    M. Rebaudengo, M. Sonza Reorda, M. Torchiano, M. Violante
    DFT'00, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, October 2000, pp. 257-265
  191. RT-Level ITC 99 Benchmarks and First ATPG Results
    F. Corno, M. Sonza Reorda, G. Squillero
    IEEE Design & Test of Computers, July-August 2000, pp. 44-53
  192. Exploiting the Selfish Gene Algorithm for Evolving Cellular Automata
    F. Corno, M. Sonza Reorda, G. Squillero
    IJCNN2000: IEEE-INNS-ENNS International Joint Conference Neural Networks, Como (I), July 2000, pp. 577-581
  193. Exploiting the Selfish Gene Algorithm for Evolving Hardware Cellular Automata
    F. Corno, M. Sonza Reorda, G. Squillero
    CEC2000: Congress on Evolutionary Computation, San Diego (USA), July 2000, pp. 1401-1406
  194. Evaluating the effectiveness of a Software Fault-Tolerance technique on RISC- and CISC-based architectures
    M. Rebaudengo, M. Sonza Reorda, M. Violante, P. Cheynet, B. Nicolescu, R. Velazco
    IOLTW2000: International On-Line Test Workshop, Mallorca (Spain), July 2000, pp. 17-20
  195. New Techniques for Accelerating Fault Injection in VHDL descriptions
    B. Parrotta, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IOLTW2000: International On-Line Test Workshop, Mallorca (Spain), July 2000, pp. 61-66
  196. Automatic Test Bench Generation for Simulation-based Validation
    M. Lajolo, L. Lavagno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    CODES2000: IEEE International Workshop on Hardware/Software Codesign, San Diego (USA), May 2000, pp. 136-140
  197. An Improved Cellular Automata-Based BIST Architecture for Sequential Circuits
    F. Corno, M. Sonza Reorda, G. Squillero
    ISCAS2000: IEEE International Symposium on Circuits and Systems, Geneve (CH), May 2000, pp. 76-79
  198. CA-CSTP: A new BIST Architecture for Sequential Circuits
    F. Corno, M. Sonza Reorda, G. Squillero, M. Violante
    ETW2000: European Test Workshop, May 2000, pp. 167-172
  199. System-level Test Bench Generation in a Co-design Framework
    M. Lajolo, L. Lavagno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    ETW2000: European Test Workshop, May 2000, pp. 25-30
  200. Low Power BIST via Hybrid Cellular Automata
    F. Corno, M. Rebaudengo, M. Sonza Reorda, G. Squillero, M. Violante
    VTS2000: 18th IEEE VLSI Test Symposium, Montreal, Canada, May 2000, pp. 29-34
  201. High-Level Observability for Effective High-Level ATPG
    F. Corno, M. Sonza Reorda, G. Squillero
    VTS2000: 18th IEEE VLSI Test Symposium, Montreal, Canada, May 2000, pp. 411-416
  202. Evolving Cellular Automata for Self-Testing Hardware
    F. Corno, M. Sonza Reorda, G. Squillero
    ICES2000: Third International Conference on Evolvable Systems: From Biology to Hardware, Edinburgh (UK), April 2000, pp. 31-39
  203. Prediction of Power Requirements for High-Speed Circuits
    F. Corno, M. Rebaudengo, M. Sonza Reorda, G. Squillero, M. Violante
    EvoTel2000: European Workshops on Telecommunications, Edinburgh (UK), May 2000, pp. 247-254
  204. Automatic Validation of Protocol Interfaces Described in VHDL
    F. Corno, M. Sonza Reorda, G. Squillero
    EvoTel2000: European Workshops on Telecommunications, Edinburgh (UK), May 2000, pp. 205-213
  205. Evaluating System Dependability in a Co-Design Framework
    M. Lajolo, L. Lavagno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DATE2000: Design, Automation and Test in Europe, Paris (F), March 2000, pp. 586-590
  206. Automatic Test Bench Generation for Validation of RT-level Descriptions: an Industrial Experience
    F. Corno, A. Manzone, A. Pincetti, M. Sonza Reorda, G. Squillero
    DATE2000: Design, Automation and Test in Europe, Paris (F), March 2000, pp. 385-389
  207. High-level ATPG: a real topic or an academic amusement?
    M. Sonza Reorda
    IEEE International Test Conference, Atlantic City (USA), September 1999, Poster Session, pp. 1118
  208. Optimal Vector Selection for Low Power BIST
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DFT99: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, November 1-3 1999 - Albuquerque, New Mexico (USA), pp. 219-226
  209. Soft-error Detection through Software Fault-Tolerance techniques
    M. Rebaudengo, M. Sonza Reorda, M. Torchiano, M. Violante
    DFT99: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, November 1-3 1999 - Albuquerque, New Mexico (USA), pp. 210-218
  210. High Quality Test Pattern Generation for RT-level VHDL Descriptions
    F. Corno, M. Sonza Reorda, G. Squillero
    MTV99: 2nd International Workshop on Microprocessor Test and Verification Common Challenges and Solutions, Atlantic City (USA), September 1999
  211. FlexFi: a flexible Fault Injection environment for microprocessor-based systems
    A. Benso, M. Rebaudengo, M. Sonza Reorda
    SAFECOMP 1999: 18th International Conference on Computer Safety, Reliability and Security, (Lecture Notes in Computer Science, Springer Verlag, A. Pasquini (Ed.)), pp. 323-335
  212. On Reducing the Peak Power Consumption of Test Sequences
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    European Conference on Circuit Theory and Design, Stresa, Italy, August 1999, pp. 247-250
  213. A Peak-Power Estimation Algorithm for Sequential Circuits
    F. Corno, M. Rebaudengo, M. Sonza Reorda, V. Speranza, M. Violante
    European Conference on Circuit Theory and Design, Stresa, Italy, August 1999, pp. 896-899
  214. Simulation-Based Sequential Equivalence Checking of RTL VHDL
    F. Corno, M. Sonza Reorda, G. Squillero
    ICECS99: 6th IEEE International Conference on Electronics, Circuits and Systems, Paphos, Cyprus, September 1999, pp. 351-354
  215. Verifying the Equivalence of Sequential Circuits with Genetic Algorithms
    F. Corno, M. Sonza Reorda, G. Squillero
    CEC99: 1999 Congress on Evolutionary Computation, Washington DC (USA), July 1999, pp. 1293-1297
  216. Optimizing Deceptive Functions with the SG-Clans Algorithm
    F. Corno, M. Sonza Reorda, G. Squillero
    CEC99: 1999 Congress on Evolutionary Computation, Washington DC (USA), July 1999, pp. 2190-2195
  217. A New BIST Architecture for Low Power Circuits
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    ETW99: IEEE European Test Workshop, Konstanz(D), May 1999
  218. Test Pattern Generation under Low Power Constraints
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    R. Poli, H-M. Voigt, S. Cagnoni, D. Corne, G. Smith, T. Fogarty (eds.), Evolutionary Image Analysis, Signal Processing and Telecommunications First European Workshops, EvoIASP'99 and EuroEcTel'99 Goteborg, Sweden, May 1999 Joint Proceedings, Springer LNCS, 1999, pp. 162-170
  219. Approximate Equivalence Verification for Protocol Interface Implementation via Genetic Algorithms
    F. Corno, M. Sonza Reorda, G. Squillero
    EuroEcTel99: R. Poli, H-M. Voigt, S. Cagnoni, D. Corne, G. Smith, T. Fogarty (eds.), Evolutionary Image Analysis, Signal Processing and Telecommunications First European Workshops, EvoIASP'99 and EuroEcTel'99 Goteborg, Sweden, May 1999 Joint Proceedings, Springer LNCS, 1999, pp. 182-192
    Special Jury Award for Outstanding Work Presented by a Student or Young Researcher
  220. Evaluating the Fault Tolerance Capabilities of Embedded Systems via BDM
    M. Rebaudengo, M. Sonza Reorda
    VTS99: 17th IEEE VLSI Test Symposium, Dana Point (USA), April 1999, pp. 452-457
  221. ALPS: A Peak Power Estimation Tool for Sequential Circuits
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    GLS-VLSI99: 8th Great Lakes Symposium on VLSI, Ypsilanti MI (USA), March 4-6 1999, pp. 350-353
  222. Transformation-based Peak Power Reduction for Test Sequences
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    poster at VOLTA99: IEEE Alessandro Volta Memorial Workshop on Low Power Design, Como (ITALY), March 3-5 1999, pp. 78-83
  223. Approximate Equivalence Verification of Sequential Circuits via Genetic Algorithms
    F. Corno, M. Sonza Reorda, G. Squillero
    DATE99: IEEE Design, Automation & Test in Europe, Munich (Germany), March 1999, pp. 754-755
  224. A Low-Cost Programmable Board for Speeding-Up Fault Injection in Microprocessor-Based Systems
    A. Benso, P. L. Civera, M. Rebaudengo, M. Sonza Reorda
    RAMS99: Annual Reliability and Maintainability Symposium, Washington, DC (USA), January 1999, pp. 171-177
  225. Fault Injection for Embedded Microprocessor-based Systems
    A. Benso, M. Rebaudengo, M. Sonza Reorda
    Journal of Universal Computer Science (Special Issue on Dependability Evaluation and Validation), Vol. 5, No. 5, pp. 693-711
  226. SymFony: a Hybrid Topological-Symbolic ATPG exploiting RT-level Information
    F. Corno, P. Prinetto, M. Sonza Reorda, M. Violante, U. Glaeser, H. T. Vierhaus
    IEEE Transactions on Computer-Aided Design, February 1999, Vol. 18, No. 2, pp. 191-202
  227. A Fault Injection Environment for Microprocessor-based Boards
    A. Benso, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    ITC98: IEEE International Test Conference, Washington (USA), September 1998, pp. 768-773
  228. EXFI: a low cost Fault Injection System for embedded Microprocessor-based Boards
    A. Benso, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    ACM Transactions on Design Automation of Electronic Systems, Vol. 3, Number 4, October 1998, pp. 626-634
  229. An Integrated HW and SW Fault Injection Environment for Real-Time Systems
    A. Benso, M. Rebaudengo, M. Sonza Reorda, P. L. Civera
    DFT98, 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, November 2-4 1998, Austin, Texas, pp. 117-122
  230. A System for Evaluating On-Line Testability at the RT-level
    S. Chiusano, F. Corno, M. Sonza Reorda, R. Vietti
    DFT98, 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, November 2-4 1998, Austin, Texas
  231. Enhancing Topological ATPG with High-Level Information and Symbolic Techniques
    F. Corno, J. H. Patel, E. M. Rudnick, M. Sonza Reorda, R. Vietti
    ICCD98, International Conference on Circuit Design, Austin, Texas (USA), October 1998
  232. VEGA: A Verification Tool Based on Genetic Algorithms
    F. Corno, M. Sonza Reorda, G. Squillero
    ICCD98, International Conference on Circuit Design, Austin, Texas (USA), October 1998, pp. 321-326
  233. Exploiting the Background Debugging Mode in a Fault Injection system
    P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    IPDS: The 3rd Annual IEEE International Computer Performance & Dependability Symposium, Durham (NC), September 7-9 1998, pag. 277
  234. Experiences in the use of evolutionary techniques for testing digital circuits
    F. Corno, M. Sonza Reorda, M. Rebaudengo
    Applications and Science of Neural Networks, Fuzzy Systems, and Evolutionary Computation, SPIE 1998 Annual Meeting
    Invited paper
  235. A Hybrid Fault Injection Methodology for Real Time Systems
    A. Benso, P. L. Civera, M. Rebaudengo, M. Sonza Reorda, A. Ferro
    Digest of FastAbstracts: FTCS-28, The 28th Annual International Symposium on Fault-Tolerant Computing, June 23-25, Munich (Germany), pp. 74-75
  236. Evaluating cost and effectiveness of software redundancy techniques for hardware errors detection
    M. Rebaudengo, M. Sonza Reorda
    Digest of FastAbstracts: FTCS-28, The 28th Annual International Symposium on Fault-Tolerant Computing, June 23-25, Munich (Germany), pp. 88-89
  237. A Test Pattern Generation methodology for low power consumption
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    VTS98: 16th IEEE VLSI Test Symposium, Monterey, CA (USA), April 1998
  238. On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits
    F. Corno, N. Gaudenzi, P. Prinetto, M. Sonza Reorda
    VTS98: 16th IEEE VLSI Test Symposium, Monterey, CA (USA), April 1998
  239. Algoritmi da taglio
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, S. Bisotto
    La Rivista del Vetro, Miller Freeman ed., Milano (Italy), anno 22, n. 2, marzo 1998, pp. 86-98
  240. A New Evolutionary Algorithm Inspired by the Selfish Gene Theory
    F. Corno, M. Sonza Reorda, G. Squillero
    ICEC98: IEEE International Conference on Evolutionary Computation, May 1998, pp. 575-580
  241. Scan Chain Partitioning and Re-ordering based on Layout Information: an Industrial Experience
    S. Barbagallo, G. Borgonovo, D. Grassi, D. Medina, F. Corno, P. Prinetto, M. Sonza Reorda
    DATE98: Design, Automation and Test in Europe (User Forum), Paris (F), February 1998
  242. Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques
    E. M. Rudnick, R. Vietti, A. Ellis, F. Corno, P. Prinetto, M. Sonza Reorda
    DATE98: Design, Automation and Test in Europe, Paris (F), February 1998
  243. Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection
    F. Corno, P. Prinetto, M. Sonza Reorda, M. Violante
    DATE98: Design, Automation and Test in Europe, Paris (F), February 1998
  244. The Selfish Gene Algorithm: a New Evolutionary Optimization Strategy
    F. Corno, M. Sonza Reorda, G. Squillero
    SAC98: 13th Annual ACM Symposium on Applied Computing, Atlanta, Georgia (USA), February 1998, pp. 349-355
  245. The General Product Machine: a New Model for Symbolic FSM Traversal
    G. Cabodi, P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda
    Formal Methods in Systems Design, Kluwer Academic Publishers, N. 12, 1998, pp. 267-289
  246. Integrating Online and Offline Testing of a Switching Memory
    S. Barbagallo, F. Corno, D. Medina, P. Prinetto, M. Sonza Reorda
    IEEE Design & Test of Computers, January-March 1998
  247. Exploiting Symbolic Techniques within Genetic Algorithms for Power Optimization
    S. Chiusano, F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    ICTAI97: 9th IEEE International Conference on Tools with Artificial Intelligence, Newport Beach, CA (USA), November 1997
    CV. Ramamoorthy Best Paper Award
  248. Simulation-Based Verification of Network Protocols Performance
    M. Baldi, F. Corno, M. Rebaudengo, P. Prinetto, M. Sonza Reorda, G. Squillero
    CHARME97: Advanced Research Working Conference on Correct Hardware Design and Verification Methods, Montr? al, Quebec, Canada, October 1997, pp. 236-251
  249. Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments
    A. Benso, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, J. Raik, R. Ubar
    DFT97: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Paris (F), November 1997
  250. A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, G. Squillero
    ATS97: The Sixth IEEE Asian Test Symposium, Akita (JP), November 1997, pp. 56-61
    Also included in the 10th Anniversary Compedium of Papers from Asian Test Symposium
  251. Guaranteeing Testability in Re-encoding for Low Power
    S. Chiusano, F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    ATS97: The Sixth IEEE Asian Test Symposium, Akita (JP), November 1997
  252. Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, M. Violante
    ATS97: The Sixth IEEE Asian Test Symposium, Akita (JP), November 1997
  253. Il Politecnico di Torino su Internet: un'esperienza di gestione di un server web universitario
    F. Corno, L. Farinetti, M. Innocenti, F. Maino, M. Sonza Reorda
    AICA97 (Associazione Italiana Calcolo Automatico), Milano, 1997
  254. Testability analysis and ATPG on behavioral RT-level VHDL
    F. Corno, P. Prinetto, M. Sonza Reorda
    ITC97, IEEE International Test Conference, Washington D. C. (USA), November 1997
  255. Optimizing Area Loss in Flat Glass Cutting
    S. Bisotto, F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    GALESIA97, IEE/IEEE International Conference on Genetic ALgorithms in Engineering Systems: Innovations and Applications, Glasgow (UK), September 1997
  256. A New Approach for Initialization Sequences Computation for Synchronous Sequential Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, G. Squillero
    ICCD97, October 1997, Austin, Texas (USA), pp. 381-386
  257. Boolean Function Manipulation on a Parallel System using BDDs
    R. Ansaloni, F. Bianchi, F. Corno, M. Rebaudengo, M. Sonza Reorda
    HPCN Europe 1997: International Conference and exhibition on High-Performance Computing and Networking, Vienna, Austria, April 1997, in Lecture Notes in Computer Science 1225, Springer, pp. 916-928
  258. Cellular Automata for Sequential Test Pattern Generation
    S. Chiusano, F. Corno, P. Prinetto, M. Sonza Reorda
    VTS97: 15th IEEE VLSI Test Symposium, Monterey, CA (USA), April 1997, pp. 60-65
  259. A new approach to build a low-level Malicious Fault List starting from High-level description and Alternative Graphs
    A. Benso, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, R. Ubar
    ED&TC97: IEEE European Design and Test Conference, Paris (F), March 1997
  260. Hybrid Symbolic-Explicit Techniques for the Graph Coloring Problem
    S. Chiusano, F. Corno, P. Prinetto, M. Sonza Reorda
    ED&TC97: IEEE European Design and Test Conference, Paris (F), March 1997, pp. 422-426
  261. Testable Synthesis through RT-level DfT rules
    S. Barbagallo, F. Corno, D. Medina, P. Prinetto, M. Sonza Reorda, M. Violante
    ED&TC97: IEEE European Design and Test Conference User's Forum, Paris (F), March 1997, pp. 57-61
  262. New Static Compaction Techniques of Test Sequences for Sequential Circuits
    F. Corno, M. Rebaudengo, P. Prinetto, M. Sonza Reorda
    ED&TC97: IEEE European Design and Test Conference, Paris (F), March 1997, pp. 37-43
  263. SAARA: a Simulated Annealing Algorithm for Test Pattern Generation for Digital Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    SAC97: 12th Annual ACM Symposium on Applied Computing, San Jose, CA (USA), February 1997, pp. 228-232
  264. Faulty Behavior Observation on a Microprocessor System through a VHDL Simulation-Based Fault Injection Experiment
    A. Amendola, A. Benso, F. Corno, L. Impagliazzo, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    IEEE EURO-VHDL96, Geneva (Switzerland), September 1996
  265. Fault Tolerant and BIST design of a FIFO cell
    F. Corno, P. Prinetto, M. Sonza Reorda
    IEEE EURO-VHDL96, Geneva (Switzerland), September 1996
  266. Scan Insertion Criteria for Low Design Impact
    S. Barbagallo, M. Lobetti, D. Medina, F. Corno, P. Prinetto, M. Sonza Reorda
    IEEE VLSI Test Symposium, Princeton (USA), April 1996
  267. Exploiting Competing Subpopulations for Automatic Generation of Test Sequences for Digital Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    Fourth International Conference on Parallel Problem Solving from Nature, Berlin (Germany), September 1996
  268. Partial Scan Flip Flop Selection for Simulation-based Sequential ATPGs
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    IEEE International Test Conference, Washington (USA), October 1996
  269. Comparing topological, symbolic and GA-based ATPGs: an experimental approach
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    IEEE International Test Confernce, Washington (USA), October 1996
  270. A Genetic Algorithm for Automatic Generation of Test Logic for Digital Circuits
    F. Corno, P. Prinetto, M. Sonza Reorda
    IEEE International Conference On Tools with Artificial Intelligence, Toulouse (F), November 1996
  271. A Parallel Genetic Algorithm for Automatic Generation of Test Sequences for Digital Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    International Conference on High-Performance Computing and Networking, Brussels (Belgium), April 1996
  272. Advanced Techniques for GA-based sequential ATPGs
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, R. Mosca
    IEEE Design & Test Conference, Paris (F), March 1996
  273. Il ruolo delle tecniche di fault injection nell'analisi dell'affidabilit? dei sistemi
    A. Benso, F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    AEI (Automazione Energia Informazione), Vol. 83, N. 10, Ottobre 1996, pp. 63/807-69/813
  274. On-line Testing of an Off-the-Shelf Microprocessor Board for Safety-critical Applications
    F. Corno, M. Damiani, L. Impagliazzo, P. Prinetto, M. Rebaudengo, G. Sartore, M. Sonza Reorda
    EDCC Conference, Taormina (Italy), October 1996
  275. Testable Synthesis of Control Units via Circular Self-Test Path: Problems and Solutions
    F. Corno, P. Prinetto, M. Sonza Reorda
    IEEE Design & Test of Computers, Winter 1996
  276. GALLO: a Genetic Algorithm for Floorplan Area Optimization
    M. Rebaudengo, M. Sonza Reorda
    IEEE Transactions on Computer-Aided Design, August 1996, Vol. 15, No. 8, pp. 991-1000
  277. GATTO: a Genetic Algorithm for Automatic Test Pattern Generation for Large Synchronous Sequential Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    IEEE Transactions on Computer-Aided Design, August 1996, Vol. 15, No. 8, pp. 943-951
  278. Uso di Tecniche Evolutive per la Risoluzione di problemi di CAD Elettronico
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    Processori Dedicati, a cura di Lanfranco Lopriore, Fabrizio Luccio e Maria Marinaro, Collana CNR/Progetto Finalizzato "Sistemi Informatici e Calcolo Parallelo" diretta da Bruno Fadini, Franco Angeli Editore
  279. Improving Topological ATPG with Symbolic Techniques
    F. Corno, U. Glaeser, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, H. T. Vierhaus
    IEEE VLSI Test Symposium, Princeton (USA), April 1995
  280. A Portable ATPG tool for Parallel and Distributed Systems
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, E. Veiluva
    IEEE VLSI Test Symposium, Princeton (USA), April 1995
  281. Testing a Switching Memory in a Telecommunication System
    S. Barbagallo, F. Corno, P. Prinetto, M. Sonza Reorda
    IEEE International Test Conference, Washington (USA), October 1995
  282. Using Symbolic Techniques to find the Maximum Clique in Very Large Sparse Graphs
    F. Corno, P. Prinetto, M. Sonza Reorda
    ED&TC95: IEEE European Design and Test Conference, Paris, March 1995
  283. GARDA: a Diagnostic ATPG for Large Synchronous Sequential Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    ED&TC95: IEEE European Design and Test Conference, Paris, March 1995
  284. A Data Parallel Algorithm for Boolean Function Manipulation
    S. Gai, M. Rebaudengo, M. Sonza Reorda
    5th IEEE Symposium on the Frontiers of Massively Parallel Computation, McLean (USA), February 1995
  285. A PVM tool for Automatic Test Generation on Parallel and Distributed Systems
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, E. Veiluva
    International Conference on High-Performance Computing and Networking, Milan (Italy), May 1995, Lecture Notes in Computer Science, Ed. Springer
  286. Exploiting Massively Parallel Architectures for the Solution of Diffusion and Propagation Problems
    P. P. Delsanto, S. Biancotto, M. Scalerandi, M. Rebaudengo, M. Sonza Reorda
    International Conference on High-Performance Computing and Networking, Milan (Italy), May 1995, Lecture Notes in Computer Science, Ed. Springer
  287. An Improved Data Parallel Algorithm for Boolean Function Manipulation using BDDs
    S. Gai, M. Rebaudengo, M. Sonza Reorda
    3th IEEE/Euromicro Workshop on Parallel and Distributed Processing, Sanremo (Italy), January 1995
  288. Exploiting Massively Parallel Architectures for the Analysis of Growth Phenomena
    P. P. Delsanto, G. Kaniadakis, M. Scalerandi, M. Rebaudengo, M. Sonza Reorda
    AICA94: Congresso Annuale Associazione Italiana per l'Informatica ed il Calcolo Automatico, Palermo (I), September 1994
  289. Parallel Processing Analysis of the 1-D KPZ growth equation
    P. P. Delsanto, G. Kaniadakis, M. Scalerandi, M. Rebaudengo, M. Sonza Reorda
    6-th EPS-APS International Conference on Physics Computing, Lugano (CH), August 1994
  290. A Genetic Algorithm for Floorplan Area Optimization
    M. Rebaudengo, M. Sonza Reorda
    ICEC94: IEEE Conference on Evolutionary Computation, Orlando, FL (USA), June 1994
  291. GATTO: an Intelligent Tool for Automatic Test Pattern Generation for Digital Circuits
    P. Prinetto, M. Rebaudengo, M. Sonza Reorda, E. Veiluva
    IEEE International Conference on Tools with Artificial Intelligence, New Orleans (USA), November 1994
  292. An Automatic Test Pattern Generator for Large Sequential Circuits based on Genetic Algorithms
    P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    ITC94: IEEE International Test Conference, Washington D. C. (USA), October 1994
  293. Making the Circular Self-Test Path Technique Effective for Real Circuits
    F. Corno, P. Prinetto, M. Sonza Reorda
    ITC94: IEEE International Test Conference, Washington D. C. (USA), October 1994
  294. A Data Parallel Approach to Boolean Function Manipulation using BDDs
    G. Cabodi, S. Gai, M. Rebaudengo, M. Sonza Reorda
    MPCS94: IEEE/EuroMicro International Conference on Massively Parallel Computing Systems, Ischia (I), May 1994
  295. Floorplan Area Optimization using Genetic Algorithms
    M. Rebaudengo, M. Sonza Reorda
    GLS94: 4th IEEE Great Lakes Symposium on VLSI, Notre Dame, IN (USA), March 1994
  296. A Package for Boolean Function Manipulation on a Massively Parallel SIMD Architecture
    G. Cabodi, S. Gai, M. Rebaudengo, M. Sonza Reorda
    EWPDP94: IEEE/EuroMicro Workshop on Parallel and Distributed Processing, Malaga (E), Gennaio 1994
  297. Exploiting a Workstation Network for Automatic Generation of Test Patterns for Digital Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, A. R. Meo, E. Veiluva
    AICA94: Congresso Annuale Associazione Italiana per l'Informatica ed il Calcolo Automatico, Palermo (I), September 1994
  298. An Experimental Analysis of the Effectiveness of the Circular Self-Test Path Technique
    F. Corno, P. Prinetto, M. Sonza Reorda
    EURO-DAC94: IEEE European Design Automation Conference, Grenoble (F), September 1994
  299. Efficient Parallel Hash Table Methods for a Boolean Function Manipulation Package for CM-200
    M. Rebaudengo, M. Sonza Reorda
    Science on the Connection Machine System (Editors: J. M. Alimi, A. Serna, H. Scholl), Proceedings of the Second European CM Users Meeting, Meudon (F), 11-14 Ottobre 1993, pp. 59-68
  300. An Approach to Sequential Circuit Diagnosis based on Formal Verification Techniques
    G. Cabodi, P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda
    JETTA: The Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers, N. 4, January 1993, pp. 11-17
  301. Finding the Maximum Clique in a Graph Using BDDs
    F. Corno, P. Prinetto, M. Sonza Reorda
    ICVC93: IEEE 3rd International Conference on VLSI and CAD, Taejon, Korea, November 1993, pp. 269-272
  302. A BDD Package for a Massively Parallel SIMD Architectures
    G. Cabodi, S. Gai, M. Rebaudengo, M. Sonza Reorda
    ICVC93: IEEE International Conference on VLSI and CAD, Tajeon (South Korea), Novembre 1993, pp. 332-335
  303. Hybrid Genetic Algorithms for the Traveling Salesman Problem
    P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    International Conference on Neural Networks and Genetic Algorithms, Innsbruck (A), Aprile 1993, pp.559-566
  304. An Experimental Analysis of effects of Migration in Paralell Genetic Algorithms
    M. Rebaudengo, M. Sonza Reorda
    EWPDP93: IEEE/Euromicro Workshop on Parallel and Distributed Processing, Gran Canaria (E), Gennaio 1993, pp.232-238
  305. Tecniche di diagnosi per circuiti sequenziali
    G. Cabodi, P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda
    Congresso Annuale AICA'92, Torino (I), October 1992, Volume II, pp. 737-748
  306. Attraversamento simbolico di Macchine a Stati Finiti per verifica, sintesi e collaudo
    G. Cabodi, P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda
    Congresso Annuale AICA'92, Torino (I), October 1992, Volume I, pp. 133-145
  307. Uso di sistemi paralleli nella verifica di circuiti sequenziali
    P. Camurati, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    Congresso Annuale AICA'92, Torino (I), October 1992, Volume I, pp. 115-124
  308. Improved techniques for multiple stuck-at-fault analysis using single stuck-at fault test
    P. Camurati, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    ISCAS 92: IEEE International Symposium on Circuits and Systems, San Diego, CA (USA), Maggio 1992, pp. 383-386
  309. Centralized vs. Distributed Implementation of FSM Equivalence Verification on a Parallel System, in Parallel Computing
    P. Camurati, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    from Theory to Sound Practice, ed. by W. Joosen and E. Milgrom, IOS Press, 1992, pp. 554-557
  310. Efficient Verification of Sequential Circuits on a Parallel Systems
    P. Camurati, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    EDAC92: IEEE European Conference on Design Automation, Brussels (B), Marzo 1992, pp.64-67
  311. Sequential circuit diagnosis based on formal verification techniques
    G. Cabodi, P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda
    ITC92: IEEE International Test Conference, Baltimore, MD (USA), September 1992, pp. 187-196
  312. Cross-fertilizing FSM verification techniques and sequential diagnosis
    G. Cabodi, P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda
    EURO-DAC92: IEEE European Design Automation Conference, Hamburg (Germany), September 1992, pp. 306-311
  313. A new model for improving symbolic Product Machine traversal
    G. Cabodi, P. Camurati, F. Corno, S. Gai, P. Prinetto, M. Sonza Reorda
    DAC92: 29th ACM/IEEE Design Automation Conference, Anaheim, CA (USA), June 1992, pp. 614-619
  314. A simulation-based approach to test pattern generation for synchronous circuits
    P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda
    VTS92: 10th IEEE VLSI Test Symposium, Atlantic City, NJ (USA), April 1992, pp. 263-267