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Papers by M. Violante

  1. Application-oriented SEU cross-section of a processor soft core for Atmel RHBD FPGAs
    N. Battezzati, F. Margaglia, M. Violante, F. Decuzzi, D. Merodio Codinachs, B. Bancelin
    [accepted for publication on] IEEE Transactions on Nuclear Science
  2. Application-oriented SEU cross-section of a processor soft core for Atmel RHBD FPGAs
    N. Battezzati, F. Margaglia, M. Violante, F. Decuzzi, D. Merodio Codinachs, B. Bancelin
    IEEE RADECS 2010: 11th European Conference on Radiation and Its Effects on Component and Systems, 2010 [accepted for publication]
  3. An integrated flow for the design of hardened circuits on SRAM-based FPGAs
    C. Bolchini, A. Miele, C. Sandionigi, N. Battezzati, L. Sterpone, M. Violante
    15th IEEE European Test Symposium (ETS), 2010, pp. 214 - 219
  4. Advanced technologies for transient faults detection and compensation
    M. Sonza Reorda, L. Sterpone, M. Violante
    book chapter on IGI [accepted for publication on]
  5. Layout-aware Multi-Cell Upsets Effects Analysis on TMR circuits implemented on SRAM-based FPGAs
    L. Sterpone, M. Violante, A. Panariti, A. Bocquillon, F. Miller, N. Buard, A. Manuzzato, S. Gerardin, A. Paccagnella
    IEEE Transactions on Nuclear Science [accepted for publication on]
  6. Reconfigurable Field Programmable Gate Arrays for Mission-Critical Applications
    N. Battezzati, L. Sterpone, M. Violante
    Springer, 1st Edition, 240 pages, ISBN: 978-1-4419-7594-2
  7. A New Software Tool for Static Analysis of SET Sensitiveness in Flash-based FPGAs
    N. Battezzati, F. Decuzzi, L. Sterpone, M. Violante
    IEEE International Symposium on Very Large Scale of Integration (VLSI) and System-on-Chip (SoC), pp. 79 - 84, 2010
  8. A new framework for the automatic insertion of mitigation structures in circuits netlists.
    N. Battezzati, D. Serrone, M. Violante
    IEEE International On-Line Testing Symposium (IOLTS), July 5-7, 2010, Corfu Island, Greece [accepted for publication]
  9. Coping with the Obsolescence of Safety- or Mission-Critical Embedded Systems using FPGAs
    H. Guzman-Miranda, L. Sterpone, M. Violante, M. A. Aguirre, M. Gutierrez-Rizo M.
    IEEE Transactions on Industrial Electronics, Vol. 58, Issue 3, pp. 814 - 821, 2011
  10. Methodologies to study frequency-dependent Single Event Effects sensitivity in Flash-based FPGAs
    N. Battezzati, S. Gerardin, A. Manuzzato, D. Merodio, A. Paccagnella, C. Poivey, L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, December, 2009, Vol. 56, pp. 3534 - 3541
  11. Soft Errors in Flash-based FPGAs: Analysis Methodologies and First Results
    N. Battezzati, F. Decuzzi, L. Sterpone, M. Violante
    19th IEEE International Conference on Field Programmable Logic and Applications, August 31 - September 2, 2009, pp. 723 - 724
  12. Application-oriented SEU sensitiveness analysis of Atmel rad-hard FPGAs
    N. Battezzati, F. Decuzzi, M. Violante, M. Briet
    15th IEEE International On-Line Testing Symposium, 24 - 26 June, 2009, pp. 89 - 94
  13. New techniques for improving the performance of the lockstep architecture for SEEs mitigation in FPGA embedded processors
    F. Abate, C. A. Lisboa, L. Carro, L. Sterpone, M. Violante
    IEEE Transaction on Nuclear Science, Volume 56, Issue 4, Part 2, August 2009, pp. 1992 - 2000
  14. A study of the Single Event Effects Impact on Functional Mapping within Flash-based FPGAs
    F. Abate, F. Lima Kastensmidt, L. Sterpone, M. Violante
    IEEE Design, Automation and Test in Europe, Munich, Germany , 20 - 24 April 2009, pp. 1226 - 1229
  15. On the Static Cross Section of SRAM-based FPGAs
    A. Manuzzato, S. Gerardin, A. Paccagnella, L. Sterpone, M. Violante
    IEEE Radiation Effects Data Workshop, July 2008, pp. 94 - 97
  16. Experimental Validation of Lockstep, Checkpoint, and Rollback Recovery to Detect and Correct Soft Errors in System-On-Programmable-Chips
    F. Abate, L. Sterpone, M. Violante
    IEEE Radiation Effects on Components and Systems.
  17. Coping with Obsolescence of Processor Cores in Critical Applications.
    F. Abate, M. Violante
    IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems
  18. Monte Carlo Analysis of the Effects of Soft Error Accumulation in SRAM-based FPGAs
    N. Battezzati, L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, Volume 55, Issue 6, Part 1, December 2008, pp. 3381 - 3387
  19. On the evaluation of radiation-induced transient faults in Flash-based FPGAs
    N. Battezzati, S. Gerardin, A. Manuzzato, A. Paccagnella, S. Rezgui, L. Sterpone, M. Violante
    14th IEEE International On-Line Testing Symposium , 22 - 25 June, 2008, pp. 157 - 163
  20. Soft Errors in SRAM-FPGAs: a Comparison of Two Complementary Approaches
    M. Alderighi, F. Casini, S. DAngelo, M. Mancini, S. Pastore, L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 55, Issue 4, Part 1, August 2008, pp. 2267 - 2273
  21. A new Algorithm for the Analysis of the MCUs Sensitiveness of TMR Architectures in SRAM-based FPGAs
    L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 55, Issue 4, Part 1, August 2008, pp. 2019 - 2027
  22. A new Placement Algorithm for the Optimization of Fault Tolerant Circuits on Reconfigurable Devices
    N. Battezzati, L. Sterpone, M. Violante
    CF2008: ACM International Conference on Computing Frontiers, Ischia, Italy, 5 - 7 May 2008, pp. 347 - 352
  23. A new low-cost non intrusive platform for injecting soft errors in SRAM-based FPGAs
    N. Battezzati, L. Sterpone, M. Violante
    ISIE2008: IEEE International Symposium on Industrial Electronics, Cambridge, UK, 30 June - 2 July 2008, pp. 2282 - 2287
  24. Effectiveness of TMR-based techniques to mitigate alpha-induced SEU accumulation in commercial SRAM-based FPGAs
    A. Manuzzato, S. Gerardin, A. Paccagnella, L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 55, Issue 4, Part 1, August 2008, pp. 1968 - 1973
  25. A New Mitigation Approach For Soft Errors In Embedded Processors
    F. Abate, L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 55, Issue 4, Part 1, August 2008, pp. 2063 - 2069
  26. Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs
    E. L. Rhod, C. A. Lang Lisb?a, L. Carro, M. Sonza Reorda, M. Violante
    JETTA: The Journal of Electronic Testing: Theory and Applications, Springer Netherlands, Volume 24, Numbers 1-3, June 2008, pp. 45 - 56
  27. Software and Hardware Techniques for SEU Detection in IP Processors
    C. Bolchini, A. Miele, M. Rebaudengo, F. Salice, D. Sciuto, L. Sterpone, M. Violante
    JETTA: The Journal of Electronic Testing: Theory and Applications, Springer Netherlands, 2008, pp. 35 - 44
  28. Experimental Validation of a Tool for Predicting the Effects of Soft Errors in SRAM-based FPGAs
    L. Sterpone, M. Violante, R. Harboe Sorensen, D. Merodio, F. Sturesson, R. Weigand, S. Mattsson
    IEEE Transactions on Nuclear Science, Vol. 54, No. 6, Part 1, December 2007, pp. 2576-2583
  29. Multi-level Fault Effects Evaluation
    L. Anghel, M. Rebaudengo, M. Sonza Reorda, M. Violante
    chapter in "Radiation Effects on Embedded Systems", Springer (The Netherlands), ISBN 978-1-4020-5645-1, 2007, pp. 69-88
  30. Optimization of Self Checking FIR filters by means of Fault Injection Analysis
    S. Pontarelli, L. Sterpone, G.C. Cardarilli, M. Re, M. Sonza Reorda, A. Salsano, M. Violante
    DFT2007, 22th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2007, pp. 96 - 104
  31. Sensitivity evaluation of TMR-hardened circuits to multiple SEUs induced by alpha particles in commercial SRAM-based FPGAs
    A. Manuzzato, P. Rech, S. Gerardin, A. Paccagnella, L. Sterpone, M. Violante
    DFT2007, 22th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2007, pp. 79 - 86
  32. Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders
    S. Pontarelli, L. Sterpone, G.C. Cardarilli, M. Re, M. Sonza Reorda, A. Salsano, M. Violante
    IOLTS2007: IEEE International On-Line Testing Symposium, 2007, pp. 194 - 196
  33. A new approach to estimate the effect of single event transients in complex circuits
    M. A. Aguirre, V.Baena, J. Tombs, M. Violante
    [accepted for publication on] IEEE Transactions on Nuclear Science, 2007
  34. A new hardware/software platform and a new 1/E neutron source for soft error studies: testing FPGAs at the ISIS facility
    M. Violante, L. Sterpone, A. Manuzzato, S. Gerardin, P. Rech, M. Bagatin, A. Paccagnella, C. Andreani, G. Gorini, A. Pietropaolo, G. Cardarilli, S. Pontarelli, C. Frost
    IEEE Transactions on Nuclear Science, 2007, Volume 54, Issue 4, Part 2, August 2007, pages 965 - 970
  35. Static and Dynamic Analysis of SEU effects in SRAM-based FPGAs
    L. Sterpone, M. Violante
    ETS2007: IEEE European Test Symposium, Freiburg, Germany, 2007, pp. 159 - 164
  36. A New Partial Reconfiguration-based Fault-Injection System to Evaluate SEU Effects in SRAM-based FPGAs
    L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, 2007, Volume 54, Issue 4, Part 2, August 2007, Pages 965 - 970
  37. An Analysis of SEU Effects in Embedded Operating Systems for Real-Time Applications
    L. Sterpone, M. Violante
    ISIE2007: IEEE International Symposium on Industrial Electronics, Vigo, Spain, June 4-7, 2007, pp. 3345 - 3349
  38. A new hardware/software platform for the soft-error sensitivity evaluation of FPGA devices
    M. Violante, M. Sonza Reorda, L. Sterpone, A. Manuzzato, S. Gerardin, P. Rech, M. Bagatin, A. Paccagnella, C. Andreani, G. Gorini, A. Pietropaolo, G. Cardarilli, A. Salsano, S. Pontarelli, C. Frost
    LATW2007: 8th IEEE Latin American Test Workshop, Cuzco, Peru, March 11-14, 2007
  39. A new FPGA-based edge detection system for the gridding of DNA microarray images
    L. Sterpone, M. Violante
    IMTC2007: IEEE Instrumentation and Measurement Technology Conference, Warsaw, Poland, May 1-3, 2007, pp. 1 - 6
  40. A new hardware architecture for performing the gridding of DNA microarray images
    L. Sterpone, M. Violante
    GLSVLSI2007: ACM 17th Great Lake Symposium on VLSI, Stresa, Italy, March 11-13, 2007, pp. 341 - 346
  41. A new decompression system for the configuration process of SRAM-based FPGAs
    L. Sterpone, M. Violante
    GLSVLSI2007: ACM 17th Great Lake Symposium on VLSI, Stresa, Italy, March 11-13, 2007, pp. 241 - 246
  42. Evaluating different solutions to design fault tolerant systems with SRAM-based FPGAs
    M. Sonza Reorda, L. Sterpone, M. Violante, F. Lima Kastensmidt, L. Carro
    JETTA: The Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers, Vol. 23, No. 1, February, 2007, pp. 47 - 54
  43. Hybrid Fault Detection Technique: A Case Study on Virtex-II Pro s PowerPC 405
    P. Bernardi, L. Sterpone, M. Violante, M. Portela-Garcia
    IEEE Transactions on Nuclear Science, 2006, Vol. 53, No. 6, December 2006, pp. 3550 - 3557
  44. Online hardening of programs against SEUs and SETs
    C.A.L. Lisboa, L. Carro, M. Sonza Reorda, M. Violante
    DFT2006, 21th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2006, pp. 280 - 290
  45. Combined software and hardware techniques for the design of reliable IP processors
    M. Rebaudengo, L. Sterpone, M. Violante, C. Bolchini, A. Miele, D. Sciuto
    DFT2006, 21th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2006, pp. 265 - 273
  46. Software-Implemented Hardware Fault Tolerance
    O. Goloubeva, M. Rebaudengo, M. Sonza Reorda, M. Violante
    Springer Science+Business Media, LLC, New York (USA), ISBN: 0-387-26060-9, pages 228
  47. Hardware-in-the-loop-based Dependability Analysis of Automotive Systems
    M. Sonza Reorda, M. Violante
    IOLTS06: IEEE International On-Line Testing Symposium, 2006, Como, Italy, pp. 229-234
  48. Hardening FPGA-based systems against SEUs: A new design methodology
    L. Sterpone, M. Violante
    Academy Publisher Journal of Computers, Vol. 1, No. 1, April 2006, pp. 22 - 30
  49. Dependability evaluation of transient fault effects in Reconfigurable Compute Fabric devices
    L. Sterpone, M. Violante
    IOLTS2006, IEEE 12th International On-Line Testing Symposium , 2006, pp. 189 - 190
  50. An Analysis based on Fault Injection of Hardening Techniques for SRAM-based FPGAs
    L. Sterpone, M. Violante, S. Rezgui
    IEEE Transactions on Nuclear Science, Vol. 53, Issue 4, August 2006, pp. 2054 - 2059
  51. ReCoM: A new Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications
    L. Sterpone, M. Violante
    DDECS2006: IEEE Workshop Design and Diagnostic of Electronic circuits and systems, 2006, pp. 54 - 58
  52. Fault Injection-based Reliability Evaluation of SoPCs
    M. Sonza Reorda, L. Sterpone, M. Violante, M. Portela-Garcia, C. Lopez-Ongil, L. Entrena
    ETS2006: IEEE European Test Symposium, 2006, pp. 75 - 82
  53. A new reliability-oriented place and route algorithm for SRAM-based FPGAs
    L. Sterpone, M. Violante
    IEEE Transactions on Computers, Vol. 55, No. 6, June 2006, pp. 732 - 744
  54. Early, Accurate Dependability Analysis of CAN-Based Networked Systems
    J. Perez, M. Sonza Reorda, M. Violante
    IEEE Design & Test of Computers, Vol. 23, No. 1, Jan/Feb. 2006, pp. 38-45
  55. A New Hybrid Fault Detection Technique for Systems-on-a-Chip
    P. Bernardi, L. M. Veiras Bolzani, M. Rebaudengo, M. Sonza Reorda, F. L. Vargas, M. Violante
    IEEE Transactions on Computers, Vol. 55, No. 2, Feb. 2006, pp. 185-198
  56. A new approach to cope with single event upsets in processor-based systems
    M. Schillaci, M. Sonza Reorda, M. Violante
    LATW2006, 7th IEEE Latin-American Test Workshop, Buenos Aires, Argentina, March 26-29 2006, pp. 145-150
  57. A Fault Injection Environment for SoPC's Embedded Microprocessors
    M. Portela-Garcia, L. Sterpone, C. Lopez-Ongil, M. Sonza Reorda, M. Violante
    LATW2006, 7th IEEE Latin-American Test Workshop, Buenos Aires, Argentina, March 26-29 2006, pp. 68-73
  58. A new approach to compress the configuration information of programmable devices
    L. Sterpone, M. Violante, M. Martina, G. Masera, A. Molino, F. Vacca
    DATE2006: IEEE Design, Automation and Test in Europe, 2006, pp. 1 - 4
  59. An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors
    P. Bernardi, L. Bolzani, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DFT2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 307-312
  60. A design flow for protecting FPGA-based systems against single event upsets
    L. Sterpone, M. Violante
    DFT2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 436 - 444
  61. Automatic Generation of Test Sets for SBST of Microprocessor IP Cores
    E. Sanchez, M. Sonza Reorda, G. Squillero, M. Violante
    SBCCI 2005, 18th IEEE Symposium on Integrated Circuits and Systems Design, pp. 74-79
  62. On-line Detection of Control-Flow Errors in SoCs by means of an Infrastructure IP core
    P. Bernardi, L. Bolzani, M. Rebaudengo, M. Sonza Reorda, F. Vargas, M. Violante
    IEEE Dependable Systems and Networks Symposium, july 2005, pp. 50 -58
  63. A New Analytical Approach to Estimate the Effects of SEUs in TMR Architectures Implemented Through SRAM-based FPGAs
    L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, 2005, Vol. 52, No. 6, December 2005, pp. 2217 - 2223
  64. Analysis of the robustness of the TMR architecture in SRAM-based FPGAs
    L. Sterpone, M. Violante
    IEEE Transactions on Nuclear Science, 2005, Vol. 52, No. 5, October 2005, pp. 1545 - 1549
  65. An experimental analysis of hardening techniques for SRAM-based FPGAs
    L. Sterpone, M. Violante, S. Rezgui
    RADECS 2005: 8th European Conference on Radiation and Its Effects on Component and Systems, 2005, pp. J5-1 - J5-4
  66. New Evolutionary Techniques for Test-Program Generation for Complex Microprocessor Cores
    E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero, L. Sterpone, M. Violante
    GECCO05: Genetic and Evolutionary Computation Conference, Washington, DC, USA, June 25-29 2005, pp. 2193-2194
  67. System-level Test and Validation of Hardware/Software Systems
    M. Sonza Reorda, Z. Peng, M. Violante
    Series: Springer Series in Advanced Microelectronics, Vol. 17, Springer, London (UK), ISBN 1-85233-899-7
  68. RoRA: Reliability-oriented Place and Route for SRAM-based FPGAs
    L. Sterpone, M. Sonza Reorda, M. Violante
    PRIME05: IEEE Ph.D. Research In Micro-Electronics & Electronics, 2005, pp. 147-150
  69. Efficient Estimation of SEU effects in SRAM-based FPGAs
    M. Sonza Reorda, L. Sterpone, M. Violante
    IOLTS 2005: IEEE International On-line Testing Symposium, 2005, pp. 54-59
  70. Multiple errors produced by single upsets in FPGA configuration memory: a possible solution
    M. Sonza Reorda, L. Sterpone, M. Violante
    ETS2005: IEEE European Test Symposium, 2005, pp. 136-141
    BEST PAPER AWARD at IEEE ETS 2005
  71. Improved Software-Based Processor Control-Flow Errors Detection Technique
    O. Goloubeva, M. Rebaudengo, M. Sonza Reorda, M. Violante
    RAMS2005: The Annual Reliability and Maintainability Symposium, 2005, Session 14B
  72. Simulation-Based Analysis of SEU Effects in SRAM-Based FPGAs
    M. Violante, L. Sterpone, M. Ceschia, D. Bortolato, P. Bernardi, M. Sonza Reorda, A. Paccagnella
    IEEE Transactions on Nuclear Science, Vol. 51, No. 6, December 2004, pp. 3354-3359
  73. Validation of the dependability of CAN-based networked systems
    F. Corno, J. Perez, M. Ramasso, M. Sonza Reorda, M. Violante
    IEEE High-level Design Validation and Test Workshop, pp. 161-164, 2004
  74. A multi-level approach to the dependability analysis of CAN networks for automotive applications
    F. Corno, J. Perez, M. Ramasso, M. Sonza Reorda, M. Violante
    International Conference Integrated Chassis Control(ICC), 10-12, Nov. 2004
  75. Software Techniques for Dependable Computer-based Systems
    O. Goloubeva, M. Rebaudengo, M. Sonza Reorda, M. Violante
    chapter in "Space radiation environment and its effects on spacecraft components and systems", C padu s d., Toulouse (France), ISBN 2-85428-654-5, 2004, pp. 461-480
  76. On-line Analysis and Perturbation of CAN Networks
    M. Sonza Reorda, M. Violante
    IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004, pp. 424-432
  77. A new approach to software-implemented fault tolerance
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    JETTA: The Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers, N. 20, August 2004, pp. 433-437
  78. A multi-level approach to the dependability analysis of networked systems based on the CAN protocol
    F. Corno, J. Perez, M. Sonza Reorda, M. Violante
    SBCCI04: IEEE Symposium on Integrated Circuits and Systems Design, 2004, pp. 71-75
  79. Hybrid Soft Error Detection by means of Infrastructure IP cores
    L. Bolzani, M. Rebaudengo, M. Sonza Reorda, F. Vargas, M. Violante
    IOLTS2004: IEEE International On-Line Testing Symposium, 2004, pp. 79-84
  80. On the evaluation of SEU sensitiveness in SRAM-based FPGAs
    P. Bernardi, M. Sonza Reorda, L. Sterpone, M. Violante
    IOLTS2004: IEEE International On-Line Testing Symposium, 2004, pp. 115-120
  81. An Infrastructure IP for Soft Error Detection
    L. Bolzani, M. Rebaudengo, M. Sonza Reorda, F. Vargas, M. Violante
    LATW'04: IEEE Latin-American Test WorkShop
  82. A Local Analysis of the Genotype-Fitness Mapping in Hardware Optimization Problems
    E. Sanchez, G. Squillero, M. Violante
    CEC2004, Congress on Evolutionary Computation, Portland (Oregon), June 20-23, 2004, pp. 871-878
  83. Exploiting HW Acceleration for Classifying Complex Test Program Generation Problems
    E. Sanchez, G. Squillero, M. Violante
    of Evolutionary Computing: EvoWorkshops 2004 proceedings, Coimbra (Portugal), April 5-7 2004, pp. 230-239
  84. Efficient analysis of single event transients
    M. Sonza Reorda, M. Violante
    Journal of Systems Architecture, Elsevier Science, Amsterdam, Netherland, Vol. 50, No. 5, 2004, pp. 239-246
  85. Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA
    M. Bellato, P. Bernardi, D. Bortolato, A. Candelori, M. Ceschia, A. Paccagnella,, M. Rebaudengo, M. Sonza Reorda, M. Violante, P. Zambolin
    DATE2004: Design, Automation and Test in Europe, 2004, pp. 188-193
  86. Automatic Generation of Validation Stimuli for Application-Specific Processors
    O. Goloubeva, M. Sonza Reorda, M. Violante
    DATE2004: Design, Automation and Test in Europe, 2004, pp. 188-193
  87. Impact of data cache memory on the single event upset-induced error rate of microprocessors
    F. Faure, R. Velazco, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 50, No. 6, December 2003, pp. 2101-2106
  88. Identification and classification of single-event upsets in the configuration memory of sram-based fpgas
    M. Ceschia, M. Violante, M. Sonza Reorda, A. Paccagnella, P. Bernardi, M. Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, A. Candelori
    IEEE Transactions on Nuclear Science, Vol. 50, No. 6, December 2003, pp. 2088-2094
  89. Accurate single-event-transient analysis via zero-delay logic simulation
    M. Violante
    IEEE Transactions on Nuclear Science, Vol. 50, No. 6, December 2003, pp. 2113-2118
  90. Accurate Analysis of Single Event Upsets in a Pipelined Microprocessor
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    Journal of Electronic Testing: Theory and Applications, Vol. 19, No. 5, October 2003, pp. 577-584
  91. Accurate Dependability Analysis of CAN-based Networked Systems
    J. Perez, M. Sonza Reorda, M. Violante
    SBCCI2003: 16th IEEE Symposium on Integrated Circuits and Systems Design, 2003, pp. 337-342
  92. High-level test generation for hardware testing and software validation
    O. Goloubeva, M. Sonza Reorda, M. Violante
    HLDVT2003: IEEE International Workshop on High Level Design Validation and Test, 2003, pp- 143-148
  93. Emulation-based Analysis of Soft Errors in Deep Sub-micron Circuits
    M. Sonza Reorda, M. Violante
    FPL2003: International Conference on Field Programmable Logic and Application, 2003, pp. 616-626
  94. Detailed comparison of dependability analyses performed at RT and gate levels
    A. Ammari, R. Leveugle, M. Sonza Reorda, M. Violante
    DFT2003: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2003, pp. 336-343
  95. Soft-error Detection Using Control Flow Assertions
    O. Goloubeva, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DFT2003: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2003, pp. 581-588
  96. Dependability Analysis of CAN Networks: an emulation-based approach
    J. Perez, M. Sonza Reorda, M. Violante
    DFT2003: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2003, pp 537-544
  97. A programmable BIST approach for the diagnosis of embedded memory cores
    D. Appello, P. Bernardi, A. Fudoli, M. Rebaudengo, M. Sonza Reorda, V. Tancorre, M. Violante
    ETW03: 8th IEEE European Test Workshop (Formal Proceedings), The Netherlands, May 25-28, 2003, pp. 101-102
  98. New Techniques for efficiently assessing reliability of SOCs
    P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    Microelectronics Journal, Vol. 34, No. 1, January 2003, pp. 53-61, Elsevier Science, Amsterdam, Netherland.
  99. Exploiting programmable BIST for the diagnosis of embedded memory cores
    D. Appello, P. Bernardi, A. Fudoli, M. Rebaudengo, M. Sonza Reorda, V. Tancorre, M. Violante
    ITC2003: IEEE International Test Conference, 2003, pp. 379-385
  100. Accurate and Efficient Analysis of Single Event Transients in VLSI Circuits
    M. Violante, M. Sonza Reorda
    IOLTS2003: IEEE International On-Line Testing Symposium, 2003, pp. 101-105
  101. Analyzing SEU Effects in SRAM-based FPGAs
    M. Violante, M. Ceschia, M. Sonza Reorda, A. Paccagnella, P. Bernardi, M. Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, and A. Candelori
    IOLTS2003: IEEE International On-Line Testing Symposium, 2003, pp. 119-123
  102. A P1500 compatible microprocessor-based approach for the test of Embedded Flash Memories
    P. Bernardi, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DATE2003: Design, Automation and Test in Europe, 2003, pp. 720-725
  103. An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    DATE2003: Design, Automation and Test in Europe, 2003, pp. 602-607
  104. A new Software-based technique for low-cost Fault-Tolerant application
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    RAMS2003: The Annual Reliability and Maintainability Symposium, 2003, pp. 25-28
  105. Coping With SEUs/SETs in Microprocessors by means of Low-Cost Solutions: A Comparative Study
    M. Rebaudengo, M. Sonza Reorda, M. Violante, B. Nicolescu, R. Velazco
    IEEE Transactions on Nuclear Science, Vol. 49, No. 3, June 2002, pp. 1491-1495
  106. An FPGA-based approach for speeding-up Fault Injection campaigns on safety-critical circuits
    P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    Journal of Electronic Testing:Theory and Applications, Vol. 18, No. 3, June 2002, pp. 261-271
  107. A Software Fault Tolerance Method for Safety-Critical Systems: Effectiveness and Drawbacks
    B. Nicolescu, R. Velazco, M. Sonza Reorda, M. Rebaudengo, M. Violante
    SBCCI: 15th IEEE Symposium on Integrated Circuits and Systems Design, Porto Alegre (Brasil), Septempber 2002, pp. 101-106
  108. A Hierarchical Approach for Designing Dependable Systems
    M. Sonza Reorda, M. Violante, N. Mazzocca, S. Venticinque, A. Bobbio, G. Franceschinis
    HLDVT2002: IEEE International Workshop on High Level Design Validation and Test, 2002, pp. 63-67
  109. High-Level and Hierarchical Test Sequence Generation
    G. Jervan, Z. Peng, O. Goloubeva, M. Sonza Reorda, M. Violante
    HLDVT2002: IEEE International Workshop on High Level Design Validation and Test, 2002, pp. 169-174
  110. A simplified gate-level fault model for crosstalk effects analysis
    P. Civera, L. Macchiarulo, M. Violante
    DFT2002: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 31-39
  111. Fault List Compaction through Static Timing Analysis for Efficient Fault Injection Experiments
    M. Sonza Reorda, M. Violante
    DFT2002: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 263-271
  112. A new functional fault model for FPGA Application-Oriented testing
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    DFT2002: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 372-380
  113. Simulation-based analysis of SEU effects on SRAM-based FPGAs
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    FPL2002: International Conference on Field Programmable Logic and Application, 2002, pp. 607-615
  114. Analysis of SEU effects in a pipelined processor
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    IOLTW2002: IEEE International On-line Testing Workshop, 2002, pp. 206-210
  115. Behavioral-level fault models comparison: an experimental approach
    O. Goloubeva, M. Sonza Reorda, M. Violante
    ICAM2002, Computer-aided Technologies in Applied Mathematics, September 2002, Tomsk, Russia
  116. Experimental analysis of fault models for behavioral-level test generation
    O. Goloubeva, M. Sonza Reorda, M. Violante
    DDECS2002: IEEE Design & Diagnostic of Electronic Circuits & Systems, 2002, pp. 416-419
  117. A new approach to software-implemented fault tolerance
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    LATW2002: IEEE Latin American Test Workshop, 2002
  118. Behavioral-level test vector generation: fault model selection and preliminary test generation results
    O. Goloubeva, M. Sonza Reorda, M. Violante
    Design of Circuits and Integrated Systems, 2002
  119. FPGA-based Fault Injection for Microprocessor Systems
    P. L. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    ATS, IEEE Asian Test Symposium, 2001, pp. 304-309
  120. Exploiting Circuit Emulation for Fast Hardness Evaluation
    P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 48, No. 6, December 2001, pp. 2210-2216
  121. A source-to-source compiler for generating dependable software
    M. Rebaudengo, M. Sonza Reorda, M. Torchiano, M. Violante
    SCAM, IEEE International Workshop on Source Code Analysis and Manipulation, 2001, pp. 33-42
  122. Exploiting FPGA-based Techniques for Fault Injection Campaigns on VLSI Circuits
    P. L. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DFT, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2001, pp. 250-258
  123. Exploring Test Solutions by means of System-level Design Tools
    M. Lajolo, M. Sonza Reorda, M. Violante
    DCIS, Design of Circuits and Integrated Systems, 2001
  124. FPGA-based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits
    P. L. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    FPL 2001, 11th International Conference on Field Programmable Logic and Applications, Belfast (UK), August, 2001, pp. 493-502
  125. Exploiting FPGA for accelerating Fault Injection Experiments
    P. L. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IOLTW, IEEE On-Line Testing Workshop, Taormina (Italy), July 9-11, 2001, pp. 9-13
  126. System Safety through Automatic High-level Code Transformations: an Experimental Evaluation
    M. Rebaudengo, M. Sonza Reorda, M. Violante, P. Cheynet, B. Nicolescu, R. Velazco
    DATE: IEEE Design, Automation & Test in Europe Conference, Munich (Germany), 13-16 March 2001, pp. 297-301
  127. On the Test of Microprocessor IP Cores
    F. Corno, M. Sonza Reorda, G. Squillero, M. Violante
    DATE2001: IEEE Design, Automation & Test in Europe Conference, Munich (Germany), 13-16 March 2001, pp. 209-213
  128. Early evaluation of bus interconnects dependability for System-on-Chip Designs
    M. Lajolo, M. Sonza Reorda, M. Violante
    14th IEEE International Conference on VLSI Design, Bangalore (India), January 2001, pp. 371-376
  129. Experimentally evaluating an automatic approach for generating safety-critical software with respect to transient errors
    P. Cheynet, B. Nicolescu, R. Velazco, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IEEE Transactions on Nuclear Science, Vol. 47, No. 6, December 2000, pp. 2231-2236
  130. Dependability Evaluation through Effective Fault Injection Techniques on VHDL Descriptions
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    ISATA 2000: Automotive and Transportation Technology, Dublin (Ireland), September 2000, pp. 171-179
  131. A Genetic Algorithm-based System for Generating Test Programs for Microprocessor IP Cores
    F. Corno, M. Sonza Reorda, G. Squillero, M. Violante
    ICTAI2000: The Twelfth IEEE International Conference on Tools with Artificial Intelligence, Vancouver, British Columbia, Canada, November 13-15, 2000, pp. 195-198
  132. Early power estimation for System-on-Chip designs
    M. Lajolo, L. Lavagno, M. Sonza Reorda, M. Violante
    PATMOS 2000: International Workshop - Power and Timing Modeling Optimization and Simulation, G? ttingen (Germany), September 2000, pp. 108-117
  133. Behavioral-level Test Vector Generation for System-on-Chip Designs
    M. Lajolo, L. Lavagno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IEEE International High Level Design Validation Workshop, The Claremont Resort & Spa, Berkeley, California, November 8-10 2000, pp. 21-26
  134. Speeding-up Fault Injection Campaigns in VHDL models
    B. Parrotta, M. Rebaudengo, M. Sonza Reorda, M. Violante
    19th International Conference on Computer Safety, Reliability and Security, Safecomp 2000, Rotterdam, The Nederlands, October 2000, pp. 27-36
  135. An experimental evaluation of the effectiveness of automatic rule-based transformations for safety-critical applications
    M. Rebaudengo, M. Sonza Reorda, M. Torchiano, M. Violante
    DFT'00, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, October 2000, pp. 257-265
  136. Evaluating the effectiveness of a Software Fault-Tolerance technique on RISC- and CISC-based architectures
    M. Rebaudengo, M. Sonza Reorda, M. Violante, P. Cheynet, B. Nicolescu, R. Velazco
    IOLTW2000: International On-Line Test Workshop, Mallorca (Spain), July 2000, pp. 17-20
  137. New Techniques for Accelerating Fault Injection in VHDL descriptions
    B. Parrotta, M. Rebaudengo, M. Sonza Reorda, M. Violante
    IOLTW2000: International On-Line Test Workshop, Mallorca (Spain), July 2000, pp. 61-66
  138. Automatic Test Bench Generation for Simulation-based Validation
    M. Lajolo, L. Lavagno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    CODES2000: IEEE International Workshop on Hardware/Software Codesign, San Diego (USA), May 2000, pp. 136-140
  139. CA-CSTP: A new BIST Architecture for Sequential Circuits
    F. Corno, M. Sonza Reorda, G. Squillero, M. Violante
    ETW2000: European Test Workshop, May 2000, pp. 167-172
  140. System-level Test Bench Generation in a Co-design Framework
    M. Lajolo, L. Lavagno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    ETW2000: European Test Workshop, May 2000, pp. 25-30
  141. Low Power BIST via Hybrid Cellular Automata
    F. Corno, M. Rebaudengo, M. Sonza Reorda, G. Squillero, M. Violante
    VTS2000: 18th IEEE VLSI Test Symposium, Montreal, Canada, May 2000, pp. 29-34
  142. Prediction of Power Requirements for High-Speed Circuits
    F. Corno, M. Rebaudengo, M. Sonza Reorda, G. Squillero, M. Violante
    EvoTel2000: European Workshops on Telecommunications, Edinburgh (UK), May 2000, pp. 247-254
  143. Evaluating System Dependability in a Co-Design Framework
    M. Lajolo, L. Lavagno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DATE2000: Design, Automation and Test in Europe, Paris (F), March 2000, pp. 586-590
  144. Optimal Vector Selection for Low Power BIST
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DFT99: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, November 1-3 1999 - Albuquerque, New Mexico (USA), pp. 219-226
  145. Soft-error Detection through Software Fault-Tolerance techniques
    M. Rebaudengo, M. Sonza Reorda, M. Torchiano, M. Violante
    DFT99: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, November 1-3 1999 - Albuquerque, New Mexico (USA), pp. 210-218
  146. On Reducing the Peak Power Consumption of Test Sequences
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    European Conference on Circuit Theory and Design, Stresa, Italy, August 1999, pp. 247-250
  147. A Peak-Power Estimation Algorithm for Sequential Circuits
    F. Corno, M. Rebaudengo, M. Sonza Reorda, V. Speranza, M. Violante
    European Conference on Circuit Theory and Design, Stresa, Italy, August 1999, pp. 896-899
  148. A New BIST Architecture for Low Power Circuits
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    ETW99: IEEE European Test Workshop, Konstanz(D), May 1999
  149. Test Pattern Generation under Low Power Constraints
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    R. Poli, H-M. Voigt, S. Cagnoni, D. Corne, G. Smith, T. Fogarty (eds.), Evolutionary Image Analysis, Signal Processing and Telecommunications First European Workshops, EvoIASP'99 and EuroEcTel'99 Goteborg, Sweden, May 1999 Joint Proceedings, Springer LNCS, 1999, pp. 162-170
  150. ALPS: A Peak Power Estimation Tool for Sequential Circuits
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    GLS-VLSI99: 8th Great Lakes Symposium on VLSI, Ypsilanti MI (USA), March 4-6 1999, pp. 350-353
  151. Transformation-based Peak Power Reduction for Test Sequences
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    poster at VOLTA99: IEEE Alessandro Volta Memorial Workshop on Low Power Design, Como (ITALY), March 3-5 1999, pp. 78-83
  152. SymFony: a Hybrid Topological-Symbolic ATPG exploiting RT-level Information
    F. Corno, P. Prinetto, M. Sonza Reorda, M. Violante, U. Glaeser, H. T. Vierhaus
    IEEE Transactions on Computer-Aided Design, February 1999, Vol. 18, No. 2, pp. 191-202
  153. Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection
    F. Corno, P. Prinetto, M. Sonza Reorda, M. Violante
    DATE98: Design, Automation and Test in Europe, Paris (F), February 1998
  154. Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, M. Violante
    ATS97: The Sixth IEEE Asian Test Symposium, Akita (JP), November 1997
  155. Testable Synthesis through RT-level DfT rules
    S. Barbagallo, F. Corno, D. Medina, P. Prinetto, M. Sonza Reorda, M. Violante
    ED&TC97: IEEE European Design and Test Conference User's Forum, Paris (F), March 1997, pp. 57-61