Papers

  1. A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing
    M. Valka, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, E. Sanchez, M. De Carvalho, M. Sonza Reorda,
    2011 16th IEEE European Test Symposium (ETS), 2011, pp. 153-158

  2. A Low-cost Emulation System for Fast Co-verification and Debug
    Lagos-Benites J., Grosso M., Sterpone L., Sonza Reorda M., Audisio G., Pipponzi M., Sabatini M.
    IEEE European Test Symposium, 2011, pp. 212-212

  3. A New Reconfigurable Clock-gating Technique for Low Power SRAM-based FPGAs
    L. Sterpone, D. Matos, L. Carro, S. Wong, F. Anjam
    IEEE Design, Automation and Test in Europe, 2011, pp. 1-6

  4. A general approach for improving RNS Montgomery exponentiation using pre-processing
    Gandino F., Lamberti F., Bajard J.C., Montuschi P.
    20th IEEE Symposium on Computer Arithmetic (ARITH2011), 2011, pp. 195-204

  5. A new Architecture to Cross-Fertilize On-line and Manufacturing Testing
    P. Bernardi, M. Sonza Reorda
    Twentieth IEEE Asian Test Symposium (ATS 2011), 2011, pp. 142-147

  6. A novel access scheme for online test in RFID memories
    Sanchez E.R., Rebaudengo M.
    2nd IEEE Latin American Symposium on Circuits and Systems (LASCAS), 2011, pp. 1-4

  7. Adaptive fuzzy-MAC for power reduction in wireless sensor networks
    Sanchez E.R., Montrucchio B., Murillo L.M., Rebaudengo M.
    New Technologies, Mobility and Security (NTMS), 2011 4th IFIP International Conference on, 2011, pp. 1-5

  8. Adaptive opponent modelling for the iterated prisoner's dilemma
    E. Piccolo, G. Squillero
    Evolutionary Computation (CEC), 2011, pp. 836-841

  9. An Effective Methodology for On-line Testing of Embedded Microprocessors
    P. Bernardi, L. Ciganda, E. Sanchez, M. Sonza Reorda
    IEEE 17th International on-line testing symposium (IOLTS), 2011, 2011, pp. 270-275

  10. An FPGA-emulation-based platform for characterization of digital baseband communication systems
    Lagos-Benites J., Grosso M., Sonza Reorda M., Audisio G., Pipponzi M., Sabatini M., Avantaggiati V.A.
    International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011, pp. 391-398

  11. An adaptive power-aware multi-hop routing algorithm for wireless sensor networks
    Sanchez E.R., Murillo L.M., Montrucchio B., Rebaudengo M.
    8th International Conference on Information Technology: New Generations (ITNG), 2011, pp. 112-115

  12. An adaptively reconfigurable computing framework for intelligent robotics
    Hussain M., Din A., Violante M., Bona B.
    2011 IEEE/ASME International Conference on Advanced Intelligent Mechatronics (AIM 2011), 2011, pp. 996-1002

  13. Analysis of SEU Effects in Partially Reconfigurable SoPCs
    L. Sterpone, F. Margaglia, M. Koester, J. Hagemeyer, M. Porrman
    IEEE NASA/ESA Conference on Adaptive Hardware Systems, 2011, pp. 129-136

  14. Control flow checking through embedded debug interface
    Parra L., Lindoso A., Portela M., Entrena L., Grosso M., Sonza Reorda M.
    26th Conference on Desing of Circuits and Integrated Systems, 2011, pp. 339-342

  15. Degree Distribution of Unit Disk Graphs with Uniformly Deployed Nodes on a Rectangular Surface
    R. Ferrero, F. Gandino
    2011 International Conference on Broadband and Wireless Computing, Communication and Applications (BWCCA), 2011, pp. 255-262

  16. Efficient energy-aware routing for sensor networks
    Sanchez E.R., Murillo L.M., Montrucchio B., Rebaudengo M.
    2nd IEEE Latin American Symposium on Circuits and Systems (LASCAS), 2011, pp. 1-4

  17. Evaluation Framework of Opportunistic Flooding in Wireless Sensor Networks
    Zhang L., Sanchez Sanchez E.R., Rebaudengo M.
    2011 Ninth IEEE/IFIP International Conference on Embedded and Ubiquitous Computing, 2011, pp. 87-94

  18. Evolution of Test Programs Exploiting a FSM Processor Model
    E. Sanchez, G. Squillero, A. Tonda
    Lecture notes in Computer Science, 2011, pp. 162-171

  19. Evolutionary failing-test generation for modern microprocessors
    E. Sanchez, G. Squillero, A. Tonda
    GECCO '11 Proceedings of the 13th annual conference companion on Genetic and evolutionary computation, 2011

  20. Fault Injection Analysis of Transient Faults in Clustered VLIW Processors
    L. Sterpone, D. Sabena, S. Campagna, M. Sonza Reorda
    14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2011, pp. 207-212

  21. Fault grading of software-based self-test procedures for dependable automotive applications
    Bernardi P., Grosso M., Sanchez E., Ballan O.
    Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011, pp. 1-2

  22. Group evolution: Emerging synergy through a coordinated effort
    E. Sanchez, G. Squillero, A. Tonda
    Evolutionary Computation (CEC), 2011 IEEE Congress on, 2011, pp. 2662-2668

  23. Implementing a safe embedded computing system in SRAM-based FPGAs using IP cores: A case study based on the Altera NIOS-II soft processor
    J. Perez Acle, M. Sonza Reorda, M. Violante
    2011 IEEE Second Latin American Symposium on Circuits and Systems (LASCAS), 2011, pp. 1-5

  24. Increasing Throughput in RFID Multi-Reader Environments Avoiding Reader-to-Reader Collisions
    Gandino F., Ferrero R., Montrucchio B., Rebaudengo M.
    2011 IEEE International Conference on Consumer Electronics (ICCE), 2011, pp. 37-38

  25. La formazione a distanza al Politecnico di Torino: nuovi modelli e strumenti
    Barbagallo S., Bertonasco R., Corno F., Mezzalama M., Sonza Reorda M., Venuto E.
    Didamatica 2011, 2011

  26. Monitoring and modeling building energy expenditure with sensor networks
    Sanchez E.R., Montrucchio B., Rebaudengo M.
    1st International Conference on Pervasive and Embedded Computing and Communications Systems (PECCS), 2011, pp. 283-287

  27. On the Functional Test of Branch Prediction Units based on Branch History Table
    Ernesto Sanchez, Matteo Sonza Reorda, Alberto Tonda
    19th IFIP/IFEE International Conference on Very Large Scale Integration and SoC, 2011, pp. 278-283

  28. On the Modeling of Gate Delay Faults by Means of Transition Delay Faults
    Bernardi P. , Sonza Reorda M. , Bosio A. , Girard P. , Pravossoudovitch S.
    Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2011 IEEE International Symposium on, 2011

  29. On the functional test of MESI controllers
    Ernesto Sanchez, Matteo Sonza Reorda
    12th Latin American Test Workshop (LATW), 2011, pp. 1-6

  30. Optimized embedded memory diagnosis
    M. De Carvalho, P. Bernardi, M. Sonza Reorda, N. Campanelli, T. Kerekes, D. Appello, M. Barone, V. Tancorre, M. Terzi
    2011 IEEE 14th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2011, pp. 347-352

  31. Post-silicon failing-test generation through evolutionary computation
    E. Sanchez, G. Squillero, A. Tonda
    VLSI and System-on-Chip (VLSI-SoC), 2011, pp. 164-167

  32. A New Placement Algorithm for the Mitigation of Multiple Cell Upsets in SRAM-based FPGAs
    Sterpone L.; N. Battezzati
    IEEE Design, Automation and Test in Europe 2010, 2010, pp. 1231-1236

  33. A Novel Scalable and Reconfigurable Emulation Platform for Embedded Systems Verification
    Di Marzio M, Grosso M., Sonza Reorda M., Sterpone L., Audisio G.; Sabatini M.
    Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, 2010, pp. 865-868

  34. A Programmable BIST for DRAM Testing and Diagnosis
    M. Grosso, P. Bernardi, M. Sonza Reorda, Y. Zhang
    IEEE International Test Conference, 2010

  35. A Software-based self-test methodology for system peripherals
    M. Grosso, W.J. Perez H., D. Ravotto, E. Sanchez, M. Sonza Reorda, J. Velasco Medina
    15th IEEE European Test Symposium (ETS), 2010, pp. 195-200

  36. A fault grading methodology for software-based self-test programs in systems-on-chip
    Ballan O., Bernardi P., Fontana G., Grosso M., Sanchez E.
    International Workshop on Microprocessor Test and Verification, 2010, pp. 43-46

  37. A framework to support the design of COTS-based reliable space computers for on-board data handling
    Campagna S., Violante M.
    On-Line Testing Symposium (IOLTS), 2010 IEEE 16th International, 2010, pp. 91-96

  38. A hardware accelerated framework for the generation of design validation programs for SMT processors
    Ernesto Sanchez; Danilo Ravotto; Sonza Reorda M.
    13th IEEE International Symposium on Design & Diagnostics of Elctronic Circuits and Systems, 2010

  39. A new framework for the automatic insertion of mitigation structures in circuits netlists
    Battezzati N., Serrone D. , Violante M.
    On-Line Testing Symposium (IOLTS), 2010 IEEE 16th International, 2010, pp. 190-191

  40. A tester architecture suitable for MEMS calibration and testing
    Ciganda L., Bernardi P., Sonza Reorda M., Barbieri D., Straiotto M., Bonaria L.
    ITC 2010, International Test Conference, 2010

  41. Advanced Speeding-up Techniques for SEU Sensitivity Assessment
    Grosso M.; Guzman-Miranda H
    IEEE International Symposium on Industrial Electonics, 2010, pp. 1995-2000

  42. An Exact and Efficient Critical Path Tracing Algorithm
    A. Bosio, P. Girard, S. Pravossoudovitch, P. Bernardi, M. Sonza Reorda
    Fifth IEEE International Symposium on Electronic Design, Test and Application, 2010 (DELTA '10), 2010, pp. 164-169

  43. An On-line Fault Detection Technique based on Embedded Debug Features
    M. Grosso, M. Sonza Reorda, M. Portela-Garcia, M. Garcia-Valderas, C. Lopez-Ongil, L. Entrena
    IEEE 16th International On-Line Testing Symposium, 2010, pp. 167-172

  44. An adaptive tester architecture for volume diagnosis
    P. Bernardi, M. Grosso, M. Sonza Reorda
    15th IEEE European Test Symposium (ETS), 2010, pp. 227-232

  45. An enhanced strategy for functional stress pattern generation for system-on-chip reliability characterization
    De Carvalho M., Bernardi P., Sanchez E., Sonza Reorda M.
    2010 11th International Workshop on Microprocessor Test and Verification 2010, 2010

  46. An integrated flow for the design of hardened circuits on SRAM-based FPGAs
    Bolchini C., Miele A., Sandionigi C., Battezzati N., Sterpone L., Violante M.
    15th IEEE European Test Symposium, 2010, pp. 214-219

  47. Analysis of Root Causes of Alpha Sensitivity Variations on Microprocessors Manufactured using Different Cell Layouts
    P. Rech, M. Grosso, F. Melchiori, D. Loparco, D. Appello, L. Dilillo, A. Paccagnella, M. Sonza Reorda
    IEEE 16th International On-Line Testing Symposium, 2010, pp. 29-34

  48. Application-oriented SEU cross-section of a processor soft core for Atmel RHBD FPGAs
    Battezzati N., Margaglia F., Violante M., Decuzzi F., Merodio Codinachs D., Bancelin B.
    11th European Conference on Radiation and Its Effects on Component and Systems, 2010

  49. CUMULATIVE EMBEDDED MEMORY FAILURE BITMAP DISPLAY ANALYSIS
    Paolo Bernardi; Alessandro Panariti; Sonza Reorda M.; Tamas Kerekes; Davide Appello; Mario Barone
    13th IEEE International Symposium on Design & Diagnostics of Electronic Circuits and Systems, 2010

  50. Cumulative embedded memory failure bitmap display & analysis
    Campanelli N., Kekeres T., Bernardi P., De Carvalho M., Panariti A., Sonza Reorda M., Appello D., Barrone M.
    2010 IEEE 13th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 2010, pp. 255-260

  51. Enhanced Observability in Microprocessor-based Systems for Permanent and Transient Fault Resiliency
    Entrena L., Gallardo-Campos M., Garcia-Valderas M., Grosso M., Lopez-Ongil C., Portela-Garcia M., Sonza Reorda M.
    Conference on Design of Circuits and Integrated Systems, 2010, pp. 240-245

  52. Evolving Individual Behavior in a Multi-Agent Traffic Simulator
    E. Sanchez; Squillero G.; A. Tonda
    Lecture notes in Computer Science, 2010, pp. 11-20

  53. Exploiting Evolution for an Adaptive Drift-Robust Classifier in Chemical Sensing
    S. Di Carlo; M. Falasconi; E. Sanchez; A. Scionti; Squillero G.; A. Tonda
    Lecture notes in Computer Science, 2010, pp. 412-421

  54. Exploiting Wireless Sensor Networks for Monitoring Building Performance
    D. Apiletti; E. Baralis; T. Cerquitelli; S. Chiusano; B. Montrucchio; L.M. Murillo; M. Rebaudengo; E.R. Sanchez; D. Tonelli
    Congresso Nazionale AICA 2010, 2010

  55. Fair Anti-Collision Protocol in Dense RFID Networks
    R. Ferrero, F. Gandino, B. Montrucchio, M. Rebaudengo
    The Third International EURASIP Workshop on RFID Technology, 2010, pp. 101-105

  56. Functional Test Generation for DMA Controllers
    Grosso M; W.J. Perez H; Ravotto D; Sanchez E.; Sonza Reorda M; Velasco Medina J
    11th IEEE Latin-American Test Workshop 2010, 2010

  57. Generating Power-Hungry Test Programs for Power-Aware Validation of Pipelined Processors
    Andrea Calimera, Enrico Macii, Danilo Ravotto, Ernesto Sanchez, Matteo Sonza Reorda
    23rd annual symposium on Integrated circuits and system design, 2010, pp. 61-66

  58. Hypervisor-Based Virtual Hardware for Fault Tolerance in COTS Processors Targeting Space Applications
    Campagna S, Hussain M., Violante M
    Defect and Fault Tolerance in VLSI Systems (DFT), 2010 IEEE 25th International Symposium on, 2010, pp. 44-51

  59. On the mitigation of SET broadening effects in integrated circuits
    Sterpone L., Battezzati N.
    IEEE Design and Diagnostics of Electronic Circuits and Systems, 2010, pp. 36-39

  60. Towards Drift Correction in Chemical Sensors Using an Evolutionary Strategy
    Di Carlo S., Falasconi M., Sanchez E., Scionti A., Squillero G., Tonda A.
    GECCO, Proceedings of the 12th annual conference on Genetic and evolutionary computation, 2010, pp. 1329-1330

  61. A Deterministic Methodology for Identifying Functionally Untestable Path-Delay Faults in Microprocessor Cores
    Bernardi P; Grosso M.; Sanchez E; Sonza Reorda M
    9th International Workshop on Microprocessor Test and Verification (MTV'08), 2009, pp. 103-108

  62. A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips
    Sonza Reorda M.; M. Violante; C. Meinhardt; R. Reis
    Design, Automation & Test in Europe Conference & Exhibition (DATE '09), 2009, pp. 352-357

  63. A new RC design for mixed-grain based dynamically reconfigurable architectures
    E. Rhod; Sterpone L.; L. Carro
    IEEE International Conference on Electronics Circuits and Systems, 2009, pp. 984-987

  64. A study of the Single Event Effects Impact on Functional Mapping within Flash-based FPGAs
    Abate F.; Lima Kastensmidt F; Sterpone L; Violante M
    DATE'09, 2009

  65. An Enhanced FPGA-Based Low-Cost Tester Platform Exploiting Effective Test Data Compression for SoCs
    L. Ciganda; F. Abate; P. Bernardi; M. Bruno; Sonza Reorda M.
    12th IEEE Symposium on Design and Diagnostics of Electronic Systems (DDECS), 2009, pp. 258-263

  66. An I-IP Based Approach for the Monitoring of NBTI Effects in SoCs
    Appello D; Bernardi P.; Guardiani C; Shibkov A; Brambilla A; Storti Gajani G; Piazza F
    IEEE Internation On-Line Test Symposium (IOLTS'09), 2009

  67. An In-Vehicle Infotainment Software Architecture Based on Google Android
    Gianpaolo Macario; Torchiano M.; Massimo Violante
    IEEE Symposium on Industrial Embedded Systems (SIES) 2009, 2009, pp. 257-260

  68. An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAs
    Matteo Sonza Reorda; Massimo Violante; Cristina Meinhardt
    24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009 (DFT09), 2009, pp. 254-262

  69. An efficient fault simulation technique for transition faults in non-scan sequential circuits
    Bosio A; Girard P; Pravossoudovich S; Bernardi P.; Sonza Reorda M
    Design and Diagnostics of Electronic Circuits & Systems, 2009. DDECS '09., 2009

  70. An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs
    Ciganda L., Abate F., Bernardi P., Bruno M., Sonza Reorda M.
    12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2009, 2009, pp. 258-263

  71. Application-oriented SEU sensitiveness analysis of Atmel rad-hard FPGAs
    Battezzati N.; Decuzzi F; Violante M; Briet M
    Proceedings of the 15th IEEE International On-Line Testing Symposium, 2009, pp. 89-94

  72. Automatic Detection of Software Defects: an Industrial Experience
    Gandini S; Ravotto D; Ruzzarin W; Sanchez E; Squillero G; Tonda A.P.
    Proceedings GECCO 2009, 2009

  73. Automatic Functional Test Pattern Generation for SoC Reliability Characterization
    Appello D; Bernardi P; Cagliesi R; Giancarlini M; Grosso M.; Sanchez E; Sonza Reorda M
    14th IEEE European Test Symposium (ETS'09), 2009, pp. 93-98

  74. Design validation of multithreaded architectures using concurrent threads evolution
    Ravotto D; Sanchez E.; Sonza Reorda M; Squillero G
    22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes, 2009

  75. DfT Reuse for Low-Cost Radiation Testing of SoCs: A Case Study
    D. Appello; P. Bernardi; S. Gerardin; M. Grosso; A. Paccagnella; P. Rech; Sonza Reorda M.
    27th IEEE VLSI Test Symposium (VTS '09), 2009, pp. 276-281

  76. Diseño de placas con lógica programable como experiencia educativa en cursos de grado.
    Fernández S., Bergeret A., Ciganda L., Oliver J.P.
    Actas de las IX jornadas de computación reconfigurable y aplicaciones, 2009, pp. 283-292

  77. Evaluating Alpha-induced Soft Errors in Embedded Microprocessors
    Bernardi P.; M. Grosso; M. Sonza Reorda; D. Appello; P. Rech; S. Gerardin; A. Paccagnella
    IEEE Internation On-Line Test Symposium (IOLTS'09), 2009

  78. Evaluating the impact of DFM library optimizations on alpha-induced SEU sensitivity in a microprocessor core
    Rech P, Paccagnella A, Grosso M, Sonza Reorda M, Melchiori F, Appello D
    European Conference on Radiation and Its Effects on Components and Systems (RADECS), 2009, pp. 481-488

  79. Exploiting Embedded FPGA in On-line Software-based Test Strategies for Microprocessor Cores
    Grosso M.; Sonza Reorda M
    15th IEEE International On-Line Testing Symposium, 2009, pp. 95-100

  80. Gene expression reliability estimation through cluster-based analysis
    Sterpone L.; Benso A; Di Carlo. S; Politano G
    proceedings of Medical Measurement and Applications 2009, 2009, pp. 229-231

  81. Improving Preamble Sampling Performance in Wireless Sensor Networks with State Information
    E.R. Sanchez; C. Chaudet; M. Rebaudengo
    The Sixth International Conference on Wireless On-demand Network Systems and Services, 2009

  82. Introducing Probability in RFID Reader-to-Reader Anti-collision
    F. Gandino; R. Ferrero; B. Montrucchio; M. Rebaudengo
    The 8th IEEE International Symposium on Network Computing and Applications (IEEE NCA09), 2009

  83. On the Generation of Functional Test Programs for the Cache Replacement Logic
    W.J. Perez H; Ravotto D.; E. Sanchez; M. Sonza Reorda; A. Tonda
    Asian Test Symposium, ATS'09, 2009, pp. 418-423

  84. Random Key Pre-Distribution with Transitory Master Key for Wireless Sensor Networks
    F. Gandino; B. Montrucchio; M. Rebaudengo
    CoNEXT Student Workshop'09, 2009

  85. Recovery scheme for hardening system on programmable chips
    Meinhardt C; Reis R; Violante M; Sonza Reorda M.
    10th IEEE Latin American Test Workshop (LATW '09), 2009, pp. 1-6

  86. Soft Errors in Flash-based FPGAs: Analysis Methodologies and First Results
    N. Battezzati; F. Decuzzi; Sterpone L.; M. Violante
    proceedings of IEEE International Conference on Field Programmable Logic and Applications, 2009, pp. 723-724

  87. Timing driven placement for fault tolerant circuits implemented on SRAM-based FPGAs
    Sterpone L.
    Lecture notes in Computer Science, 2009, pp. 85-96

  88. A Graph-Based Representation of Gene Expression Profiles in DNA Microarrays
    Benso A; Di Carlo S.; Politano G; Sterpone L
    Computational Intelligence in Bioinformatics and Bioengineering, 2008, pp. 75-82

  89. A Hybrid Approach to the Test of Cache Memory Controllers Embedded in SoCs
    Perez W. J; Velasco-Medina J; Ravotto D; Sanchez E.; Sonza Reorda M
    Proceedings of the 2008 14th IEEE International On-Line Testing Symposium, 2008, pp. 143-148

  90. A Novel Design Flow for the Performance Optimization of Fault Tolerant Circuits on SRAM-based FPGAs
    L. Sterpone; Battezzati N.
    NASA/ESA Conference on Adaptive Hardware and Systems, 2008. AHS '08, 2008, pp. 157-163

  91. A new Placement Algorithm for the Optimization of Fault Tolerant Circuits on Reconfigurable Devices
    Battezzati N.; L. Sterpone; M. Violante
    Proceedings of the 2008 workshop on Radiation effects and fault tolerance in nanometer technologies, 2008, pp. 347-352

  92. A new low-cost non intrusive platform for injecting soft errors in SRAM-based FPGAs
    Battezzati N; Sterpone L.; Violante M
    ISIE2008, 2008, pp. 2282-2287

  93. A novel SBST generation technique for path-delay faults in microprocessors based on BDD analysis and evolutionary algorithm
    Christou K; Michael M. K; Bernardi P; Grosso M.; Sanchez E; Sonza Reorda M
    26th IEEE VLSI Test Symposium, 2008, pp. 389-394

  94. A novel methodology for diversity preservation in evolutionary algorithms
    Squillero G.; A. Tonda
    roceedings of the 2008 GECCO conference companion on Genetic and evolutionary computation, 2008, pp. 2223-2226

  95. AN EFFICIENT METHODOLOGY FOR REDUCING SoC TEST DATA VOLUME ON LOW-COST TESTERS
    P Bernardi; Sonza Reorda M.
    Design, Automation and Test in Europe (DATE2008), 2008, pp. 194-199

  96. An Anti-Counterfeit Mechanism for the Application Layer in Low-Cost RFID Devices
    P. Bernardi; F. Gandino; F. Lamberti; B. Montrucchio; M. Rebaudengo; E.R. Sanchez
    4th European Conference on Circuits and Systems for Communications, 2008, pp. 227-231

  97. An Automatic Functional Stress Pattern Generation Technique Suitable for SoC Reliability Characterization
    Appello D; Bernardi P; Bruno M; Cagliesi R; Giancarlini M; Grosso M; Sanchez E.; Sonza Reorda M
    2nd IEEE International Workshop on Automated Test Equipment: Vision ATE 2020, 2008

  98. An Evolutionary Methodology for Test Generation for Peripheral Cores Via Dynamic FSM Extraction
    Ravotto D; Sanchez E.; Schillaci M; Squillero G
    Lecture notes in Computer Science, 2008, pp. 214-223

  99. An Innovative and Low-Cost Industrial Flow for Reliability Characterization of SoCs
    Appello D; Bernardi P; Cagliesi R; Giancarlini M; Grosso M.
    13th IEEE European Test Symposium, 2008, 2008, pp. 140-145

  100. An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers
    Bernardi P.; M. Sonza Reorda
    ???, 2008

  101. Differential Gene Expression Graphs: a data structure for feature selection, clustering and classification in DNA Microarrays
    A. Benso; S. Di Carlo; G. Politano; Sterpone L.
    8th International Conference on Bioinformatics and Bioengineering, 2008, pp. 1-6

  102. Experimental Validation of Lockstep, Checkpoint, and Rollback Recovery to Detect and Correct Soft Errors in System-On-Programmable-Chips
    Abate F.; Sterpone L; Violante M
    Radiation Effects on Components and Systems, 2008

  103. Exploiting MOEA to Automatically Generate Test Programs for Path-delay Faults in Microprocessors
    Bernardi P; Christou K; Grosso M.; Michael M; Sanchez E; Sonza Reorda M
    Lecture notes in Computer Science, 2008, pp. 224-234

  104. On Automatic Test Block Generation for Peripheral Testing in SoCs via Dynamic FSMs Extraction
    Ravotto D.; Sanchez E; Schillaci M; Sonza Reorda M; Squillero G
    Microprocessor Test and Verification, 2007. MTV '07, 2008, pp. 71-76

  105. On the Static Cross Section of SRAM-Based FPGAs
    A. Manuzzato; S. Gerardin; A. Paccagnella; Sterpone L.; M. Violante
    IEEE Radiation Effects Data Workshop, 2008, pp. 94-97

  106. On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications
    Sterpone L.; Aguirre M; Tombs J; Guzman H
    IEEE Design, Automation and Test in Europe, 2008, pp. 336-341

  107. On the evaluation of radiation-induced transient faults in Flash-based FPGAs
    Battezzati N; Gerardin S; Manuzzato A; Paccagnella A; Rezgui S; Sterpone L.; Violante M
    14th IEEE International On-Line Testing Symposium, 2008, pp. 135-140

  108. On the generation of test programs for chip multithread computer architectures
    D. Ravotto; E. Sanchez; Sonza Reorda M.; G. Squillero
    IEEE International Test Conference (ITC), 2008, pp. P6.4-P6.4

  109. RFID for agri-food traceability: methods for authentication, integrity and privacy
    C. Demartini; F. Gandino; B. Montrucchio; M. Rebaudengo; E.R. Sanchez
    Workshop on Emerging Technologies for Radio-frequency Identification, 2008, pp. 87-93

  110. SoC Symbolic Simulation: a case study on delay fault testing
    Bosio; A; Girard P; Pravossoudovich S; Bernardi P.
    ???, 2008

  111. Software-Based Self-Test Strategy for Data Cache Memories Embedded in SoCs
    Perez W. J; Velasco Medina J; Ravotto D; Sanchez E.; Sonza Reorda M
    The IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, 2008, pp. 339-344

  112. A Hybrid Approach to Fault Detection and Correction in SoCs
    P. Bernardi; L. Bolzani; Sonza Reorda M.
    IOLTS2007: IEEE International On-Line Testing Symposium, 2007, pp. 107-112

  113. A Software-based Methodology for the Generation of Peripheral Test Sets Based on High-level Descriptions
    Bolzani L; Sanchez E.; Sonza Reorda M
    Proceedings of the 20th annual conference on Integrated circuits and systems design, 2007, pp. 348-353

  114. A local analysis of an incremental evolutionary tool for processor diagnosis
    D. Ravotto; E. Sanchez; M. Schillaci; Squillero G.
    CEC 2007, 2007, pp. 3467-3473

  115. A new FPGA-based edge detection system for the gridding of DNA microarray images
    Sterpone L.; M. Violante
    IEEE Instrumentation and Measurement Technology Conference, 2007

  116. A new decompression system for the configuration process of SRAM-based FPGAs
    Sterpone L.; M. Violante
    ACM 17th Great Lake Symposium on VLSI, 2007

  117. A new hardware architecture for performing the gridding of DNA microarray images
    Sterpone L.; M. Violante
    ACM 17th Great Lake Symposium on VLSI, 2007

  118. A new hardware/software platform for the soft-error sensitivity evaluation of FPGA devices
    Violante M., Sonza Reorda M., Sterpone L., Manuzzato A., Gerardin S., Rech P., Bagatin M., Paccagnella A., Andreani C., Gorini G., Pietropaolo A., Cardarilli G., Salsano A., Pontarelli S., Frost C.
    8th IEEE Latin American Test Workshop, 2007, pp. 1-6

  119. Agri-Food Traceability Management using a RFID System with Privacy Protection
    Bernardi P; Demartini C; Gandino F; Montrucchio B.; Rebaudengo M; Sanchez E.R
    The IEEE 21st International Conference on Advanced Information Networking and Applications (AINA-07), 2007, pp. 68-75

  120. An Analysis of SEU Effects in Embedded Operating Systems for Real-Time Applications
    Sterpone L; Violante M.
    International Symposium on Industrial Electronics, 2007, pp. 3345-3349

  121. An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores
    L. Bolzani; E. Sanchez; Schillaci M.; M. Sonza Reorda; G. Squillero
    IOLTS2007: IEEE International On-Line Testing Symposium, 2007, pp. 265-270

  122. An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains
    Lagos-Benites J; Appello D; Bernardi P; Grosso M; Ravotto D; Sanchez E.; Sonza Reorda M
    DFT2007, 22th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2007, pp. 291-299

  123. An Enhanced Technique for the Automatic Generation of Effective Diagnosis-oriented Test Programs for Processors
    Sanchez E; Schillaci M; Sonza Reorda M; Squillero G.
    DATE2007: Design, Automation and Test in Europe, 2007, pp. 1-6

  124. An Extensible Evolutionary-based General-purpose Optimizer
    E. Sanchez; Schillaci M.; G. Squillero
    IOST3, IEEE International Workshop on Open Source Test Technology Tools, 2007

  125. An experimental analysis of SEU sensitiveness of recursive-oriented hardening techniques
    Sterpone L.; P. Reyes Moreno; J.A. Maestro; O. Ruano; P. Reviriego
    DDECS2007: IEEE Design & Diagnostic of Electronic Circuits & Systems, 2007, 2007

  126. An optimized hybrid approach to provide fault detection and correction in SoCs
    L. Bolzani; P. Bernardi; Sonza Reorda M.
    SBCCI2007: IEEE 20th SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, 2007, pp. 342-347

  127. Analysis of an RFID-based Information System for Tracking and Tracing in an Agri-Food chain
    F. Gandino; B. Montrucchio; Rebaudengo M.; E.R. Sanchez Sanchez
    IEEE RFID Eurasia Conference, 2007, pp. 143-148

  128. Automotive Microcontroller End-of-Line Test via Software-Based Methodologies
    Di Palma W; Ravotto D; Sanchez E.; Schillaci M; Sonza Reorda M; Squillero G
    Eighth International Workshop on Microprocessor Test and Verification, 2007. MTV '07., 2007, pp. 77-82

  129. Co-evolution of Test Programs and Stimuli Vectors for Testing of Embedded Peripheral Cores
    Bolzani L; Sanchez E.; Schillaci M; Squillero G
    CEC 2007, IEEE Congress on Evolutionary Computation, 2007, pp. 3474-3481

  130. Coupling EA and High-Level Metrics for the Automatic Generation of Test Blocks for Peripheral Cores
    L. Bolzani; E. Sanchez; M. Schillaci; Squillero G.
    GECCO'07, 2007, pp. 1912-1919

  131. Design of an UHF RFID Transponder for Secure Authentication
    Bernardi P; Gandino F; Montrucchio B.; Rebaudengo M; Sanchez E.R
    GLSVLSI 2007, 2007

  132. Extended Fault Detection Techniques for Systems-on-Chip
    P. Bernardi; L. Bolzani; Sonza Reorda M.
    DDECS2007: IEEE Design & Diagnostic of Electronic Circuits & Systems, 2007, pp. 55-60

  133. Hardware-Accelerated Path-Delay Fault Grading of Functional Test Programs for Processor-based Systems
    Bernardi P; Grosso M.; Sonza Reorda M
    Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, 2007, pp. 411-416

  134. Increasing Effective Radiated Power in Wireless Sensor Networks with Channel Coding Techniques
    Sanchez E.R; Gandino F; Montrucchio B; Rebaudengo M.
    IEEE International Conference on Electromagnetics in Advanced Applications, ICEAA '07, 2007

  135. On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores
    Bernardi P; Grosso M.; Sanchez E; Sonza Reorda M
    European Test Symposium, 2007. ETS '07. 12th IEEE, 2007, pp. 179-184

  136. Optimization of Self Checking FIR filters by means of Fault Injection Analysis
    S. Pontarelli; Sterpone L.; G.C. Cardarilli; M. Re; M. Sonza Reorda; A. Salsano; M. Violante
    22th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2007, pp. 96-104

  137. Safety Evaluation of NanoFabrics
    Grosso M.; Rebaudengo M; Sonza Reorda M
    22th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2007, 2007, pp. 418-426

  138. Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders
    S. Pontarelli; L. Sterpone; G.C. Cardarilli; M. Re; Sonza Reorda M.; A. Salsano; M. Violante
    IOLTS2007: IEEE International On-Line Testing Symposium, 2007, pp. 194-196

  139. Sensitivity evaluation of TMR-hardened circuits to multiple SEUs induced by alpha particles in commercial SRAM-based FPGAs
    Manuzzato A; Rech P; Gerardin S; Paccagnella A; Sterpone L; Violante M.
    International Symposium on Defect and Fault Tolerance in VLSI Systems, 2007, pp. 79-86

  140. Static and Dynamic Analysis of SEU effects in SRAM-based FPGAs
    Sterpone L.; M. Violante
    ETS2007: IEEE European Test Symposium, Freiburg, Germany, 2007, 2007

  141. µGP an evolutionary test program generator
    G. Squillero; Schillaci M.; E. Sanchez
    IOST3, IEEE International Workshop on Open Source Test Technology Tools, 2006

  142. A Fault Injection Environment for SoPC's Embedded Microprocessors
    M. Portela-Garcia; Sterpone L.; C. Lopez-Ongil; M. Sonza Reorda; M. Violante
    7th IEEE Latin-American Test Workshop, Buenos Aires, Argentina, 2006, pp. 68-73

  143. A new approach to compress the configuration information of programmable devices
    Martina M.; G. Masera; A. Molino; F. Vacca; L. Sterpone; M. Violante
    DATE, 2006, pp. 1289-1293

  144. A pattern ordering algorithm for reducing the size of fault dictionaries
    Bernardi P; Grosso M.; Rebaudengo M; Sonza Reorda M
    VLSI Test Symposium, 2006. Proceedings. 24th IEEE, 2006, pp. 166-171

  145. A survey of µGP
    Sanchez E.; Schillaci M
    SIGEvolution, newsletter of the ACM Special Interest Group on Genetic and Evolutionary Computation, 2006, pp. 17-21

  146. An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs
    Bernardi P; Sanchez E.; Schillaci M; Squillero G; Sonza Reorda M
    Proceedings of the conference on Design, automation and test in Europe, 2006, pp. 412-417

  147. An Evolutionary Methodology to Enhance Processor Software-Based Diagnosis
    P. Bernardi; E. Sanchez; Schillaci M.; M. Sonza Reorda; G. Squillero
    CEC 2006, IEEE Congress on Evolutionary Computation, 2006, pp. 859-864

  148. An Experimental Analysis of a New Mixed Grain-Based Dynamically Reconfigurable Architecture
    Sterpone L.
    13th IEEE International Conference on Electronics, Circuits and Systems, 2006, pp. 152-155

  149. Anatomy of an extensible evolutionary tool
    E. Sanchez; Schillaci M.; G. Squillero
    GSICE06: Giornata di Studio Italiana sul Calcolo Evolutivo, 2006

  150. Combined software and hardware techniques for the design of reliable IP processors
    M. Rebaudengo; Sterpone L.; M. Violante; C. Bolchini; A. Miele; D. Sciuto
    21th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2006, pp. 265-273

  151. Dependability Evaluation of Transient Fault Effects in Reconfigurable Compute Fabric Devices
    L. Sterpone; Violante M.
    International On-Line Testing Symposium, 2006, pp. 189-190

  152. Embedded Memories Diagnosis: An Industrial Workflow
    Appello D; Bernardi P; Grosso M.; Rebaudengo M; Sonza Reorda M; Tancorre V
    IEEE International Test Conference, 2006, pp. 1-9

  153. Enhanced Test Program Compaction Using Genetic Programming
    E. Sanchez; Schillaci M.; G. Squillero
    CEC 2006, IEEE Congress on Evolutionary Computation, 2006, pp. 865-870

  154. Evolving Warriors for the Nano Core
    E. Sanchez; Schillaci M.; G. Squillero
    CIG 2006, IEEE Symposium on Computational Intelligence and Games, 2006, pp. 272-278

  155. Fault Injection-based Reliability Evaluation of SoPCs
    M. Sonza Reorda; L. Sterpone; Violante M.; M. Portela-Garcia; C. Lopez-Ongil; L. Entrena
    IEEE European Test Symposium, 2006, pp. 75-82

  156. Hardware-in-the-Loop-Based Dependability Analysis of Automotive Systems
    M. Sonza Reorda; Violante M.
    International On-Line Testing SYmposium, 2006, pp. 229-234

  157. Laboratorios en casa: Una Nueva Alternativa Para Cursos Masivos de Diseño Lógico Digital
    Oliver J.P., Haim F., Fernández S., Rodríguez J., Ciganda L., Rolando, P.
    VII Congreso de Tecnologías Aplicadas a la Enseñanza de la Electrónica, 2006

  158. Laboratory at Home: Actual Circuit Design and Testing Experiences in Massive Digital Design Courses
    Haim F., Fernández S., Rodríguez J., Ciganda L., Rolando P., Oliver J.P.
    9th International Conference on Engineering Education, 2006, pp. 5-9

  159. On the automation of the test flow of complex SoCs
    D. Appello; P. Bernardi; Grosso M.; M. Rebaudengo; M. Sonza Reorda; V. Tancorre
    VLSI Test Symposium, 2006. Proceedings. 24th IEEE, 2006, pp. 386-391

  160. Online hardening of programs against SEUs and SETs
    Lisboa C.A.L; Carro L; Reorda M.S; Violante M.
    IEEE Symposium on Defect and Fault Tolerance in VLSI Systems, 2006, pp. 280-290

  161. ReCoM: A new Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications
    L. Sterpone; Violante M.
    IEEE Workshop Design and Diagnostic of Electronic circuits and systems, 2006, pp. 54-58

  162. Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications
    Bernardi P.; L. Bolzani; M. Violante; M. Sonza Reorda; A. Manzone; M. Ossela
    ???, 2006

  163. Test Considerations about the Structured ASIC Paradigm
    Bernardi P; Grosso M.
    Design and Diagnostics of Electronic Circuits and systems, 2006 IEEE, 2006, pp. 230-231

  164. A Tool for Supporting and Automating the Test of Complex System-on-Chips
    P. Bernardi; M. Grosso; Rebaudengo M.; M. Sonza Reorda; D. Appello; R. Mattiuzzo; V. Tancorre
    ITSW 2005: IEEE International Test Synthesis Workshop, 2005

  165. A design flow for protecting FPGA-based systems against single event upsets
    L. Sterpone; Violante M.
    IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2005, pp. 436-444

  166. A modular Architecture for a Populationless Evolutionary Algorithm for MIP
    E. Sanchez; Schillaci M.; G. Squillero
    GSICE05: Giornata di Studio Italiana sul Calcolo Evolutivo, 2005

  167. A new DFM-proactive technique
    D. Appello; P. Bernardi; M. Grosso; Rebaudengo M.; M. Sonza Reorda; V. Tancorre
    SDD'05: 2nd IEEE International Workshop on Silicon Debug and Diagnosis, 2005

  168. An I-IP for the Debug of Microprocessor Cores
    D. Appello; M. Grosso; Rebaudengo M.; M. Sonza Reorda
    DCIS05: XX Conference on Design of Circuits and Integrated Systems, 2005

  169. An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors
    P. Bernardi; L. Bolzani; M. Rebaudengo; M. Sonza Reorda; Violante M.
    IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2005, pp. 307-312

  170. An experimental analysis of hardening techniques for SRAM-based FPGAs
    Sterpone L.; M. Violante; S. Rezgui
    8th IEEE European Conference on Radiation and Its Effects on Component and Systems, 2005, pp. J5-1-J5-4

  171. Automatic Completion and Refinement of Verification Sets for Microprocessor Cores
    Sanchez E.; Squillero G; Sonza Reorda M
    Lecture notes in Computer Science, 2005, pp. 205-214

  172. Automatic Generation of Test Sets for SBST of Microprocessor IP Cores
    Sanchez E.; Sonza Reorda M; Squillero G; Violante M
    18th Symposium on Integrated Circuits and Systems Design, SBCCI, 2005, pp. 74-79

  173. Diagnosing faulty functional units in processors by using automatically generated test sets
    Bernardi P.; E. Sanchez; M. Schillaci; M. Sonza Reorda; G. Squillero
    ???, 2005

  174. Efficient estimation of SEU effects in SRAM-based FPGAs
    M. Sonza Reorda; Sterpone L.; M. Violante
    IEEE International On-Line Testing Symposium, 2005, pp. 54-59

  175. Exploiting an I-IP for both test and silicon debug of microprocessor cores
    Bernardi P; Grosso M.; Rebaudengo M; Sonza Reorda M
    Microprocessor Test and Verification, 2005. MTV '05. Sixth International Workshop on, 2005, pp. 55-62

  176. Exploiting an Infrastructure-IP to reduce memory diagnosis costs in SoCs
    Bernardi P; Grosso M.; Rebaudengo M; Sonza Reorda M
    Test Symposium, 2005. European, 2005, pp. 202-207

  177. Improved Software-Based Processor Control-Flow Errors Detection Technique
    O. Goloubeva; M. Rebaudengo; M. Sonza Reorda; Violante M.
    The Annual Reliability and Maintainability Symposium, 2005, pp. 583-589

  178. Integrating BIST techniques for on-line SoC testing
    Bernardi P; Grosso M.; Manzone A; Rebaudengo M; Sanchez E; Sonza Reorda M
    On-Line Testing Symposium, 2005. IOLTS 2005. 11th IEEE International, 2005, pp. 235-240

  179. Multiple errors produced by single upsets in FPGA configuration memory: a possible solution
    M. Sonza Reorda; Sterpone L.; M. Violante
    IEEE European Test Symposium, 2005, pp. 136-141

  180. New Evolutionary Techniques for Test-Program Generation for Complex Microprocessor Cores
    E. Sanchez; M. Schillaci; M. Sonza Reorda; Squillero G.; L. Sterpone; M. Violante
    Proceedings of the 2005 conference on Genetic and evolutionary computation, 2005, pp. 2193-2194

  181. On the diagnosis of SoCs including multiple memory cores
    Bernardi P; Grosso M.; Rebaudengo M; Sonza Reorda M
    Design and Diagnostics of Electronic Circuits and Systems. IEEE Workshop on, 2005, pp. 75-80

  182. On the optimal design of triple modular redundancy logic for SRAM-based FPGAs
    F. Kastensmidt; Sterpone L.; M. Sonza Reorda; L. Carro
    IEEE Design, Automation and Test in Europe, 2005, pp. 1290-1295

  183. On the transformation of manufacturing test sets into on-line test sets for microprocessors
    Sanchez E; Reorda M.S; Squillero G.
    roceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005, pp. 494-502

  184. On-line Detection of Control-Flow Errors in SoCs by means of an Infrastructure IP core
    P. Bernardi; L. Bolzani; M. Rebaudengo; M. Sonza Reorda; F. Vargas; Violante M.
    IEEE Dependable Systems and Networks Symposium, 2005, pp. 50-58

  185. RoRA: a reliability-oriented place and route algorithm for SRAM-based FPGAs
    L. Sterpone; M. Sonza Reorda; Violante M.
    Research in Microelectronics and Electronics, 2005, pp. 173-176

  186. Testing logic cores using a BIST P1500 compliant approach: a case of study
    P. Bernardi; G. Masera; Quaglio F.; M. Sonza Reorda
    Proceedings of DATE2005, 2005, pp. 228-233

  187. A Local Analysis of the Genotype-Fitness Mapping in Hardware Optimization Problems
    E. Sanchez; G. Squillero; Violante M.
    Congress on Evolutionary Computation, 2004, pp. 871-878

  188. A multi-level approach to the dependability analysis of networked systems based on the CAN protocol
    Corno F.; J. Perez; M. Sonza Reorda; M. Violante
    SBCCI04: IEEE Symposium on Integrated Circuits and Systems Design, 2004

  189. An Infrastructure IP for Soft Error Detection
    L. Bolzani; Rebaudengo M.; M. Sonza Reorda; F. Vargas; M. Violante
    LATW'04: IEEE Latin-American Test WorkShop, 2004

  190. Approaching production diagnostic for BIST-based testing
    D. Appello; P. Bernardi; D. Chindamo; Rebaudengo M.; M. Sonza Reorda; V. Tancorre
    SDD'04: 1st IEEE International Workshop on Silicon Debug and Diagnosis, 2004

  191. Automatic Generation of Validation Stimuli for Application-Specific Processors
    O. Goloubeva; M. Sonza Reorda; Violante M.
    DATE2004: Design, Automation and Test in Europe, 2004, pp. 188-193

  192. Automatic Test Programs Generation Driven by Internal Performance Counters
    W. Lindsay; E. Sanchez; M. Sonza Reorda; Squillero G.
    Proceedings of the Fifth International Workshop on Microprocessor Test and Verification, 2004, pp. 8-13

  193. Automatic Verification of RT-Level Microprocessor Cores Using Behavioral Specifications: a Case Study
    L. Anghel; E. Sanchez; M. Sonza Reorda; Squillero G.; R. Velazco
    Conference on Design of Circuits and Integrated Systems, 2004

  194. Coupling different methodologies to validate obsolete microprocessors
    L. Anghel; E. Sanchez; M. Sonza Reorda; Squillero G.; R. Velazco
    Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium on (DFT'04), 2004, pp. 250-255

  195. Dynamic Optimization of Semantic Annotation Relevance
    Bonino D.; Corno F; Squillero G
    Proceedings of CEC2004, Congress on Evolutionary Computation, 2004, pp. 1301-1308

  196. Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA
    M. Bellato; Bernardi P.; D. Bortolato; A. Candelori; M. Ceschia; A. Paccagnella; M. Rebaudengo; M. Sonza Reorda; M. Violante; P. Zambolin
    ???, 2004

  197. Evaluating the effects of transient faults on vehicle dynamic performance in automotive systems
    F. Corno; F. Esposito; Sonza Reorda M.; S. Tosato
    IEEE International Test Conference, 2004, pp. 1332-1339

  198. Exploiting HW Acceleration for Classifying Complex Test Program Generation Problems
    E. Sanchez; Squillero G.; M. Violante
    Lecture notes in Computer Science, 2004, pp. 230-239

  199. Exploiting an I-IP for In-field SOC test
    Bernardi P.; M. Rebaudengo; M. Sonza Reorda
    ???, 2004

  200. Hybrid Soft Error Detection by means of Infrastructure IP cores
    L. Bolzani; M. Rebaudengo; M. Sonza Reorda; F.L. Vargas; M. Violante
    10th IEEE International On-Line Test Symposium - IOLTS'04, 2004

  201. On the diagnosis of embedded memory cores through Programmable BIST
    D. Appello; P. Bernardi; Rebaudengo M.; M. Sonza Reorda; V. Tancorre
    TRP'04: 5th IEEE International Workshop on Test Resource Partitioning, 2004

  202. On the evaluation of SEU sensitiveness in SRAM-based FPGAs
    P. Bernardi; M. Sonza Reorda; L. Sterpone; Violante M.
    IEEE International On-Line Testing Symposium, 2004, pp. 115-120

  203. On the evolution of corewar warriors
    F. Corno; E. Sanchez; Squillero G.
    Congress on Evolutionary Computation, 2004, pp. 2365-2371

  204. On-line Analysis and Perturbation of CAN Networks
    M. Sonza Reorda; Violante M.
    IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004, pp. 424-432

  205. Using Infrastructure IPs to support SW-based Self-Test of Processor Cores
    P. Bernardi; Rebaudengo M.; M. Sonza Reorda
    MTV'04: 5th International Workshop on Microprocessor Test and Verification, 2004, pp. 22-27

  206. Validation of the dependability of CAN-based networked systems
    F. Corno; J. Perez; M. Ramasso; M. Sonza Reorda; Violante M.
    IEEE High-level Design Validation and Test Workshop, 2004, pp. 161-164

  207. A P1500 compatible microprocessor-based approach for the test of Embedded Flash Memories
    P. Bernardi; M. Rebaudengo; M. Sonza Reorda; Violante M.
    Design, Automation and Test in Europe, 2003, pp. 720-725

  208. A new Software-based technique for low-cost Fault-Tolerant application
    Rebaudengo M.; M. Sonza Reorda; M. Violante
    RAMS2003: The Annual Reliability and Maintainability Symposium, 2003, pp. 25-28

  209. A programmable BIST approach for the diagnosis of embedded memory cores
    D. Appello; P. Bernardi; A. Fudoli; Rebaudengo M.; M. Sonza Reorda; V. Tancorre; M. Violante
    ETW03: 8th IEEE European Test Workshop (, 2003, pp. 101-102

  210. A real-time evolutionary algorithm for Web prediction
    D. Bonino; F. Corno; Squillero G.
    Proceedings of the IEEE/WIC International Conference on Web Intelligence, 2003, pp. 139-145

  211. Accurate Dependability Analysis of CAN-based Networked Systems
    J. Perez; M. Sonza Reorda; Violante M.
    IEEE Symposium on Integrated Circuits and Systems Design, 2003, pp. 337-342

  212. Accurate and Efficient Analysis of Single Event Transients in VLSI Circuits
    Violante M.; M. Sonza Reorda
    IEEE International On-Line Testing Symposium, 2003, pp. 101-105

  213. An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor
    Rebaudengo M.; M. Sonza Reorda; M. Violante
    DATE2003: Design, Automation and Test in Europe, 2003, pp. 602-607

  214. An Enhanced Framework for Microprocessor Test-Program Generation
    F. Corno; Squillero G.
    Lecture notes in Computer Science, 2003, pp. 307-315

  215. An Evolutionary Approach to Web Request Prediction
    Bonino D.; Corno F.; Squillero G.
    WWW2003 - The 12th Intl World Wide Web Conference, Budapest, HU, 2003

  216. An efficient algorithm for the extraction of compressed diagnostic information from embedded memory cores
    P. Bernardi; Rebaudengo M.; M. Sonza Reorda
    ETFA 2003: 9th IEEE International Conference on Emerging Technologies and Factory Automation, 2003, pp. 417-421

  217. Analyzing SEU Effects in SRAM-based FPGAs
    M. Violante; M. Ceschia; M. Sonza Reorda; A. Paccagnella; P. Bernardi; Rebaudengo M.; D. Bortolato; M. Bellato; P. Zambolin; And A. Candelori
    IOLTS2003: IEEE International On-Line Testing Symposium, 2003, pp. 119-123

  218. Automatic Test Program Generation for Pipelined Processors
    F. Corno; M. Sonza Reorda; Squillero G.
    Proceedings of the 2003 ACM symposium on Applied computing, 2003, pp. 736-740

  219. Code generation for functional validation of pipelined microprocessors
    F. Corno; Squillero G.; M. Sonza Reorda
    Proceedings of the 8th IEEE European Test Workshop, 2003, pp. 113-118

  220. Dependability Analysis of CAN Networks: an emulation-based approach
    J. Perez; M. Sonza Reorda; Violante M.
    IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2003, pp. 537-544

  221. Detailed comparison of dependability analyses performed at RT and gate levels
    A. Ammari; R. Leveugle; M. Sonza Reorda; Violante M.
    IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2003, pp. 336-343

  222. Dynamic Prediction of Web Requests
    Corno F; Bonino D.; Squillero G
    CEC03: 2003 IEEE Congress on Evolutionary Computation, 2003, pp. 2034-2041

  223. Emulation-based Analysis of Soft Errors in Deep Sub-micron Circuits
    M. Sonza Reorda; Violante M.
    International Conference on Field Programmable Logic and Application, 2003, pp. 616-626

  224. Exploiting Auto-Adaptive microGP for Highly Effective Test Programs Generation
    F. Corno; Squillero G.
    Lecture notes in Computer Science, 2003, pp. 262-273

  225. Exploiting co-evolution and a modified island model to climb the Core War hill
    F. Corno; E. Sanchez; Squillero G.
    Congress on Evolutionary Computation, 2003, pp. 2217-2221

  226. Exploiting programmable BIST for the diagnosis of embedded memory cores
    D. Appello; P. Bernardi; A. Fudoli; Rebaudengo M.; M. Sonza Reorda; V. Tancorre; M. Violante
    ITC2003: IEEE International Test Conference, 2003, pp. 379-385

  227. Fully automatic test program generation for microprocessor cores
    F. Corno; G. Cumani; M. Sonza Reorda; Squillero G.
    Proceedings of the conference on Design, Automation and Test in Europe - Volume 1, 2003, pp. 1006-1011

  228. High-level test generation for hardware testing and software validation
    O. Goloubeva; M. Sonza Reorda; Violante M.
    IEEE International Workshop on High Level Design Validation and Test, 2003, pp. 143-148

  229. Soft-error Detection Using Control Flow Assertions
    O. Goloubeva; Rebaudengo M.; M. Sonza Reorda; M. Violante
    DFT2003: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2003, pp. 581-588

  230. A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques
    D. Appello; A. Fudoli; V. Tancorre; F. Corno; Rebaudengo M.; M. Sonza Reorda
    IOLTW2002: IEEE International On-line Testing Workshop, 2002, pp. 112-116

  231. A Hierarchical Approach for Designing Dependable Systems
    M. Sonza Reorda; Violante M.; N. Mazzocca; S. Venticinque; A. Bobbio; G. Franceschinis
    IEEE International Workshop on High Level Design Validation and Test, 2002, pp. 63-67

  232. A New Methodology for Debugging Embedded Cores
    D. Appello; L. Bouzaida; A. Fudoli; R. Mattiuzzo; R. Kapur; Rebaudengo M.; M. Sonza Reorda
    TRP2002: Test Resource Partitioning Workshop 2002, 2002

  233. A Software Fault Tolerance Method for Safety-Critical Systems: Effectiveness and Drawbacks
    B. Nicolescu; R. Velazco; M. Sonza Reorda; Rebaudengo M.; M. Violante
    SBCCI: 15th IEEE Symposium on Integrated Circuits and Systems Design, 2002, pp. 101-106

  234. A Transparent Search Agent for Closed Collections
    Bota F; Corno F; Farinetti L; Squillero G.
    SSGRR-2002w: International Conference on Advances in Infrastructure for e-Business, e-Education, e-S, 2002

  235. A new approach to software-implemented fault tolerance
    Rebaudengo M.; M. Sonza Reorda; M. Violante
    LATW2002: IEEE Latin American Test Workshop, 2002

  236. A new functional fault model for FPGA Application-Oriented testing
    Rebaudengo M.; M. Sonza Reorda; M. Violante
    DFT2002: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002, pp. 372-380

  237. An Evolutionary Algorithm for Reducing Integrated-Circuit Test Application Time
    Corno F; Sonza Reorda M; Squillero G.
    Proceedings of the 2002 ACM symposium on Applied computing, 2002, pp. 608-612

  238. An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation
    L. Berrojo; Corno F.; L. Entrena; I. Gonzlez; C. Lopez; M. Sonza Reorda; G. Squillero
    VTS2002: 20th IEEE VLSI Test Symposium, 2002

  239. Analysis of SEU effects in a pipelined processor
    Rebaudengo M.; M. Sonza Reorda; M. Violante
    IOLTW2002: IEEE International On-line Testing Workshop, 2002, pp. 206-210

  240. Analysis of the Equivalences and Dominances of Transient Faults at the Register-Transfer Level
    Errojo L; Gonzlez I; Corno F; Sonza Reorda M; Squillero G.; Entrena L; Lopez C
    Proceedings of the Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02), 2002, pp. 193-

  241. Automatic Test Program Generation from RT-level Microprocessor Descriptions
    Corno F.; G. Cumani; M. Sonza Reorda; G. Squillero
    ISQED2002: 3rd International Symposium on Quality Electronic Design, 2002

  242. Efficient Machine-Code Test-Program Induction
    Corno F; Cumani G; Sonza Reorda M; Squillero G.
    CEC2002: Congress on Evolutionary Computation, 2002, pp. 1486-1491

  243. Evolutionary Techniques for Minimizing Test Signals Application Time
    Corno F; Sonza Reorda M; Squillero G.
    Lecture notes in Computer Science, 2002, pp. 183-189

  244. Evolutionary Test Program Induction for Microprocessor Design Verification
    Corno F; Cumani G; Sonza Reorda M; Squillero G.
    Proceedings of the 11th Asian Test Symposium, 2002, pp. 368-373

  245. New Techniques for Speeding-up Fault-injection Campaigns
    Berrojo L; Gonzlez I; Corno F; Sonza Reorda M; Squillero G.; Entrena L; Lopez C
    Proceedings of the conference on Design, automation and test in Europe, 2002, pp. 847-852

  246. Reducing Test Application Time through Interleaved Scan
    Corno F; Sonza Reorda M; Squillero G.
    Proceedings of the 15th symposium on Integrated circuits and systems design, 2002, pp. 89-94

  247. Simulation-based analysis of SEU effects on SRAM-based FPGAs
    Rebaudengo M., Sonza Reorda M., Violante M.
    Lecture notes in Computer Science, 2002, pp. 101-116

  248. Simulation-based analysis of SEU effects on SRAM-based FPGAs
    Rebaudengo M.; M. Sonza Reorda; M. Violante
    FPL2002: International Conference on Field Programmable Logic and Application, 2002, pp. 607-615

  249. A P1500 compliant BIST-based approach to embedded RAM diagnosis
    D. Appello; F. Corno; M. Giovinetto; Rebaudengo M.; M. Sonza Reorda
    ATS, IEEE Asian Test Symposium, 2001, pp. 97-102

  250. A source-to-source compiler for generating dependable software
    Rebaudengo M.; M. Sonza Reorda; M. Torchiano; M. Violante
    SCAM, IEEE International Workshop on Source Code Analysis and Manipulation, 2001, pp. 33-42

  251. ARPIA: a High-Level Evolutionary Test Signal Generator
    Corno F; Cumani G; Sonza Reorda M; Squillero G.
    Lecture notes in Computer Science, 2001, pp. 298-306

  252. An Interpretation Framework for Evaluating High-Level Fault Models and ATPG Capabilities
    Corno F; Sonza Reorda M; Squillero G.
    DCIS2001: Design of Circuits and Integrated Systems, 2001, pp. 273-278

  253. Devising an RT-Level ATPG for uProcessor Cores
    Corno F; Cumani G; Sonza Reorda M; Squillero G.
    WRTLT2001: 2nd Worshop on RTL, ATPG & DFT, 2001

  254. Effective Techniques for High-Level ATPG
    Corno F; Cumani G; Sonza Reorda M; Squillero G.
    Proceedings of the 10th Asian Test Symposium, 2001, pp. 225-230

  255. Evolving Effective CA/CSTP BIST Architectures for Sequential Circuits
    Corno F; Sonza Reorda M; Squillero G.
    Proceedings of the 2001 ACM symposium on Applied computing, 2001, pp. 345-350

  256. Exploiting FPGA for accelerating Fault Injection Experiments
    P.L. Civera; L. Macchiarulo; Rebaudengo M.; M. Sonza Reorda; M. Violante
    IOLTW, IEEE On-Line Testing Workshop, 2001, pp. 9-13

  257. Exploiting FPGA-based Techniques for Fault Injection Campaigns on VLSI Circuits
    P.L. Civera; L. Macchiarulo; Rebaudengo M.; M. Sonza Reorda; M. Violante
    DFT, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2001, pp. 250-258

  258. FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits
    Civera P., Macchiarulo L., Rebaudengo M., Sonza Reorda M., Violante M.
    Lecture notes in Computer Science, 2001, pp. 493-502

  259. FPGA-based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits
    P.L. Civera; L. Macchiarulo; Rebaudengo M.; M. Sonza Reorda; M. Violante
    FPL 2001, 11th International Conference on Field Programmable Logic and Applications, 2001, pp. 493-502

  260. FPGA-based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits
    Civera P.L., Macchiarulo L., Rebaudengo M., Sonza Reorda M., Violante M.
    Lecture notes in Computer Science, 2001, pp. 493-502

  261. FPGA-based Fault Injection for Microprocessor Systems
    P.L. Civera; L. Macchiarulo; Rebaudengo M.; M. Sonza Reorda; M. Violante
    ATS, IEEE Asian Test Symposium, 2001, pp. 304-309

  262. On the Test of Microprocessor IP Cores
    Corno F; Sonza Reorda M; Violante M; Squillero G.
    Proceedings of the conference on Design, automation and test in Europe, 2001, pp. 209-213

  263. System Safety through Automatic High-level Code Transformations: an Experimental Evaluation
    Rebaudengo M.; M. Sonza Reorda; M. Violante; P. Cheynet; B. Nicolescu; R. Velazco
    DATE: IEEE Design, Automation & Test in Europe Conference, 2001, pp. 297-301

  264. A Genetic Algorithm-based System for Generating Test Programs for Microprocessor IP Cores
    Corno F.; M. Sonza Reorda; G. Squillero; M. Violante
    ICTAI2000: The Twelfth IEEE International Conference on Tools with Artificial Intelligence, Vancouver, British Columbia, Canada, November 13-15, 2000, pp. 195-198, 2000, pp. 195-198

  265. An Improved Cellular Automata-Based BIST Architecture for Sequential Circuits
    Corno F.; M. Sonza Reorda; G. Squillero
    ISCAS2000: IEEE International Symposium on Circuits and Systems, Geneva (CH), May 2000, pp. 76-79, 2000, pp. 76-79

  266. An Intelligent User Interface oriented to non-expert users
    Corno F; Farinetti L; Squillero G.
    World Conference on the WWW and Internet, 2000, pp. 675-676

  267. An RT-level Fault Model with High Gate Level Correlation
    Corno F; Cumani G; Sonza Reorda M; Squillero G.
    Proceedings of the IEEE International High-Level Validation and Test Workshop (HLDVT'00), 2000, pp. 3-3

  268. Archivi on-line fruibili da utenti inesperti: un'esperienza nel campo della disabilità
    Corno F; Squillero G.
    Convegno AICA sull'Informatica per la Didattica, 2000, pp. 181-187

  269. Automatic Test Bench Generation for Validation of RT-level Descriptions: an Industrial Experience
    Corno F; Manzone A; Pincetti A; Sonza Reorda M; Squillero G.
    Proceedings of the conference on Design, automation and test in Europe, 2000, pp. 385-389

  270. Automatic Validation of Protocol Interfaces Described in VHDL
    Corno F; Sonza Reorda M; Squillero G.
    Lecture notes in Computer Science, 2000, pp. 205-213

  271. Automatic Validation of Protocol Interfaces Described in VHDLAutomatic Test Bench Generation for Validation of RT-level Descriptions: an Industrial Experience
    F. Corno; A. Manzone; A. Pincetti; Sonza Reorda M.; G. Squillero
    IEEE DATE2000: Design, Automation and Test in Europe, 2000, pp. 385-389

  272. CA-CSTP: A new BIST Architecture for Sequential Circuit
    Corno F; Sonza Reorda M; Squillero G.; Violante M
    Proceedings of the IEEE European Test Workshop, 2000, pp. 167-172

  273. Early Power Estimation for System-on-Chip Designs
    M. Lajolo, L. Lavagno, M. Sonza Reorda, M. Violante
    Lecture notes in Computer Science, 2000, pp. 108-117

  274. Evolving Cellular Automata for Self-Testing Hardware
    Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
    Lecture notes in Computer Science, 2000, pp. 31-40

  275. Exploiting the Selfish Gene Algorithm for Evolving Cellular Automata
    Corno F.; M. Sonza Reorda; G. Squillero
    IJCNN2000: IEEE-INNS-ENNS International Joint Conference Neural Networks, Como (I), July 2000, pp. 577-581, 2000, pp. 577-581

  276. Exploiting the Selfish Gene Algorithm for Evolving Hardware Cellular Automata
    Corno F.; M. Sonza Reorda; G. Squillero
    CEC2000: Congress on Evolutionary Computation, San Diego (USA), July 2000, pp. 1401-1406, 2000, pp. 1401-1406

  277. High-Level Observability for Effective High-Level ATPG
    Corno F.; M. Sonza Reorda; G. Squillero
    VTS2000: 18th IEEE VLSI Test Symposium, Montreal, Canada, May 2000, pp. 411-416, 2000, pp. 411-416

  278. Low Power BIST via Non-Linear Hybrid Cellular Automata
    Corno F; Rebaudengo M; Sonza Reorda M; Squillero G.; Violante M
    Proceedings of the 18th IEEE VLSI Test Symposium (VTS'00), 2000, pp. 29-34

  279. Prediction of Power Requirements for High-Speed Circuits
    Corno F; Rebaudengo M; Sonza Reorda M; Squillero G.; Violante M
    European Workshops on Telecommunications, 2000, pp. 247-254

  280. Prediction of Power Requirements for High-Speed Circuits
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    Lecture notes in Computer Science, 2000, pp. 247-254

  281. RT-level Fault Simulation Techniques based on Simulation Command Scripts
    Corno F.; G. Cumani; M. Sonza Reorda; G. Squillero
    DCIS2000: XV Conference on Design of Circuits and Integrated Systems, Le Corum, Montpellier, November 21-24, 2000, pp. 825-830, 2000, pp. 825-830

  282. Speeding-up Fault Injection Campaigns in VHDL models
    Rebaudengo M., Sonza Reorda M., Violante M., Parrotta B.
    Lecture notes in Computer Science, 2000, pp. 27-36

  283. Approximate Equivalence Verification for Protocol Interface Implementation via Genetic Algorithms
    Corno F; Sonza Reorda M; Squillero G.
    Lecture notes in Computer Science, 1999, pp. 182-192

  284. Approximate Equivalence Verification of Sequential Circuits via Genetic Algorithms
    Corno F; Sonza Reorda M; Squillero G.
    Proceedings of the conference on Design, automation and test in Europe, 1999, pp. 754-755

  285. FlexFi: A Flexible Fault Injection Environment for Microprocessor-Based Systems
    Benso A., Rebaudengo M., Sonza Reorda M.
    Lecture notes in Computer Science, 1999, pp. 323-335

  286. High Quality Test Pattern Generation for RT-level VHDL Descriptions
    Corno F; Sonza Reorda M; Squillero G.
    2nd International Workshop on Microprocessor Test and Verification Common Challenges and Solutions, 1999

  287. Optimizing Deceptive Functions with the SG-Clans Algorithm
    Corno F; Sonza Reorda M; Squillero G.
    Congress on Evolutionary Computation, 1999, pp. 2190-2195

  288. Simulation-Based Sequential Equivalence Checking of RTL VHDL
    Corno F; Sonza Reorda M; Squillero G.
    Proceedings the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999, pp. 351-354

  289. Test Pattern Generation under Low Power Constraints
    Corno F., Rebaudengo M., Sonza Reorda M., Violante M.
    Lecture notes in Computer Science, 1999, pp. 162-170

  290. Verifying the Equivalence of Sequential Circuits with Genetic Algorithms
    Corno F; Sonza Reorda M; Squillero G.
    Congress on Evolutionary Computation, 1999, pp. 1293-1297

  291. A New Evolutionary Algorithm Inspired by the Selfish Gene Theory
    Corno F; Sonza Reorda M; Squillero G.
    IEEE International Conference on Evolutionary Computation, 1998, pp. 575-580

  292. The Selfish Gene Algorithm: a New Evolutionary Optimization Strategy
    Corno F; Sonza Reorda M; Squillero G.
    Proceedings of the 1998 ACM symposium on Applied Computing, 1998, pp. 349-355

  293. VEGA: A Verification Tool Based on Genetic Algorithms
    Corno F; Sonza Reorda M; Squillero G.
    Proceedings the International Conference on Circuit Design, 1998, pp. 321-326

  294. A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits
    Corno F; Prinetto P; Rebaudengo M; Sonza Reorda M; Squillero G.
    Proceedings of the 6th Asian Test Symposium, 1997, pp. 56-61

  295. A New Approach for Initialization Sequences Computation for Synchronous Sequential Circuits
    Corno F; Prinetto P; Rebaudengo M; Sonza Reorda M; Squillero G.
    1997 IEEE Proceedings of the International Conference on Computer Design, 1997, pp. 381-386

  296. Boolean function manipulation on a parallel system using BDDs
    F. Bianchi, F. Corno, M. Rebaudengo, M. Sonza Reorda, R. Ansaloni
    Lecture notes in Computer Science, 1997, pp. 916-928

  297. GA-based Performance Analysis of Network Protocols
    Baldi M; Corno F; Rebaudengo M; Sonza Reorda M; Squillero G.
    9th IEEE Proceedings the International Conference on Tools with Artificial Intelligence, 1997, pp. 118-124

  298. Simulation-Based Verification of Network Protocols Performance
    Baldi M; Corno F; Prinetto P; Rebaudengo M; Sonza Reorda M; Squillero G.
    Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification, 1997, pp. 236-251

  299. A cellular genetic algorithm for the Floorplan area optimization problem on a SIMD architecture
    Rebaudengo M., Sonza Reorda M.
    Lecture notes in Computer Science, 1996, pp. 987-988

  300. A parallel genetic algorithm for Automatic Generation of Test Sequences for digital circuits
    Corno F., Prinetto P., Rebaudengo M., Sonza Reorda M.
    Lecture notes in Computer Science, 1996, pp. 454-459

  301. Exploiting competing subpopulations for automatic generation of test sequences for digital circuits
    Corno F., Prinetto P., Rebaudengo M., Sonza Reorda M.
    Lecture notes in Computer Science, 1996, pp. 791-800

  302. On-line testing of an off-the-shelf microprocessor board for safety-critical applications
    F. Corno, M. Damiani, L. Impagliazzo, P. Prinetto, M. Rebaudengo, G. Sartore , M. Sonza Reorda
    Lecture notes in Computer Science, 1996, pp. 190-201

  303. Test Pattern Generation under Low Power Constraints
    Corno F., Rebaudengo M, Sonza Reorda M., Violante M.
    Lecture notes in Computer Science, 1996, pp. 162-170

  304. Using parallel genetic algorithms for solving the Min-Cut problem
    G. Godza, M. Rebaudengo, M. Sonza Reorda
    Lecture notes in Computer Science, 1996, pp. 985-986

  305. A PVM tool for automatic test generation on parallel and distributed systems
    Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Enzo Veiluva
    Lecture notes in Computer Science, 1995, pp. 39-44

  306. Exploiting massively parallel architectures for the solution of diffusion and propagation problems
    P.P. Delsanto, S. Biancotto, M. Scalerandi, M. Rebaudengo, M. Sonza Reorda
    Lecture notes in Computer Science, 1995, pp. 1-6

  307. The use of model checking in ATPG for sequential circuits
    P. Camurati, M. Gilli, P. Prinetto, M. Sonza Reorda
    Lecture notes in Computer Science, 1991, pp. 86-95