An I-IP for the Debug of Microprocessor Cores
DCIS05: XX Conference on Design of Circuits and Integrated Systems, Lisboa, Portugal
Semiconductor manufacturers aim at deliver new devices within shorter times in order to gain market shares. First silicon debug is an important issue in order to minimize the time-to-market. In this paper we propose an Infrastructure IP (I-IP) intended to be a companion for processor cores. The I-IP is an efficient, low-cost and easy-to-adopt solution for supporting the silicon debug of microprocessor cores and of other cores in a SoC.
[AGRS05] D. Appello, M. Grosso, M. Rebaudengo, M. Sonza Reorda, "An I-IP for the Debug of Microprocessor Cores," DCIS05: XX Conference on Design of Circuits and Integrated Systems, Lisboa, Portugal