An Interpretation Framework for Evaluating High-Level Fault Models and ATPG Capabilities

Most ASICs are automatically generated from RT- (or higher) level de-scriptions. However, most of the test activities are still performed on gate-level. Several research efforts have been performed to devise test methods able to work directly on high-level descriptions. However, to develop indus- trially effective high-level test methodologies the relationship between high- level fault models and traditional gate-level stuck- at faults must be clearly understood. This paper presents an Interpretation Framework for evaluating, analyzing and understanding the results of RT-Level Fault Models and ATPGs. The proposed framework is applied to analyze the results of a specific tool. The investigation discriminates between the deficiencies of the tool algo-rithm and the adopted Fault Model, and shows that it is possible to foresee at the RT-level a large portion of untested gate-level faults.