RT-level Fault Simulation Techniques based on Simulation Command Scripts

With the advent of new RT-level design and test flow, new tools are needed to migrate at the RT-level the activities of fault simulation, testability analysis, and test pattern generation. This paper focuses on fault simulation at the RT-level, and aims at exploiting the capabilities of commercial VHDL simulators to compute faulty responses without modifying the VHDL source code. The proposed approach was implemented as a prototypical tool, and experimental results show that simulation of a faulty circuit is no more costly than simulation of the original circuit. For defining RT-level faults, we adopted a refinement of the observability-enhanced statement coverage metric. While this metric usually handles observability in an approximated way, we were able to efficiently and exactly determine the observability of single-bit stuck-at faults on all assignment statements.