Experimental analysis of fault models for behavioral-level test generation

The diffusion of the System-on-Chip paradigm is making even more important addressing design at the highest levels of abstraction. Behavioral-level design tools are today commercially available, and offer a solution to this problem. Conversely, test issues are usually addressed at the lowest levels of abstraction and, although in recent years many efforts have been devoted to the definition of strategies for addressing test at the high level, a global solution is yet to come. In particular, several high-level fault models have been proposed, most of them working at the RT-level. In this paper we report preliminary experimental results about some of the available high-level fault models working at the behavioral-level. The experimental procedure we adopted is presented and some preliminary results are discussed.