Automatic Test Program Generation - a Case Study

This paper describes a validation methodology for microprocessors based on the generation of suitable test programs. To devise an effective set of test programs, a small number of programs are randomly created and then optimized by an evolutionary core using the feedback information from a logic simulator. The proposed methodology is almost fully automatic, broadly applicable and does not rely on skilled experts. A synthesizable VHDL model of a 32-bit processor conforming to the SPARC V8 standard is used as a case study. Although of moderate size, this case study uncovers several problems that can be found in modern designs. The proposed methodology was exploited to generate a test program aimed at maximizing the RT-level statement coverage; the achieved results are compared with the ones attained with an instruction randomizer, and show the effectiveness of the proposed approach.