Integrating Online and Offline Testing of a Switching Memory
IEEE Design & Test of Computers, January-March 1998
ABSTRACT
The paper describes the architecture of a circuit used in a telephone switching unit and focuses on its on-line and off-line test features. Several techniques have been exploited: BIST is adopted to test some embedded memories, Partial Scan allows the test of the remaining logic, and Boundary Scan is used to activate the test and gather the results. Data are reported, concerning the obtained Fault Coverage, the hardware overhead and the performance penalties introduced by the approach. By sharing the same circuitry for both on-line and off-line testing we succeeded in minimizing the additional logic.
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[BCMP98] S. Barbagallo, F. Corno, D. Medina, P. Prinetto, M. Sonza Reorda, "Integrating Online and Offline Testing of a Switching Memory," IEEE Design & Test of Computers, January-March 1998