System-Level Modeling and Verification: a Comprehensive Design Methodology
ED&TC94: 1st IEEE European Design and Test Conference 1994, Paris, February 1994
KEYWORDS: Formal Verification,
System-Level
ABSTRACT
Working at system level is attracting increasing interest, as it supports the exploration of several alternatives, before the hardware/software partitioning takes place. New issues must be taken into account, such as validation and verification at all steps. This paper presents a system-level design methodology that supports description, validation, and verification at system-level.
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[CCPB94] P. Camurati, F. Corno, P. Prinetto, C. Bayol, B. Soulas, "System-Level Modeling and Verification: a Comprehensive Design Methodology," ED&TC94: 1st IEEE European Design and Test Conference 1994, Paris, February 1994