Advanced Techniques for GA-based sequential ATPGs
IEEE Design & Test Conference, Paris (F), March 1996
KEYWORDS: ATPG,
Approximate Methods,
Evolutionary Algorithms,
Gate-Level,
Genetic Algorithms,
Simulation-Based Approaches
ABSTRACT
Genetic Algorithms have been recently investigated as an efficient approach to test generation for synchronous sequential circuits. In this paper we propose a set of techniques which significantly improves the performance of the GA-based ATPG algorithm proposed in [PRSR94]: in particular, the new techniques enhance the capability of the algorithm in terms of test length minimization and fault excitation. We report some experimental results gathered with a prototypical tool and show that a well-tuned GA-based ATPG is generally superior to both symbolic and topological ones in terms of achieved Fault Coverage and required CPU time.
| Related files: | |
|---|---|
| edtc96.pdf | Adobe Acrobat portable document |
| edtc96.ps.gz | postscript document, compressed (with gzip) |
Copyright note for papers published by the IEEE Computer Society:
Copyright IEEE. Personal use of this material is permitted. However,
permission to reprint/republish this material for advertising or
promotional purposes or for creating new collective works for resale
or redistribution to servers or lists, or to reuse any copyrighted
component of this work in other works, must be obtained from the IEEE.
[CPRS96] F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, R. Mosca, "Advanced Techniques for GA-based sequential ATPGs," IEEE Design & Test Conference, Paris (F), March 1996