Advanced Techniques for GA-based sequential ATPGs
IEEE Design & Test Conference, Paris (F), March 1996
KEYWORDS: ATPG, Approximate Methods, Evolutionary Algorithms, Gate-Level, Genetic Algorithms, Simulation-Based Approaches
Genetic Algorithms have been recently investigated as an efficient approach to test generation for synchronous sequential circuits. In this paper we propose a set of techniques which significantly improves the performance of the GA-based ATPG algorithm proposed in [PRSR94]: in particular, the new techniques enhance the capability of the algorithm in terms of test length minimization and fault excitation. We report some experimental results gathered with a prototypical tool and show that a well-tuned GA-based ATPG is generally superior to both symbolic and topological ones in terms of achieved Fault Coverage and required CPU time.
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[CPRS96] F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, R. Mosca, "Advanced Techniques for GA-based sequential ATPGs," IEEE Design & Test Conference, Paris (F), March 1996