Post-Silicon Functional Failing-Test Generation through Evolutionary Computation

The incessant progress in manufacturing technology is posing new challenges to microprocessor designers. Several activities that were originally supposed to be part of the pre-silicon design phase are migrating after tape-out, when the first silicon prototypes are available. The paper describes a post-silicon methodology that can be exploited to devise functional failing tests, essential to analyze and debug speed paths during verification, speed-stepping, and other critical activities. The proposed methodology is based on an evolutionary algorithm and exploits a versatile toolkit named µGP. The paper describes how such an high-level methodology may take into account complex hardware characteristics and architectural details of complex devices. The experimental evaluation clearly demonstrates the potential of this line of research.