Code Generation for Functional Validation of Pipelined Microprocessors

Functional verification of pipelined microprocessors is a challenging task, as the behavior of a pipeline is determined by a sequence of instructions and by the interaction between their operands. This paper describes an approach to test-program generation based on an evolutionary algorithm. The proposed methodology is able to tackle complex pipelined designs. Human intervention is limited to the enumeration of all assembly instructions, and also internal parameters of the optimizer are auto-adapted. A prototype was built and exploited to generate test programs for the DLX/pII, a simple pipelined microprocessor. Test programs were devised trying to maximize the RT-level statement coverage. Results show the feasibility and effectiveness of the method.