CA-CSTP: A new BIST Architecture for Sequential Circuits
ETW2000: European Test Workshop, May 2000, pp. 167-172
KEYWORDS: Approximate Methods,
BIST,
Cellular Automata,
Evolutionary Algorithms,
Gate-Level,
Genetic Algorithms,
Simulation-Based Approaches
ABSTRACT
Circular Self-Test Path (CSTP) is an attractive technique for implementing BIST in sequential circuits; unfortunately, there are cases in which the fault coverage it attains is unacceptably low. This paper proposes a new architecture, named CA-CSTP, which overcomes these limitations and always reaches a high fault coverage by exploiting a slightly more complex chain cell based on a Cellular Automata architecture. Experimental results show the effectiveness of our proposal.
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[CSSV00] F. Corno, M. Sonza Reorda, G. Squillero, M. Violante, "CA-CSTP: A new BIST Architecture for Sequential Circuits," ETW2000: European Test Workshop, May 2000, pp. 167-172