An RT-level Fault Model with High Gate Level Correlation

One of the hardest theoretical barrier to the diffusion of test-related tools at the RT-level is the lack of widely accepted fault models. Several variants of high level faults (or testability metrics, as they are sometimes called) have been proposed, and their relationships with stuck-at faults has been shown, either experimentally or theoretically, but such results are generally limited to some specific class of circuits (some approaches target control-dominated circuits [CSSq00b], other are more suited to data-dominated ones [FADe99], or to circuits with few interactions with the environment [FiFu00], and so on). No single fault model is universally accepted, since no comprehensive and general results, valid for all classes of circuits, are known yet. One of the most used fault model is the observability enhanced statement coverage metric proposed in [DGKe96] and [FDKe98]. This fault model requires that all statements in the VHDL description are executed at least once, and that their effects are propagated to at least one primary output. Propagation is modeled implicitly, by determining whether the faulty statement may influence the output values but without hypothesizing any specific faulty value: in some cases, heuristics are needed to resolve non-determinism, and the meaningfulness of the resulting fault coverage is affected by these approximations. While this approach can be fruitfully exploited for test pattern generation [FADe99] [CSSq00b], for fault simulation we need more accurate results. In this paper we thus adopt a particular instantiation of the observability enhanced statement coverage metric, and in particular we model single stuck-at bit faults on all assignment targets of the executed statements that respects an defined set of rules. With this choice, a concrete faulty behavior is simulated, and fault propagation can therefore be performed exactly, by computing the faulty machine evolution. This fault model implies observability enhanced statement coverage, since it models one of the possible fault classes on executed statements. We also define a series of rules to identify redundant faults in the fault list, obtained using the proposed fault model, in order to increase the correlation between the RT-level fault coverage and the Gate-level one. Redundancies identification is based on the reduction of the RT-level fault list taking into account analyzing the optimizations of the synthesis process, in order to eliminate faults corresponding to part of the logic optimized away by the synthesizer.