Behavioral-level fault models comparison: an experimental approach

While the design practice is quickly moving toward higher levels of abstraction, test issues are still considered only when a detailed description of the design is available, typically at the gate-level for test sequence generation purposes and register transfer (RT)-level for design for testability structures insertion. In the past years, intensive research efforts have been devoted to devise solutions tackling test sequence generation since the early design phases, mainly the RT-level and several approaches have been proposed. In this paper we report preliminary results of an experimental analysis of the available high-level fault models when test is addressed at the behavioral-level. The experimental procedure we adopted is presented and some preliminary results are discussed.