VEGA: A Verification Tool Based on Genetic Algorithms
ICCD98, International Conference on Circuit Design, Austin, Texas (USA), October 1998, pp. 321-326
KEYWORDS: Approximate Methods, Equivalence Checking, Evolutionary Algorithms, Gate-Level, Genetic Algorithms, Simulation-Based Approaches
While modern state-of-the-art optimization techniques can handle designs with up to hundreds of flip-flops, equivalence verification is still a challenging task in many industrial design flows. This paper presents a new verification methodology that, while sacrificing exactness, is able to handle larger circuits and give designers the opportunity to trade off CPU time with confidence on the result. The proposed methodology is able to fruitfully support an exact verification tool, dramatically increasing the confidence on the validity of an optimization process. A prototypical tool has been developed and preliminary experimental results that support this claim are shown in the paper.
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[CSSq98] F. Corno, M. Sonza Reorda, G. Squillero, "VEGA: A Verification Tool Based on Genetic Algorithms," ICCD98, International Conference on Circuit Design, Austin, Texas (USA), October 1998, pp. 321-326