Simulation-Based Sequential Equivalence Checking of RTL VHDL
ICECS99: 6th IEEE International Conference on Electronics, Circuits and Systems, Paphos, Cyprus, September 1999, pp. 351-354
KEYWORDS: Approximate Methods,
Equivalence Checking,
Evolutionary Algorithms,
Gate-Level,
Genetic Algorithms,
Rt-Level,
Simulation-Based Approaches,
VHDL
ABSTRACT
This paper presents a novel approach to equivalence verification of RT-Level descriptions. The proposed approach sacrifices exactness in favor of applicability: it is not always able to produce an answer, but it is able to check sequential equivalence of large systems. Furthermore, being based on commercial VHDL tools, it does not have arbitrary limitations in the syntax of the descriptions.
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[CSSq99] F. Corno, M. Sonza Reorda, G. Squillero, "Simulation-Based Sequential Equivalence Checking of RTL VHDL," ICECS99: 6th IEEE International Conference on Electronics, Circuits and Systems, Paphos, Cyprus, September 1999, pp. 351-354