A Genetic Algorithm for Automatic Generation of Test Logic for Digital Circuits

Testing is a key issue in the design and production of digital circuits: the adoption of BIST (Built-In Self-Test) techniques is increasingly popular, but sometimes requires efficient algorithms for the automatic generation of the logic which generates the test vectors applied to the Unit Under Test. This paper addresses the issue of identifying a Cellular Automaton able to generate input patterns to detect stuck-at faults inside a Finite State Machine (FSM). A suitable hardware structure is first identified. A Genetic Algorithm is then proposed, which directly identifies a Cellular Automaton able to reach a very good Fault Coverage of the stuck-at faults. The novelty of the method consists in combining the generation of test patterns with the synthesis of a Cellular Automaton able to reproduce them. Experimental results are provided, which show that in most of the standard benchmark circuits the Cellular Automaton selected by the Genetic Algorithm is able to reach a Fault Coverage close to the maximum one. Our approach is the first attempt of exploiting evolutionary techniques for identifying the hardware for input pattern generation in BIST structures.