Finding the Maximum Clique in a Graph Using BDDs
ICVC93: IEEE 3rd International Conference on VLSI and CAD, Taejon, Korea, November 1993, pp. 269-272
ABSTRACT
Working at system level is attracting increasing interest, as it supports the exploration of several alternatives, before the hardware/software partitioning takes place. New issues must be taken into account, such as validation and verification at all steps. This paper presents a system-level design methodology that supports verification. Starting from a description in a verification-oriented version of VHDL, an efficient BDD-based tool for Process Algebras is used to perform equivalence proofs.
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[CPSe93] F. Corno, P. Prinetto, M. Sonza Reorda, "Finding the Maximum Clique in a Graph Using BDDs," ICVC93: IEEE 3rd International Conference on VLSI and CAD, Taejon, Korea, November 1993, pp. 269-272