Partial Scan Flip Flop Selection for Simulation-based Sequential ATPGs
IEEE International Test Conference, Washington (USA), October 1996
KEYWORDS: ATPG,
Approximate Methods,
Evolutionary Algorithms,
Gate-Level,
Genetic Algorithms,
Partial Scan,
Simulation-Based Approaches
ABSTRACT
The partial scan approach is now widely adopted and several commercial tools support this technique. However, there is no general agreement on how to select the Scan Flip Flops: in general each technique is tailored to a particular ATPG algorithm and results effective when coupled with the right ATPG tool. In this paper, we propose an approach suitable for GA-based ATPGs, which is based on exploiting some information coming from the ATPG itself; we compare the results of our method with the ones of the approach based on cutting the topological loops and use a GA-based ATPG to demonstrate its effectiveness in terms of Fault Coverage and CPU time.
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[CPRS96] F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, "Partial Scan Flip Flop Selection for Simulation-based Sequential ATPGs," IEEE International Test Conference, Washington (USA), October 1996