Automatic generation of software-based functional failing test for speed debug and on-silicon timing verification
MTV11: International Workshop on Microprocessor Test and Verification
KEYWORDS: Approximate Methods, Evolutionary Algorithms, Genetic Programming, MicroGP, Microprocessors, Post-Silicon Verification, Speed Paths
The 40 years since the appearance of the Intel 4004 deeply changed how microprocessors are designed. Today, essential steps in the validation process are performed relying on physical dices, analyzing the actual behavior under appropriate stimuli. This paper presents a methodology that can be used to devise assembly programs suitable for a range of on-silicon activities, like speed debug, timing verification or speed binning. The methodology is fully automatic. It exploits the feedback from the microprocessor under examination and does not rely on information about its microarchitecture, nor does it require design-for-debug features. The experimental evaluation performed on a Intel Pentium Core i7-950 demonstrates the feasibility of the approach.
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[SSTo11] E. Sanchez, G. Squillero, A. Tonda, "Automatic generation of software-based functional failing test for speed debug and on-silicon timing verification," MTV11: International Workshop on Microprocessor Test and Verification