High Quality Test Pattern Generation for RT-level VHDL Descriptions

In current microprocessor design, an increasingly high silicon portion is derived through automatic syn-thesis. Effective test generation procedures working on the HDL before synthesis would therefore be extremely useful to shorten the design cycle and increase the test quality. This paper presents an effective test pattern generator working at the RT-level on the synthesizable VHDL source. The tool is based on an extensive con-trol- and data-flow analysis of the design and on a Genetic Algorithm interacting with a commercial simu-lator. Experimental results concerning a set of standard benchmarks show that the obtained results, in terms of gate-level stuck-at fault coverage, are much better than a previous version of the tool and are very close to those obtained by state-of-the-art gate-level ATPGs.