An experimental analysis of hardening techniques for SRAM-based FPGAs

Triple Modular Redundancy (TMR) is recognized as one of the possible solutions to harden circuits implemented on SRAM-based FPGAs against soft-errors affecting configuration memory and user memory. Several works already showed crosssection figures confirming the soundness of TMR principle, however some faults still escape the TMR's fault masking mechanism. In this work we analyzed by means of extensive fault-injection experiments the TMR architecture. We identified some of the causes that are responsible for the escaped faults, and we proposed some possible solutions. In our analyses we considered both the TMR and one of its enhanced versions, the XTMR.