Reducing Test Application Time through Interleaved Scan
SBCCI2002: 15th IEEE Symposium on Integrated Circuits and Systems Design, Porto Alegre (Brasil), Septempber 2002, pp. 89-94
Outstanding Paper Award
KEYWORDS: ATPG,
Test Compaction
ABSTRACT
This paper proposes a new method for reducing the test length for digital circuits by adopting an architecture derived from the popular scan approach. An evolutionary optimization algorithm is exploited to find the optimal solution. The proposed approach was tested on the ISCAS89 standard benchmarks and the experimental results show its effectiveness.
[CSSq02] F. Corno, M. Sonza Reorda, G. Squillero, "Reducing Test Application Time through Interleaved Scan," SBCCI2002: 15th IEEE Symposium on Integrated Circuits and Systems Design, Porto Alegre (Brasil), Septempber 2002, pp. 89-94