VOVHDL: a verification-oriented dialect of VHDL

P. Camurati F. Corno P. Prinetto C. Bayol B. Soulas

VFE93: VHDL-Forum for CAD in Europe, Hamburg (D), September 1993, pp. 37-47

KEYWORDS: Formal Verification, Rt-Level, VHDL

ABSTRACT

This paper presents the VO-VHDL language, defined to be a formally verifiable variant of VHDL. The communication semantics are described, as well as a syntax for describing them.

[CCPB93] P. Camurati, F. Corno, P. Prinetto, C. Bayol, B. Soulas, "VOVHDL: a verification-oriented dialect of VHDL," VFE93: VHDL-Forum for CAD in Europe, Hamburg (D), September 1993, pp. 37-47