Low Power BIST via Hybrid Cellular Automata

In the last decade, researchers devoted increasing efforts to reduce the average power consumption in VLSI systems during normal operation mode, while power consumption during test operation mode was usually neglected. However, during test application the circuits are subject to an activity higher than the normal one: the extra power consumption due to test application may thus rise severe hazards to the circuit reliability. Moreover, it can dramatically shorten the battery life when periodic testing of battery-powered systems is considered. In this paper we propose an algorithm to design a Test Pattern Generator for testing of combinational circuits that effectively reduces the power consumption while attaining high Fault Coverage. Experimental results show that our approach saves 30% on the average of the power consumed during test without affecting Fault Coverage and Test Length.