A new Functional Fault Model for System-Level Descriptions
VTS94: 12th IEEE VLSI Test Symposium, Cherry Hill, NJ (USA), April 1994
ABSTRACT
Process Algebras are a suitable formalism both for system-level description and for ATPG with formal verification techniques. A functional fault model for System-Level descriptions is presented and experimental data are reported. The contributions of this paper are the definition of a general-purpose fault model for concurrently evolving processes and the implementation of a test pattern generation procedure, as a variant of the testing equivalence proof. A complete test system is implemented, allowing to describe systems, describe faults and generate test patterns whithin the same environment.
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[CCMP94] P. Camurati, F. Corno, M. Meo, P. Prinetto, "A new Functional Fault Model for System-Level Descriptions," VTS94: 12th IEEE VLSI Test Symposium, Cherry Hill, NJ (USA), April 1994