RT-level TPG Exploiting High-Level Synthesis Information
17th IEEE VLSI Test Symposium, Dana Point (USA), April 1999
KEYWORDS: ATPG,
Approximate Methods,
Evolutionary Algorithms,
Genetic Algorithms,
Rt-Level,
Simulation-Based Approaches,
VHDL
ABSTRACT
High-level test pattern generation is today a widely investigated research topic. The present paper proposes a fully automated, simulation-based ATPG system, to address test pattern generation for circuits described at the RT-level. The approach is based on a set of suitable testability metrics, and the test pattern generation phase resorts to Genetic Algorithms. Experiments show the excellent fault coverage provided by the RT-level test patterns, when applied at the final gate-level. The approach, being based on a high-level representation, promises to be particularly suited where gate-level ATPGs are often inefficient, mainly for large circuits and for control-intensive designs.
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[CCPr99] S. Chiusano, F. Corno, P. Prinetto, "RT-level TPG Exploiting High-Level Synthesis Information," 17th IEEE VLSI Test Symposium, Dana Point (USA), April 1999