Devising an RT-Level ATPG for uProcessor Cores
WRTLT2001: 2nd Worshop on RTL, ATPG & DFT, Nara, Japan, November 22-23, 2001
KEYWORDS: ATPG,
Approximate Methods,
Evolutionary Algorithms,
Genetic Algorithms,
Microprocessors,
Rt-Level,
Simulation-Based Approaches,
VHDL
ABSTRACT
The issue of SOC testing is one of the most crucial in their design and production process. A popular solution for SOCs including microprocessor cores is based on letting them execute a test program, thus implementing a very attracting BIST solution. This paper describes a method for the generation of effective programs for the self-test of a processor starting from its RT-level description. The method can be partially automated, and combines ideas from traditional functional approaches and from the ATPG field. We are preliminary assessing the feasibility and effectiveness of the method by applying it to an 8051 core.
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[CCSS01] F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero, "Devising an RT-Level ATPG for uProcessor Cores," WRTLT2001: 2nd Worshop on RTL, ATPG & DFT, Nara, Japan, November 22-23, 2001