Publications

  1. A Comprehensive Methodology for Stress Procedures Evaluation and Comparison for Burn-In of Automotive SoC
    P. Bernardi, D. Appello, G. Giacopelli, A. Motta, A. Pagani, G. Pollaccia, C. Rabbi, M. Restifo, P. Ruberg, E. Sanchez, C. Villa, F. Venini
    Titolo non avvalorato

  2. A Light-Weight Fault Tolerance Framework for Space Computing using COTS Components
    S. Campagna, H. Moazzam, M. Violante
    LECTURE NOTES IN COMPUTER SCIENCE

  3. A New Soft-Error Resilient Voltage-Mode Quaternary Latch
    E. Rhod, L. Sterpone, L. Carro

  4. A New Software Tool for Static Analysis of SET Sensitiveness in Flash-based FPGAs
    N. Battezzati, F. Decuzzi, L. Sterpone, M. Violante

  5. A new EDA flow for the Mitigation of SEUs in Dynamic Reconfigurable FPGAs
    B. Du, L. Sterpone, D. Codinachs
    21st IEEE European Test Symposium Proceedings
    KEYWORDS: reconfiguration, design flow, placement, routing, reliability, fault tolerance, fpga
    ABSTRACT: This work presents a new EDA flow that aims to increase the design robustness versus transient errors when the dynamic reconfigurable computing paradigm is adopted. In brief, we propose a modification of the existing commercial toolchain flow to make transient error aware designs. Aiming at that scope, a new algorithm for the design mapping has been developed reducing Single Event Upsets on the routing interactions between reconfigurable placed modules. The performance evaluation of the EDA flow has been evaluated with neutron-based radiation test experiments and fault injection using a proper dynamic reconfiguration context. Results prove a reduction of the transient error sensitivity about 3 orders of magnitude without any area overhead and with a performance degradation of less than 10% on the average

  6. An Analytical Model of the Propagation Induced Pulse Broadening (PIPB) Effects on Single Event Transient in Flash-based FPGAs
    L. Sterpone, N. Battezzati, F. Lima Kastensmidt

  7. An Evolutionary Approach to Hardware Encryption and Trojan-Horse Mitigation
    A. Marcelli, M. Restifo, E. Sanchez, G. Squillero
    Proceedings
    KEYWORDS: multi-objective evolutionary algorithm; hardware security; hardware trojan horses; hardware encription
    ABSTRACT: New threats, grouped under the name of hardware attacks, became a serious concern in recent years. In a global market, untrusted parties in the supply chain may jeopardize the production of integrated circuits with intellectual-property piracy, illegal overproduction, and hardware Trojan-horses injection. While one way to protect from overproduction is to encrypt the design by inserting logic gates that prevents the circuit from generating the correct outputs unless the right key is used, reducing the number of poorly-controllable signals is known to minimize the chances for an attacker to successfully hide the trigger for some malicious payload. Several approaches successfully tackled independently these two issues. Differently, this paper proposes a novel technique based on a multi-objective evolutionary algorithm able to increase hardware security by explicitly targeting both the minimization of rare signals and the maximization of the efficacy of logic encryption. Experimental results demonstrate the effectiveness of the proposed method.

  8. Hardening Dynamically Reconfigurable Processing Modules Architectures: A Neutron Test Experience
    M. Desogus, L. Sterpone, D. Sabena, A. Ullah, M. Porrmann, J. Hagemeyer, J. Ilstad
    Proceedings of Radiation Effects on Components and Systems 2013

  9. Real-Time SEU Tolerant Circuits on SRAM-based FPGAs
    U. Sterpone Luca
    Proceedings of Radiation Effects on Components and Systems 2013

  10. A DMA and CACHE-based stress schema for burn-in of automotive microcontroller
    P. Bernardi, R. Cantoro, L. Gianotto, M. Restifo, E. Sanchez, F. Venini, D. Appello
    DOI: 10.1109/LATW.2017.7906767
    KEYWORDS: memory management; stress; random access memory; built-in self-test; automotive engineering; thermal stresses; performance evaluation
    ABSTRACT: Thermal and electrical stress phases are commonly applied to automotive devices at the end of manufacturing test to give rise to early life latent failures. This paper proposes a new methodology to optimize the stress procedures during the Burn-In phase. In the proposed method, stress of CPU, RAM memory and FLASH memory are run in parallel using DMA and CACHE interventions. The paper reports also some experimental results gathered in an automotive microcontroller, and a comparison between traditional and parallelized burn-in stress technique is also provided.

  11. Adaptive Batteries Exploiting On-Line Steady-State Evolution Strategy
    E. Fadda, G. Perboli, G. Squillero
    Applications of Evolutionary Computation
    DOI: 10.1007/978-3-319-55849-3_22
    KEYWORDS: optimisation; evolutionary strategy; battery; intelligent systems
    ABSTRACT: In energy distribution systems, uncertainty is the major single cause of power outages. In this paper, we consider the usage of electric batteries in order to mitigate it. We describe an intelligent battery able to maximize its own lifetime while guaranteeing to satisfy all the electric demand peaks. The battery exploits a customized steady-state evolution strategy to dynamically adapt its recharge strategy to changing environments. Experimental results on both synthetic and real data demonstrate the efficacy of the proposed solution.

  12. An Effective Fault-Injection Framework for Memory Reliability Enhancement Perspectives
    G. Harcha, P. Girard, A. Virazel
    Design &Technology of Integrated Systems in Nanoscale Era

  13. Multi-objective Evolutionary Algorithms for Influence Maximization in Social Networks
    D. Bucur, G. Iacca, A. Marcelli, G. Squillero, A. Tonda
    Applications of Evolutionary Computation
    DOI: 10.1007/978-3-319-55849-3_15
    KEYWORDS: social network; multi-objective evolutionary algorithms; influence maximization
    ABSTRACT: As the pervasiveness of social networks increases, new NP-hard related problems become interesting for the optimization community. The objective of influence maximization is to contact the largest possible number of nodes in a network, starting from a small set of seed nodes, and assuming a model for information propagation. This problem is of utmost practical importance for applications ranging from social studies to marketing. The influence maximization problem is typically formulated assuming that the number of the seed nodes is a parameter. Differently, in this paper, we choose to formulate it in a multi-objective fashion, considering the minimization of the number of seed nodes among the goals, and we tackle it with an evolutionary approach. As a result, we are able to identify sets of seed nodes of different size that spread influence the best, providing factual data to trade-off costs with quality of the result. The methodology is tested on two real-world case studies, using two different influence propagation models, and compared against state-of-the-art heuristic algorithms. The results show that the proposed approach is almost always able to outperform the heuristics.

  14. On the detection of board delay faults through the execution of functional programs
    G. An, R. Cantoro, E. Sanchez, M. Reorda
    DOI: 10.1109/LATW.2017.7906759
    KEYWORDS: computational modeling; ip networks; delays; circuit faults; integrated circuit modeling; random access memory; testing
    ABSTRACT: In the last years, the phenomenon of electronic products passing all tests by the manufacturer but failing in the field (No Fault Found, or NFF) attracted the attention of industries and researchers. Delay faults are supposed to be among the contributors to this phenomenon. Hence, companies are increasingly adopting functional test as a final step, which is expected to detect this kind of defects. This paper investigates the capabilities of detecting delay faults by several types of functional test, and proposes a method to write functional test programs able to detect most of the delay faults on the connections between the CPU and the memory.

  15. Radiation-induced SET on Flash-based FPGAs: Analysis and Filtering methods
    L. Sterpone, S. Azimi
    ARCS 2017 - 30th International Conference on Architecture of Computing Systems Workshop Proceedings
    KEYWORDS: redundancy; single event transients; flash-based fpgas; electrical injection; filtering
    ABSTRACT: Reliability of Integrated Circuits (ICs) it is nowadays a major concern for deep sub-micron technology. The progressive decreasing of device feature sizes provokes an increasing sensitiveness to radiation-induced particle strikes within the device silicon structure generating a larger number of Single Event Transients (SETs). In the present paper, we propose a new analysis to characterize the SET phenomena within Flashbased FPGAs. Besides, we developed a new mitigation strategy based on the modification of the place and routed design to improve the filtering capability selectively adding electrical resistive capacitive loads without introducing performance degradation and introducing a limited overhead in terms of routing segments. Experimental results performed on a various set of benchmark circuits shows a mitigation of SET improved of 3 orders of magnitude with respect to traditional logical filtering solutions with a minimal performance degradation of about 9%.

  16. A General-Purpose Framework for Genetic Improvement
    F. Marino, G. Squillero, A. Tonda
    Parallel Problem Solving from Nature - PPSN XIV
    DOI: 10.1007/978-3-319-45823-6_32
    KEYWORDS: genetic improvement, genetic programming, linear genetic programming, software engineering
    ABSTRACT: Genetic Improvement is an evolutionary-based technique. Despite its relatively recent introduction, several successful applications have been already reported in the scientific literature: it has been demonstrated able to modify the code complex programs without modifying their intended behavior; to increase performance with regards to speed, energy consumption or memory use. Some results suggest that it could be also used to correct bugs, restoring the software's intended functionalities. Given the novelty of the technique, however, instances of Genetic Improvement so far rely upon ad-hoc, language-specific implementations. In this paper, we propose a general framework based on the software engineering's idea of mutation testing coupled with Genetic Programming, that can be easily adapted to different programming languages and objective. In a preliminary evaluation, the framework efficiently optimizes the code of the md5 hash function in C, Java, and Python

  17. A New Simulation-Based Fault Injection Approach for the Evaluation of Transient Errors in GPGPUs
    S. Azimi, B. Du, L. Sterpone
    Lecture notes in Computer Science
    DOI: 10.1007/978-3-319-30695-7_29
    KEYWORDS: gpgpu, radiation effects, seu, set, reliability
    ABSTRACT: General Purpose Graphics Processing Units (GPGPUs) are increasingly adopted thanks to their high computational capabilities. GPGPUs are preferable to CPUs for a large range of computationally intensive applications, not necessarily related to computer graphics. Within the high performance computing context, GPGPUs must require a large amount of resources and have plenty execution units. GPGPUs are becoming attractive for safety-critical applications where the phenomenon of transient errors is a major concern. In this paper we propose a novel transient error fault injection simulation methodology for the accurate simulation of GPGPUs applications during the occurrence of transient errors. The developed environment allows to inject transient errors within all the memory area of GPGPUs and into not user-accessible resources such as in streaming processors combinational logic and sequential elements. The capability of the fault injection simulation platform has been evaluated testing three benchmark applications including mitigation approaches. The amount of computational costs and time measured is minimal thus enabling the usage of the developed approach for effective transient errors evaluation

  18. A Selective Mapper for the Mitigation of SETs on Rad-Hard RTG4 Flash-based FPGAs
    S. Azimi, B. Du, L. Sterpone
    IEEE RADECS 2016
    KEYWORDS: fpga, mitigation, rtg4

  19. A Suite of IEEE 1687 Benchmark Networks
    A. T{\vs}ertov, A. Jutman, S. Devadze, M. Sonza Reorda, E. Larsson, F. Ghani Zadegan, R. Cantoro, M. Montazeri, R. Krenz-Baath
    ABSTRACT: The saturation of the IJTAG concept and its approval as the IEEE 1687 standard in 2014 has generated a wave of research activities and created demand for a set of appropriate and challenging benchmarks. This paper presents such a set developed by an industrial and academic consortium and constructed in a way that facilitates objective comparison of experimental results across research groups as well as represents challenging network examples exhaustively utilizing features and constructs defined by the standard. The suite is arranged in four comprehensive categories, each having its particular purpose and composition principles, as described in the paper. We have also made an analysis of limitations of previous popular and ad-hoc benchmark sets as these limitations majorly motivated our current action. The new public-domain benchmarks are distributed together with source files and documentation through the dedicated web site. Some of the previous research results on IEEE 1687 have been reapplied on the new benchmarks set, thus creating an important initial reference point for the research community.

  20. A low-cost susceptibility analysis methodology to selectively harden logic circuits
    I. Wali, B. Deveautour, A. Virazel, A. Bosio, P. Girard, M. Reorda
    2016 21th IEEE European Test Symposium (ETS)
    DOI: 10.1109/ETS.2016.7519296

  21. A neural network model based on co-occurrence matrix for fall prediction
    H. Masoud, R. Ferrero, B. Montrucchio, M. Rebaudengo
    KEYWORDS: fall prediction, fall avoidance system, fall prevention, health care system
    ABSTRACT: Fall avoidance systems reduce injuries due to unintentional falls, but most of them are fall detections that activate an alarm after the fall occurrence. Since predicting a fall is the most promising approach to avoid a fall injury, this study proposes a method based on new features and multilayer perception that outperforms state-of-the-art approaches. Since accelerometer and gyroscope embedded in a smartphone are recognized to be precise enough to be used in fall avoidance systems, they have been exploited in an experimental analysis in order to compare the proposal with state-of-the-art approaches. The results have shown that the proposed approach improves the accuracy from 83% to 90%

  22. AN INTEGRATED APPROACH FOR POLLUTION MONITORING: SMART ACQUIREMENT AND SMART INFORMATION
    E. Arco, P. Boccardo, F. Gandino, A. Lingua, F. Noardo, M. Rebaudengo
    ISPRS ANNALS OF THE PHOTOGRAMMETRY, REMOTE SENSING AND SPATIAL INFORMATION SCIENCES
    DOI: 10.5194/isprs-annals-IV-4-W1-67-2016
    KEYWORDS: pollution, semantic web, environmental monitoring, dynamic sensors, standard data models, internet of things
    ABSTRACT: Air quality is a factor of primary importance for the quality of life. The increase of the pollutants percentage in the air can cause serious problems to the human and environmental health. For this reason it is essential to monitor its values to prevent the consequences of an excessive concentration, to reduce the pollution production or to avoid the contact with major pollutant concentration through the available tools. Some recently developed tools for the monitoring and sharing of the data in an effective system permit to manage the information in a smart way, in order to improve the knowledge of the problem and, consequently, to take preventing measures in favour of the urban air quality and human health. In this paper, the authors describe an innovative solution that implements geomatics sensors (GNSS) and pollutant measurement sensors to develop a low cost sensor for the acquisition of pollutants dynamic data using a mobile platform based on bicycles. The acquired data can be analysed to evaluate the local distribution of pollutant density and shared through web platforms that use standard protocols for an effective smart use

  23. Accurate Analysis of SET effects on Flash-based FPGA System-on-a-Chip for Satellite Application
    G. Raoul, M. David, F. Luca
    IEEE DDECS
    KEYWORDS: fpgas, radiation effects, set, seu, see

  24. Accurate Analysis of SET effects on Flash-based FPGA System-on-a-Chip for Satellite Applications
    S. Azimi, B. Du, L. Sterpone
    IEEE RADECS
    KEYWORDS: fpga, radiation, set, see, seu, fault tolerance

  25. Accurate Analysis of SET effects on Flash-based FPGA System-on-a-Chip for Satellite Applications
    S. Azimi, B. Du, L. Sterpone, R. Grimoldi, L. Fossati, D. Codinachs
    IEEE DDECS 2016
    KEYWORDS: fpgas, radiation effects, set, seu, see

  26. An FPGA-based testing platform for the validation of automotive powertrain ECU
    B. Du, L. Sterpone
    2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016
    DOI: 10.1109/VLSI-SoC.2016.7753553
    KEYWORDS: fpga; gtm; hardware and architecture; electrical and electronic engineering; automotive; ecu validation; etpu

  27. An effective approach for functional test programs compaction
    A. Touati, A. Bosio, P. Girard, A. Virazel, P. Bernardi, M. Reorda
    Formal Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2016
    DOI: 10.1109/DDECS.2016.7482466
    KEYWORDS: safety, risk, reliability and quality; electrical and electronic engineering; hardware and architecture; test compaction; sbst; microprocessor test; functional test

  28. Analysis and optimization of Synchronization Algorithms for Multicore Architectures
    M. Hemmatpour, R. Ferrero, B. Montrucchio, M. Rebaudengo
    KEYWORDS: multicore design, synchronization techniques, parallel programming

  29. Analysis of radiation-induced SEUs on dynamic reconfigurable systems
    L. Boragno, L. Sterpone, D.M. Codinachs
    ReCoSoC
    DOI: 10.1109/ReCoSoC.2016.7533907
    KEYWORDS: fpga, reconfigurable, seu, dynamic reconfiguration, tmr, fault injection
    ABSTRACT: SRAM-Based FPGAs are widely employed in space and avionics computing. The unfriendly environment and FPGA radiation sensibility can have dramatic drawbacks on the application reliability. The partial self-reconfiguration ability gives an excellent aid to counteract single event upsets (SEUs) caused by excessive silicon ionization, and the consequent system misbehavior. Related to this feature, fault injection and fault emulation and configuration scrubbing, has been carried out over three versions of a reconfigurable Fast Fourier Transform (FFT) system: a single FFT, a single larger FFT and a FFT with TMR architecture. The analysis has been focused on multiple injected SEUs scenario, considering the availability problem in a real-time application and highlighting the circuit tolerance at the upset presence. This operation has the goal to emulate as much as possible a real radiation test avoiding all the handicaps that this procedure involves. The obtained results have shown the advantages of the configuration scrubbing performed with the aim to fix multiple upsets, achieving up to 13.6% of circuit hardening. The achieved conclusions are an interesting starting point for the study of fault mitigation techniques through the use of reconfiguration. The projects have been tested on a Z-7010 AP SoC

  30. Analysis of the effects of soft errors on compression algorithms through fault injection inside program variables
    S. Avramenko, M. Reorda, M. Violante, G. Fey
    LATS 2016 - 17th IEEE Latin-American Test Symposium
    DOI: 10.1109/LATW.2016.7483332
    KEYWORDS: electrical and electronic engineering; safety, risk, reliability and quality; hardware and architecture; soft errors; reliability; highlevel fault injection; compression algorithm
    ABSTRACT: Data logging applications, such as those deployed in satellite launchers to acquire telemetry data, may require compression algorithms to cope with large amounts of data as well as limited storage and communication capabilities. When commercial-off-the-shelf hardware components are used to implement such applications, radiation-induced soft errors may occur, especially during the last stages of the launcher cruise, potentially affecting the algorithm execution. The purpose of this work is to analyze two compression algorithms using fault injection to evaluate their robustness against soft errors. The main contribution of the work is the analysis of the compression algorithm susceptibility by attacking their data structures (also referred as program variables) rather than the memory elements of the computing platform in charge of the algorithm execution. This approach is agnostic of the downstream implementation details. Instead, the intrinsic robustness of compression algorithms can be evaluated quickly, and system-level decisions can be taken before the computing platform is finalized

  31. Automatic generation of stimuli for fault diagnosis in IEEE 1687 networks
    R. Cantoro, M. Montazeri, M. Sonza Reorda, F. Zadegan, E. Larsson
    DOI: 10.1109/IOLTS.2016.7604692
    ABSTRACT: The IEEE 1687 standard describes reconfigurable structures allowing to flexibly access the instruments existing within devices (e.g., to support test, debug, calibration, etc.), by the use of configurable modules acting as controllable switches. The increasing adoption of this standard requires the availability of algorithms and tools to automate its usage. Since the resulting networks could inevitably be affected by defects which may prevent their correct usage, solutions allowing not only to test against these defects, but also to diagnose them (i.e., to identify the location of possible faults) are of uttermost importance. This paper proposes a method to automatically generate suitable test stimuli: by applying them and observing the output of the network one can not only detect possible faults, but also identify the fault responsible for the misbehavior. Experimental results gathered on a set of benchmark networks with a prototypical tool implementing the proposed techniques show the feasibility and provide a first idea about the length of the required input stimuli

  32. Challenging Anti-virus Through Evolutionary Malware Obfuscation
    M. Gaudesi, A. Marcelli, E. Sanchez, G. Squillero, A. Tonda
    Challenging Anti-virus Through Evolutionary Malware Obfuscation
    KEYWORDS: security malware packer computational-intelligence evolutionary algorithms
    ABSTRACT: The use of anti-virus software has become something of an act of faith. A recent study showed that more than 80 % of all personal computers have anti-virus software installed. However, the protection mechanisms in place are far less effective than users would expect. Malware analysis is a classical example of cat-and-mouse game: as new anti-virus techniques are developed, malware authors respond with new ones to thwart analysis. Every day, anti-virus companies analyze thousands of malware that has been collected through honeypots, hence they restrict the research to only already existing viruses. This article describes a novel method for malware obfuscation based an evolutionary opcode generator and a special ad-hoc packer. The results can be used by the security industry to test the ability of their system to react to malware mutations

  33. Development of an automated test system for ECU software validation: an industrial experience
    E. Bagalini, M. Violante
    DOI: 10.1109/BEC.2016.7743739
    KEYWORDS: verification; validation; model based software design; hardware-in-the-loop (hil); fault-injection; rapid prototyping; engine test bench; ecu; rapid prototyping; engine test bench; ecu; verification; validation; model based software design; hardware-in-the-loop (hil); fault-injection
    ABSTRACT: Hardware-in-the-loop (HIL) and fault injection testing are widely used in automotive industry to validate hardware and software architectures as best practice and in fulfillment with international functional safety standards. Time and economical investments can constitute an obstacle to the development of effective testing systems, especially for small and medium automotive industries. This paper presents a solution we developed to balance cost with model capabilities and simulation efficiency. The adoption of a model-based approach and the use of a mix of real and emulated sensors and actuators allowed to meet cost and temporal constraints. The presented solution has been developed in six months and is currently adopted to validate new engine control strategies, reducing the testing effort up to 90% compared to manual tests.

  34. Effective generation and evaluation of diagnostic SBST programs
    A. Riefert, R. Cantoro, M. Sauer, M. Reorda, B. Becker
    Proceedings of the IEEE VLSI Test Symposium
    DOI: 10.1109/VTS.2016.7477279
    KEYWORDS: automatic test pattern generation, circuit faults, fault detection, fault diagnosis, interpolation, model checking, program processors
    ABSTRACT: Functional test and software-based self-test (SBST) approaches for processors are becoming popular as they enable low-cost production tests and are often the only solution for in-field tests. With the increasing use of volume diagnosis, efficient and cost-effective diagnosis methods are required. A high quality functional or SBST test program can be used to perform logic fault diagnosis with low-cost test equipment and therefore significantly reduce the cost of diagnosis. We present a framework for the automatic generation of functional diagnostic sequences for stuck-at faults. The framework allows a user to specify constraints imposed by the employed test environment and generates diagnostic sequences satisfying these constraints. Furthermore, the framework is able to prove the equivalence of faults under the specified constraints. This enables to compute the best possible diagnostic quality that can be reached under the given environmental constraints. Also, it gives the necessary information for implementing selective DFT techniques in order to differentiate faults which cannot be distinguished otherwise. In our experiments we evaluated a MIPS-like processor. The results show that our approach can effectively distinguish fault pairs or prove their equivalence, under different environmental constraints. To the best, of our knowledge, this is the first approach which, enables the automatic generation of diagnostic SBST, programs and allows to effectively prove the equivalence of faults in functional and SBST test environments

  35. Eigenwalk: a Novel Feature for Walk Classification and Fall Prediction
    M. Hemmatpour, R. Ferrero, B. Montrucchio, M. Rebaudengo
    KEYWORDS: fall, elderly, health care
    ABSTRACT: Predicting a fall is one of the most promising approaches to avoid it. Different studies strive to classify abnormal and normal walks in order to predict a fall before its occurrence. This study introduces eigenwalk, a novel feature based on the principal components of the accelerometer and gyroscope signals. This feature, in conjunction with a random forest classifier, is able to distinguish walk patterns and to estimate a fall risk. As the accelerometer and the gyroscope embedded in a smartphone are recognized to be precise enough for fall avoidance systems, they have been exploited in an experimental analysis in order to compare the proposed approach with the most recent ones. The results have shown that the new feature in combination with the random forest classification outperforms state-of-the-art approaches, by improving the accuracy up to 98.6%

  36. Evolutionary deckbuilding in hearthstone
    P. Garcia-Sanchez, A. Tonda, G. Squillero, A. Mora, J. Merelo
    Proceedings of Computational Intelligence and Games (CIG), 2016
    DOI: 10.1109/CIG.2016.7860426
    KEYWORDS: crystals; standards; buildings; games; evolutionary computation; artificial intelligence; electronic mail
    ABSTRACT: One of the most notable features of collectible card games is deckbuilding, that is, defining a personalized deck before the real game. Deckbuilding is a challenge that involves a big and rugged search space, with different and unpredictable behaviour after simple card changes and even hidden information. In this paper, we explore the possibility of automated deckbuilding: a genetic algorithm is applied to the task, with the evaluation delegated to a game simulator that tests every potential deck against a varied and representative range of human-made decks. In these preliminary experiments, the approach has proven able to create quite effective decks, a promising result that proves that, even in this challenging environment, evolutionary algorithms can find good solutions.

  37. Exploiting accelerometers to estimate displacement
    R. Ferrero, F. Gandino, M. Hemmatpour, B. Montrucchio, M. Rebaudengo
    KEYWORDS: accelerometer, kalman filter, position tracking, displacement
    ABSTRACT: Although the acceleration is physically related to the displacement of an object, i.e., to its change of position, it is demonstrated that the double integration of the acceleration does not provide accurate information about the displacement, due to the noise and measurement errors. This paper evaluates a correction technique based on the Kalman filter in order to increase the accuracy of the estimation of the displacement. Experiments were performed by acquiring the acceleration with an off-the-shelf accelerometer: the percentage error made by simply integrating the acceleration measurements may arrive to 68% in the general case of a movement in the space, but it can be dramatically reduced to 9% with the proposed approach. An even better behavior is obtained when the movement is constrained to a plane or along an axis

  38. FPGA-controlled PCBA power-on self-test using processor's debug features
    B. Du, E. Sanchez, M. Reorda, J. Acle, A. Tsertov
    Formal Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2016
    DOI: 10.1109/DDECS.2016.7482458
    KEYWORDS: safety, risk, reliability and quality; electrical and electronic engineering; hardware and architecture

  39. Faster-than-at-speed execution of functional programs: an experimental analysis
    P. Bernardi, A. Bosio, G. Natale, A. Guerriero, F. Venini
    IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

  40. Hybrid soft error mitigation techniques for COTS processor-based systems
    E. Chielle, B. Du, F. Kastensmidt, S. Cuenca-Asensi, L. Sterpone, M. Reorda
    LATS 2016 - 17th IEEE Latin-American Test Symposium
    DOI: 10.1109/LATW.2016.7483347
    KEYWORDS: electrical and electronic engineering; safety, risk, reliability and quality; hardware and architecture; watchdog; software-based techniques; soft errors; reliability; performance degradation; memory overhead; fault tolerance; fault coverage; error detection; cots processors; aerospace applications

  41. Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study
    A. Touati, A. Bosio, P. Girard, A. Virazel, P. Bernardi, M. Reorda
    2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
    DOI: 10.1109/ISVLSI.2016.42

  42. In-field functional test programs development flow for embedded FPUs
    R. Cantoro, D. Piumatti, P. Bernardi, S. De Luca, A. Sansonetti
    DOI: 10.1109/DFT.2016.7684079

  43. Kanzi: A Distributed, In-memory Key-Value Store
    M. Hemmatpour, B. Montrucchio, M. Rebaudengo
    KEYWORDS: in-memory key-value store, distributed system, rdma programming, high performance facility
    ABSTRACT: Traditional database systems either sacrifice availability or partitionability at the cost of offering strict consistency guarantee of data. However, the significant growth of Web-scale applications and the wider array of emerging workloads demand revisiting the need for full transactional consistency. One new dominant class of workload is the ability to efficiently support single statement transaction consisting of either Get or Put operation; thus, simplifying the consistency model. These simple workloads have given rise to decade-long efforts for building efficient key-value stores that often rely on disk-resident and log-structured storage model that is distributed across many machines. To further expand the scope of key-value stores, in this paper, we introduce Kanzi, a distributed, in-memory key-value stored over shared-memory architecture enabled by remote direct memory access (RDMA) technology. The simple data and transaction model of our proposed Kanzi additionally may serve as a generic (embedded) caching layer to speed up any disk-resident data-intensive workloads

  44. MPDEA 2016 chairs' welcome & organization
    G. Squillero, A. Tonda
    GECCO 2016 Companion - Proceedings of the 2016 Genetic and Evolutionary Computation Conference
    DOI: 10.1145/2908961.2931650
    KEYWORDS: diversity promotion; evolutionary algorithms; software; computer science applications1707 computer vision and pattern recognition; computational theory and mathematics
    ABSTRACT: n.a.

  45. On the consolidation of mixed criticalities applications on multicore architectures
    S. Esposito, S. Avramenko, M. Violante
    2016 17th Latin-American Test Symposium (LATS)
    DOI: 10.1109/LATW.2016.7483340
    KEYWORDS: hardware, multicore processing, real-time systems, redundancy, software, n-versioning, temporal triple module redundancy (ttmr), triple module redundancy (tmr), fault tolerance, soft errors, software implemented fault tolerance (sift)
    ABSTRACT: Multicore architectures are very appealing as they offer the capability of integrating federated architectures, where multiple independent computing elements are devoted to specific tasks, into a single device, allowing significant mass and power savings. Often, the tasks in the federated architectures are responsible for mixed criticalities tasks, i.e. some of them are mission-/safety-critical real-time tasks, while others are non-critical tasks. When consolidating mixed criticalities tasks on multicore architectures, designers must guarantee that each core does not interfere with the others, introducing side effects not possible in federated architectures. In this paper we propose a hybrid solution based on a combination of known techniques: lightweight hardware redundancy, implemented using smart watchdogs and voter logic, cooperates with software redundancy, implemented using software temporal triple module redundancy for those tasks with low criticality and no real-time requirement, and software triple module redundancy for tasks with high criticality and real-time requirement. To guarantee lack of interference, a hypervisor is used to segregate the execution of each task in a dedicated resource partition. Preliminary experimental results are reported on a prototypical vision-based navigation system

  46. On the diagnostic analysis of IEEE 1687 networks
    R. Cantoro, M. Montazeri, M. Reorda, F. Zadegan, E. Larsson
    DOI: 10.1109/ETS.2016.7519294
    KEYWORDS: ijtag, scan networks, testing, diagnosis
    ABSTRACT: The IEEE 1687 standard describes reconfigurable structures allowing to flexibly access the instruments existing within devices (e.g., to support test, diagnosis, calibration, etc.), by using configuration modules which act as controllable switches. The increasing adoption of this standard requires the availability of algorithms and tools to automate its usage. The resulting networks might be affected by defects preventing their correct operation. This necessitates the availability of solutions which allow not only to test against defects, but also to identify the location of possible faults via diagnosis. This paper for the first time addresses the problem of the diagnosis of IEEE 1687 networks. Experimental results gathered on a set of benchmark networks show the feasibility of the solution and provide a first idea about the length of the required input stimuli

  47. On the robustness of DCT-based compression algorithms for space applications
    S. Avramenko, M. Sonza Reorda, M. Violante, G. Fey, Mess,Jan-Gerd, R. Schmidt
    IEEE International Symposium on On-Line Testing and Robust System Design
    DOI: 10.1109/IOLTS.2016.7604656
    KEYWORDS: soft errors; lossy compression algorithm; discrete cosine transform; reliability; register-level fault injection; commercial off-the-shelf
    ABSTRACT: High compression ratio is crucial to cope with the large amounts of data produced by telemetry sensors and the limited transmission bandwidth typical of space applications. A new generation of telemetry units is under development, based on Commercial Off-The-Shelf (COTS) components that may be subject to misbehaviors due to radiation-induced soft errors. The purpose of this paper is to study the impact of soft errors on different configurations of a discrete cosine transform (DCT)-based compression algorithm. This work's main contribution lies in providing some design guidelines

  48. Online Time Interference Detection in Mixed-Criticality Applications on Multicore Architectures using Performance Counters
    S. Esposito, M. Violante, M. Sozzi, M. Terrone, M. Traversone
    22nd IEEE International Symposium on On-Line Testing and Robust System Design
    KEYWORDS: hard real-time; safety critical applications; performance counters; fault detection; mixed-criticalities; multicore processing
    ABSTRACT: In this paper a novel technique is proposed for online detection of timing interference in multicore architectures. The technique is aimed at mixed-criticality workloads. This paper describes a method to use hardware performance counters to detect such misbehaviors. Experimental data is gathered, showing the viability of this method. The method can be used as safety-net in several scheduling approaches

  49. Portfolio Optimization, a Decision-Support Methodology for Small Budgets
    I. Deplano, G. Squillero, A. Tonda
    Applications of Evolutionary Computation
    DOI: 10.1007/978-3-319-31204-0_5
    KEYWORDS: portfolio optimization; portfolio model; financial forecasting; mlp; multi-objective optimization; som; artificial neural networks
    ABSTRACT: Several machine learning paradigms have been applied to financial forecasting, attempting to predict the market's behavior, with the final objective of profiting from trading shares. While anticipating the performance of such a complex system is far from trivial, this issue becomes even harder when the investors do not have large amounts of money available. In this paper, we present an evolutionary portfolio optimizer for the management of small budgets. The expected returns are modeled resorting to Multi-layer Perceptrons, trained on past market data, and the portfolio composition is chosen by approximating the solution to a multi-objective constrained problem. An investment simulator is then used to measure the portfolio performance. The proposed approach is tested on real-world data from Milan stock exchange, exploiting information from January 2000 to June 2010 to train the framework, and data from July 2010 to August 2011 to validate it. The presented tool is finally proven able to obtain a more than satisfying profit for the considered time frame

  50. Promoting diversity in evolutionary algorithms: An updated bibliography
    G. Squillero, A. Tonda
    GECCO 2016 Companion - Proceedings of the 2016 Genetic and Evolutionary Computation Conference
    DOI: 10.1145/2908961.2931651
    KEYWORDS: evolutionary algorithms; software; computer science applications1707 computer vision and pattern recognition; computational theory and mathematics; diversity promotion
    ABSTRACT: This short paper contains an extended list of references to diversity preservation methodologies, classified following the taxonomy presented in a previous publication. The list has been updated according to the contributions sent to the workshop "Measuring and Promoting Diversity in Evolutionary Computation", held during the conference GECCO 2016.

  51. Rejuvenation of nbti-impacted processors using evolutionary generation of assembler programs
    F. Pellerey, M. Jenihhin, G. Squillero, J. Raik, M. Sonza Reorda, V. Tihhomirov, R. Ubar
    Proceedings of the Asian Test Symposium
    DOI: 10.1109/ATS.2016.57
    KEYWORDS: hardware rejuvenation; nbti; processor designs; electrical and electronic engineering; aging; critical path identification; evolutionary computation
    ABSTRACT: The time-dependent variation caused by Negative Bias Temperature Instability (NBTI) is agreed to be one of the main reliability concerns in integrated circuits implemented with current nanotechnology nodes. NBTI increases the threshold voltage of pMOS transistors: hence' it slows down signal propagation along logic paths between flip-flops. It may cause intermittent faults and' ultimately' permanent functional failures in processor circuits. In this paper' we study an NBTI mitigation approach in processor designs by rejuvenation of pMOS transistors along NBTI-critical paths. The method incorporates hierarchical fast' yet accurate modelling of NBTI-induced delays at transistor' gate and path levels for generation of rejuvenation Assembler programs using an Evolutionary Algorithm. These programs are applied further as an execution overhead to drive those pMOS transistors to the recovery phase' which are the most critical for the NBTI-induced path delay in processors. The experimental results demonstrate efficiency of evolutionary generation and significant reduction of NBTI-induced delays by the rejuvenation stimuli with an execution overhead of 0.1% or less. The proposed approach aims at extending the reliable lifetime of nanoelectronic processors.

  52. Scalable FPGA Graph model to detect routing faults
    L. Sterpone, G. Cabodi, S. Finocchiaro, C. Loiacono, F. Savarese, B. Du
    IEEE International Symposium on On-Line Testing and Robust System Design
    DOI: 10.1109/IOLTS.2016.7604690
    KEYWORDS: measurement; field programmable gate arrays; circuit faults; routing; integrated circuit modeling; computational modeling; integrated circuit interconnections
    ABSTRACT: The SRAM cells that form the configuration memory of an SRAM-based FPGA make such FPGAs particularly vulnerable to soft errors. A soft error occurs when ionizing radiation corrupts the data stored in a circuit. The error persists until new data is written. Soft errors have long been recognized as a potential problem as radiation can come from a variety of sources. This paper presents an FPGA fault model focusing on routing aspects. A graph model of SRAM nodes behavior in case of fault, starting from netlist description of well known FPGA models, is presented. It is also performed a classification of possible logical effects of a soft error in the configuration bit controlling, providing statistics on the possible numbers of faults. Finally it is reported the definition of fault metrics computed on a set of complex benchmarks proving the effectiveness of our approach.

  53. Test Time Minimization in Reconfigurable Scan Networks
    R. Cantoro, M. Palena, P. Pasini, M. Sonza Reorda
    ABSTRACT: Modern devices often include several embedded instruments, such as BISTs, sensors, and other analog components. New standards, such as IEEE Std. 1687, provide vehicles to access these instruments. In approaches based on reconfigurable scan networks, instruments are coupled with scan registers, connected into chains and interleaved with reconfigurable multiplexers, permitting a selective access to different parts of the chain. A similar scenario is also supported by IEEE Std. 1149.1-2013, where a test data register can be constructed as a chain of multiple segments, some of which can be excluded or mutually selected. The test of permanent faults affecting a reconfigurable scan network requires to shift test patterns throughout a certain number of network configurations. This paper presents a method to select the list of configurations needed to apply the complete test set in the minimum amount of clock cycles. The method is based on a graph representation of the problem. Experimental results on some benchmark networks are provided, together with a comparison with other approaches based on heuristics. The provided results can be effectively used to evaluate the test time of sub-optimal approaches.

  54. Thermal issues in test: An overview of the significant aspects and industrial practice
    J. Alt, P. Bernardi, A. Bosio, R. Cantoro, H. Kerkhoff, A. Leininger, W. Molzer, A. Motta, C. Pacha, A. Pagani, A. Rohani, R. Strasser
    Proceedings of the IEEE VLSI Test Symposium
    DOI: 10.1109/VTS.2016.7477278
    KEYWORDS: automotive; component; functional test; thermal-aware test; yield
    ABSTRACT: Thermal phenomena occurring along test execution at the final stages of the manufacturing flow are considered as a significant issue for several reasons, including dramatic effects like circuit damage that is leading to yield loss. This paper tries to redeem those bad guys in order to exploit them to improve the test quality, reducing the overall test cost without affecting the yield

  55. Tutorials at PPSN 2016
    C. Doerr, N. Bredeche, E. Alba, T. Bartz-Beielstein, D. Brockhoff, B. Doerr, G. Eiben, M. Epitropakis, C. Fonseca, A. Guerreiro, E. Haasdijk, J. Heinerman, J. Hubert, P. Lehre, L. Malagò, J. Merelo, J. Miller, B. Naujoks, P. Oliveto, S. Picek, N. Pillay, M. Preuss, P. Ryser-Welch, G. Squillero, J. Stork, D. Sudholt, A. Tonda, D. Whitley, M. Zaefferer
    Parallel Problem Solving from Nature - PPSN XIV
    DOI: 10.1007/978-3-319-45823-6_95
    ABSTRACT: PPSN 2016 hosts a total number of 16 tutorials covering a broad range of current research in evolutionary computation. The tutorials range from introductory to advanced and specialized but can all be attended without prior requirements. All PPSN attendees are cordially invited to take this opportunity to learn about ongoing research activities in our field!

  56. baseline walking dataset exploiting accelerometer and gyroscope for fall prediction and prevention systems
    M. Hemmatpour, R. Ferrero, B. Montrucchio, M. Rebaudengo
    KEYWORDS: fall, prevention, healthcare, body monitoring
    ABSTRACT: Fall datasets usually record normal activities and transitions from one posture to another one with falls. Many fall detection datasets based on different sensors are adopted by researchers to improve their systems. Although fall avoidance are dramatically increasing, a public fall prediction and prevention dataset based on an accelerometer and gyroscope is absent. So, this study creates a dataset based on the state-of-the-art techniques in simulating a fall. Different techniques are evaluated to find the best fall simulation. Since accelerometer and gyroscope sensors embedded in a smartphone are recognized to be suited for fall avoidance systems, in this study, they are used to obtain data from users. At the end, some statistical analysis of the observed data are presented and a nonlinear regression model is proposed

  57. A novel simulator for RFID reader-to-reader anti-collision protocols
    R. Ferrero, F. Gandino, B. Montrucchio, M. Rebaudengo, L. Zhang
    ABSTRACT: Reader-to-reader interference affects the simultaneous activity of the readers in an RFID system: the collisions among the readers penalize the throughput and the reliability of the application. Many reader-to-reader anti-collision protocols have been proposed to address this issue. Their performance is generally evaluated by means of simulations. For this purpose, a generic simulator of wireless networks is exploited in most of the cases. This paper proposes a novel simulator, which is customized to the characteristics of the RFID technology in order to speed up the evaluation of anti-collision protocols. The simulator is based on OMNeT++ and it adds new ad-hoc facilities, such as the implementation of the existing reader-to-reader anti-collision protocols and a modular architecture for rapidly developing and testing new ones

  58. About the functional test of permanent faults in distributed systems
    A. Vaskova, M. Portela-García, C. López-Ongil, E. Sanchez Sanchez, M. Sonza Reorda
    2015 Conference on Design of Circuits and Integrated Systems (DCIS)
    DOI: 10.1109/DCIS.2015.7388571
    ABSTRACT: The effects of permanent faults, arising along working life of digital electronic systems, may impact their reliability and performance. In-field test may help to detect these faults and to prevent serious effects in safety-critical applications. Distributed electronic systems introduce further complexity in this scenario, as the low observability and the lack of maintenance make difficult the detection as well as the identification of failing elements and their repairing. Functional workloads are often used for on-line tests of distributed systems to detect permanent faults. Suitable techniques for test generation and early identification of functionally untestable permanent faults are critical issues that are faced in this work

  59. An Evolutionary Approach for Test Program Compaction
    R. Cantoro, M. Gaudesi, E. Sanchez, P. Schiavone, G. Squillero
    campo non avvalorato
    DOI: 10.1109/LATW.2015.7102406
    KEYWORDS: on-line test; software based self testing; computational intelligence
    ABSTRACT: Abstract— The increasing complexity of electronic components based on microprocessors and their use in safety-critical application - like automotive devices - make reliability a critical aspect. During the life cycle of such products, it is needed to periodically check whether the processor cores are working correctly. In most cases, this task is performed by running short, fast and specialized test programs that satisfies in-field testing requirements. This paper proposes a method that exploits an evolutionary-computation technique for the automatic compaction of these in-field oriented test programs. The aim of the proposed approach is twofold: reduce execution time and memory occupation, while maintaining the fault coverage of the original test program. Experimental results gathered on miniMIPS, a freely available 5-stage pipelined processor core, demonstrate the effectiveness of the proposed technique

  60. An Hybrid Architecture for consolidating mixed criticality applications on multicore systems
    S. Avramenko, S. Esposito, M. Violante, M. Sozzi, M. Traversone, M. Binello, M. Terrone
    Proceedings on the IEEE International On-Line Testing Symposium
    DOI: 10.1109/IOLTS.2015.7229823

  61. An effective ATPG flow for Gate Delay Faults
    A. Bosio, L. Dilillo, P. Girard, A. Virazel, P. Bernardi, M. Sonza Reorda
    10th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2015
    DOI: 10.1109/DTIS.2015.7127350
    ABSTRACT: This paper proposes a novel approach for the generation of test patterns suitable for detecting Gate Delay Faults (GDFs). The key idea lies in associating any single Gate Delay Fault to a set of Transition Delay (TD) Faults, and exploiting this relationship to produce effective patterns. The approach encompasses several steps: once a Gate Delay Fault is translated into a set of equivalent Transition Delay Faults, a traditional ATPG procedure can be used to determine patterns without any explicit timing information. The latter may account for several iterations, and it is returning the minimum delay that is detected for each delay faults. Effectiveness and feasibility of the proposed ATPG flow have been demonstrated on ISCAS'89 and ITC'99 benchmarks

  62. An innovative parallel fuzzy scheme for low-power consumption in IEEE 802.11 devices
    M. Collotta, S. Tirrito, R. Ferrero, M. Rebaudengo
    DOI: 10.1109/INDIN.2015.7281856
    ABSTRACT: Wireless devices are mainly used in mobile systems because they do not need any physical connection for the communication and the energy supply. Therefore, reducing the power consumption of their batteries is a critical task in order to prolong their lifetime. The main aim of this paper is to dynamically adjust both the sleeping time and the transmission power of mobile devices in an IEEE 802.11 wireless network in order to reduce the power consumption. The algorithm runs on the access point that provides the wireless connection to the devices, so no extra circuitry or computation is required to the devices. The proposal is validated through simulations, which show a battery life 20% higher than other state-of-the-art approaches

  63. Analysis and mitigation of SEUs in ARM-based SoC on Xilinx Virtex-V SRAM-based FPGAS
    B. Du, M. Desogus, L. Sterpone
    2015 11th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2015
    DOI: 10.1109/PRIME.2015.7251378
    KEYWORDS: fpga; radiation experiment; single event effects; sopc; electrical and electronic engineering

  64. Black Holes and Revelations: Using Evolutionary Algorithms to Uncover Vulnerabilities in Disruption-Tolerant NetworksApplications of Evolutionary Computation
    D. Bucur, G. Iacca, G. Squillero, A. Tonda
    Lecture Notes in Computer ScienceApplications of Evolutionary Computation
    DOI: 10.1007/978-3-319-16549-3_3
    ABSTRACT: A challenging aspect in open ad hoc networks is their resilience against malicious agents. This is especially true in complex, urban-scale scenarios where numerous moving agents carry mobile devices that create a peer-to-peer network without authentication. A requirement for the proper functioning of such networks is that all the peers act legitimately, forwarding the needed messages, and concurring to the maintenance of the network connectivity. However, few malicious agents may easily exploit the movement patterns in the network to dramatically reduce its performance. We propose a methodology where an evolutionary algorithm evolves the parameters of different malicious agents, determining their types and mobility patterns in order to minimize the data delivery rate and maximize the latency of communication in the network. As a case study, we consider a fine-grained simulation of a large-scale disruption-tolerant network in the city of Venice. By evolving malicious agents, we uncover situations where even a single attacker can hamper the network performance, and we correlate the performance decay to the number of malicious agents

  65. Chromatic Selection - An Oversimplified Approach to Multi-objective OptimizationApplications of Evolutionary Computation
    G. Squillero
    Lecture Notes in Computer ScienceApplications of Evolutionary Computation
    DOI: 10.1007/978-3-319-16549-3_55
    ABSTRACT: This short paper introduces the chromatic selection, a simple technique implementable with few tens of lines of code, that enable handling multi-value fitness functions with a single-objective evolutionary optimizer. The chromatic selection is problem independent, requires no parameter tuning, and can be used as a drop-in replacement for both parent and survival selections. The resulting tool will not be a full-fledged multi-objective optimizer, lacking the ability to manage Pareto fronts, but it will efficiently seek a single, reasonable, compromise solution. In several practical problems, the time saved, both in computation and development, could represent a substantial advantage

  66. Design Space Exploration and Optimization of a Hybrid Fault-Tolerant Architecture
    Wali,I., A. Virazel, A. Bosio, P. Girard, M. Sonza Reorda
    21st IEEE International On-Line Testing Symposium
    KEYWORDS: fault tolerance, redundancy, transient and permanent faults, power consumption
    ABSTRACT: Fault-tolerant architectures have been widely used in industry to prevent circuit reliability from becoming a bottleneck for the development of robust high-performance and low-power systems. One such solution is a Hybrid Fault-Tolerant Architecture that offers benefits such as low power and lifetime reliability improvement. However, it has been identified that there is room of improvement in efficiency. Thus, in this paper we present design space exploration and optimization of the Hybrid Fault-Tolerant Architecture. The study involves application of four design variants to some ITC benchmark circuits as case study. Experimental results compare the initial and optimized designs and show that the proposed optimizations offer around 65% reduction in terms of area, about 55% power saving and 87% less performance overhead as compared to the initial design without any penalty of the fault tolerance capability

  67. Evaluation of error effects on a biomedical system
    B. Enea, V. Massimo, H. Hakob
    Proceedings of IEEE East-West Design & Test Symposium (EWDTS'2015)
    DOI: 10.1109/EWDTS.2015.7493164
    KEYWORDS: reliability, safety-critical, model-based, fault injection, biomedical system modeling
    ABSTRACT: The evaluation of the reliability of a safety-critical system in the design phase is crucial as it allows to strengthen the weaknesses of products prior to the production phase, when the countermeasures could be expensive and/or ineffective. In some domains, it is common to adopt a design flow exploiting a high-level description of the system behavior and architecture from which the software, and eventually the hardware, can be automatically generated. In this paper we applied the concept to the design of a pacemaker. Starting from a high-level model, by exploiting automatic code generation, we derived the C code implementing the pacemaker functionality, then we evaluated its robustness against transient errors that may affect the computing resources used to execute the generated code. When compared to previous works that focused on reliability analysis of the pacemaker high-level model, only, this paper highlights the importance of considering both the high-level model, and the corresponding implementation in C code to allows for accurate and comprehensive reliability analysis

  68. Experimental Investigation on the Interference between UHF RFID and GSM
    R. Ferrero, F. Gandino, B. Montrucchio, M. Rebaudengo
    ABSTRACT: Radio Frequency Identification (RFID) is a widely employed technology for automatic identification. However, it is affected by some interference issues. This paper is focused on the interference between Ultra high frequency (UHF) RFID systems and devices that communicate according to the Global System for Mobile Communications (GSM) standard. Since the GSM and the UHF RFID frequency bands are close, the mobile phones communication can affect the efficiency of RFID systems. In this paper, an experimental analysis on the interference between GSM and UHF RFID is presented. The results of the experimentation highlight the negative effects of the use of GSM devices in the proximity of operating UHF RFID systems. Moreover, the main elements that should be taken into account during the design of an RFID system that works in the same area with GSM devices are identified

  69. Exploiting Evolutionary Computation in an Industrial Flow for the Development of Code-Optimized Microprocessor Test Programs
    R. Cantoro, M. Gaudesi, E. Sanchez, G. Squillero
    Proceedings of the Companion Publication of the 2015 on Genetic and Evolutionary Computation Conference
    DOI: 10.1145/2739482.2764673
    KEYWORDS: software-based self-test, testing, evolutionary computation
    ABSTRACT: It is well-known that faults affecting an electronic device may compromise its correct functionality, and industries have to check that their devices are fault-free before selling them. In case of a processor core, this task may be accomplished by running specially written "test" programs. In industrial embedded applications, however, shrinking such programs is strictly required. The hard problems of generating and code-optimizing test programs are tackled in this paper by exploiting an evolutionary approach

  70. Exploring the Impact of Functional Test Programs Re-Used for Power-Aware Testing
    A. Touati, A. Bosio, L. Dilillo, P. Girard, A. Virazel, P. Bernardi, M. Sonza Reorda
    Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015
    KEYWORDS: power aware test, functional and structural test, microprocessor test, atpg
    ABSTRACT: High power consumption during at-speed delay fault testing may lead to yield loss and premature aging. On the other hand, reducing too much test power might lead to test escape and reliability problems. Thus, to avoid these issues, test power has to map the power consumed during functional mode. Existing works target the generation of functional test programs able to maximize the power consumption in functional mode of microprocessor cores. The obtained power consumption will be used as threshold to tune the power consumed during testing. This paper investigates the impact of re-using such functional test programs for testing purposes. We propose to apply them by exploiting existing DfT architecture to maximize the delay fault coverage. Then, we combine them with the classical at-speed LOC and LOS delay fault testing schemes to further increase the fault coverage. Results show that it is possible to achieve a global test solution able to maximize the delay fault coverage while respecting the functional power budget

  71. In-field test of safety-critical systems: is functional test a feasible solution?
    M. Sonza Reorda
    2015 16th IEEE Latin-American Test Symposium (LATS)
    DOI: 10.1109/LATW.2015.7102528
    ABSTRACT: The growing usage of electronic systems in safety- and mission-critical applications, together with the increased susceptibility of electronic devices to faults arising during the operational phase mandate for the availability of effective solutions able to face the effects of these faults. When the target system includes a processor, one possible solution is based on running suitable test programs able to detect the occurrence of faults. This solution provides several advantages (e.g., in terms of flexibility, IP protection, and defect coverage), although it is limited by the cost for developing the test programs. This paper overviews the state of the art in the area, and discusses the trends in the area

  72. Malware Obfuscation through Evolutionary Packers
    M. Gaudesi, A. Marcelli, E. Sanchez, G. Squillero, A. Tonda
    Proceedings of the Companion Publication of the 2015 Annual Conference on Genetic and Evolutionary Computation
    DOI: 10.1145/2739482.2764940
    KEYWORDS: evolutionary computation, virus
    ABSTRACT: A malicious botnet is a collection of compromised hosts coordinated by an external entity. The malicious software, or malware, that infect the systems are its basic units and they are responsible for its global behavior. Anti Virus software and Intrusion Detection Systems detect botnets by analyzing network and files, looking for signature and known behavioral patterns. Thus, the malware hiding capability is a crucial aspect. This paper describes a new obfuscation mechanism based on evolutionary algorithms: an evolutionary core is embedded in the malware to generate a different, optimized hiding strategy for every single infection. Such always-changing, hard-to-detect malware can be used by security industries to stress the analysis methodologies and to test the ability to react to malware mutations. This research is the first step in a more ambitious research project, where a whole botnet, composed of different malware and Anti Virus software, is analyzed as a prey-predator ecosystem

  73. Observability solutions for in-field functional test of processor-based systems
    J. Perez Acle, R. Cantoro, A. Hailemichael, E. Sanchez, M. Sonza Reorda
    KEYWORDS: microprocessor testing, software-based self-test
    ABSTRACT: The growing usage of electronic systems in safety-critical applications requires effective solutions to early identify possible faults affecting the hardware while it is in the operational phase. A possible approach leverages functional programs to be run by the CPU typically existing in such systems. These programs must exercise the different parts of the system, and produce a behavior different than the normal one in case of faults. However, their effectiveness depends on the adopted observation mechanism, which is deeply affected by the constraints imposed by the in-field application environment. This paper first describes different mechanisms for supporting the observation of possible fault effects; then, it reports and discusses the results of an experimental analysis performed on a multicore system, based on a representative pipelined processor. The gathered results allow to quantitatively evaluate the drop in fault coverage coming from the adoption of the different observation solutions with respect to the ideal case, and thus to better evaluate the advantages/disadvantages they provide

  74. On Test Program Compaction
    M. Gaudesi, M. Sonza Reorda, I. Pomeranz
    campo non avvalorato
    DOI: 10.1109/ETS.2015.7138771
    KEYWORDS: test program generation
    ABSTRACT: While compaction of binary test sequences for generic sequential circuits has been widely explore, the compaction of test programs for processor based systems is still an open area of research. Test program compaction is practically important because there are several scenarios in which Software-based Self-Test (SBST) is adopted, and the size of the test program is often a critical parameter. This paper is among the first to propose algorithms able to automatically compact an existing test program. The proposed solution is based on instruction removal and restoration, which is shown to significantly reduce the computational cost compared with instruction removal alone. Experimental results are reported, showing the compaction capabilities and computational costs of the proposed algorithms

  75. On gait recognition with smartphone accelerometer
    R. Ferrero, F. Gandino, B. Montrucchio, M. Rebaudengo, A. Velasco, I. Benkhelifa
    DOI: 10.1109/MECO.2015.7181946
    KEYWORDS: gait analysis; biometric authentication; mobile phone; 3-axis accelerometer
    ABSTRACT: Besides revealing useful information, like gender, age, existing impairments, the gait of every person is acknowledged to be so distinctive to allow the personal identification and it is regarded as a valid biometric authentication, similarly to fingerprinting and face recognition. Although the first analyses on the gait were conducted in laboratories with dedicated equipment, portable sensors have been exploited as they become available thanks to the technology miniaturization. Aiming at an even more unobtrusive analysis, recent proposals rely on the data acquired from the 3-axis accelerometer embedded in most of the smartphones commercially available on the market. Nevertheless the analysis must be tailored to the lower-grade accelerometer and the limited computational capability of the smartphone. This paper identifies the guidelines that the state-of-the-art research proposes for the gait recognition through a smartphone and discusses the procedures that are found as more appropriate

  76. On the Automatic Generation of SBST Test Programs for In-Field Test
    A. Riefert, R. Cantoro, M. Sauer, M. Sonza Reorda, B. Becker
    Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE)
    DOI: 10.7873/DATE.2015.0271
    KEYWORDS: atpg; software based self testing; test programs
    ABSTRACT: Software-based self-test (SBST) techniques are used to test processors against permanent faults introduced by the manufacturing process (often as a complementary approach with respect to DfT) or to perform in-field test in safety-critical applications. A major obstacle to their adoption is the high cost for developing effective test programs, since there is still a lack of suitable EDA algorithms and tools able to automatically generate SBST test programs. An efficient ATPG algorithm can serve as the foundation for the automatic generation of SBST test programs. In this work we first highlight the additional constraints characterizing SBST test programs wrt functional ones, with special emphasis on their usage for in-field test; then, we describe an ATPG framework targeting stuck-at faults based on Bounded Model Checking. The framework allows the user to exibly specify the requirements of SBST test programs in the considered scenario. Finally, we demonstrate how a set of properly chosen requirements can be used to generate test programs matching these constraints. In our experiments we evaluate the framework with the miniMIPS microprocessor. The results show that the proposed method is the first able to automatically generate SBST test programs whose fault efficiency is superior to those produced with state-of-the-art manual approaches

  77. On the Design of Highly Reliable System-on-Chip using Dynamically Reconfigurable FPGAs
    C. David Merodio, B. Du, L. Sterpone, L. Venditti
    Titolo non avvalorato
    DOI: 10.1109/ReCoSoC.2015.7238082
    KEYWORDS: sram chips field programmable gate arrays logic design radiation hardening (electronics) system-on-chip
    ABSTRACT: Radiation-induced Soft Errors are widely known since the advent of dynamic RAM chips. Reconfigurable FPGA devices based on SRAM configuration memories are extremely sensitive to these effects resulting in an unwelcome change of behavior in digital logic. Indeed, soft errors occur today as a result of radiation from space or even at sea level. Detection, protection and mitigation of soft errors beyond aerospace and defence applications have been widely debated over the last decades. In the present paper we provide a complete design flow illustrating the proper design rules ranging from the synthesis, mapping and physical place and route algorithm tailored to the implementation of high performance and reliable SoCs using dynamic-reconfiguration oriented SRAM-based FPGAs. Radiation experimental results obtained radiation test performed using proton particles demonstrated the goodness of our developed design flow resulting in an overall error cross-section reduction of more than 2 orders of magnitude

  78. On the Functional Test of the Cache Coherency Logic in Multi-core Systems
    J. Perez Acle, R. Cantoro, E. Sanchez, M. Sonza Reorda
    DOI: 10.1109/LASCAS.2015.7250453
    KEYWORDS: futional testing; multicore testng; cache cncy logic; sbst
    ABSTRACT: Multi-core systems are becoming particularly common, due to the high performance they can deliver. Higher, their performance strongly depends on the availability of effective cache controllers, able to guarantee (among others) the coherence of the caches of the different cores. This paper proposes a method for the test of the cache coherence logic existing within each core in a multi-core system, resorting to a functional approach; this means that the method is based on the generation of a suitable test program, to be run in a coordinated manner on the cores composing the system. The method is able to detect hardware defects affecting this logic. We validated our method on a LEON3 multicore system

  79. On the Maximization of the Sustained Switching Activity in a Processor
    R. Cantoro, M. Sonza Reorda, A. Rohani, H. Kerkhoff
    21st IEEE International On-Line Testing Symposium
    KEYWORDS: switching activity, burn-in, aging
    ABSTRACT: Recently, several application areas in the test domain (e.g., burn-in and aging monitoring) started to require suitable input stimuli, able to maximize the switching activity of a certain module for a certain period of time. If the module is part of a processor, this turns into identifying a suitable sequence of instructions, able to maximize the switching activity. This paper proposes a method to attack this problem, and reports some experimental results gathered on a MIPS-like pipelined processor

  80. On the Testability of IEEE 1687 Networks
    R. Cantoro, M. Montazeri, M. Sonza Reorda, F. Ghani Zadegan, E. Larsson
    DOI: 10.1109/ATS.2015.7447934
    KEYWORDS: ijtag, ieee 1687, testing, scan chains
    ABSTRACT: Due to the increasing usage of embedded instruments in many electronic devices, new solutions to effectively access these instruments appeared, including the new IEEE 1687 standard. The approach supported by IEEE 1687 allows a flexible access to embedded instruments through the Boundary Scan interface. The IEEE 1687 network includes a set of reconfigurable scan chains. This paper addresses the issue of testing the circuitry implementing them, checking whether any permanent hardware fault exists, affecting either the registers associated to the instruments made accessible by the network, or the configuration structures it embeds (e.g., the multiplexers and the associated flip-flops). The paper proposes an approach, in which the IEEE 1687 network undergoes a sequence of test sessions, each composed of a configuration phase and a test phase. By properly selecting the network configurations to be used, we can guarantee that the method can test any permanent fault possibly affecting the network. We also provide some experimental results gathered on a set of benchmark networks, allowing to practically evaluate the viability of the approach

  81. On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors
    H. Ghasemzadeh, P. Gaillardon, J. Zhang, G. De Micheli, E. Sanchez, M. Reorda
    Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
    DOI: 10.1109/ISVLSI.2015.13
    KEYWORDS: controllable-polarity transistors; fault model; fault-tolerant adder; hardware and architecture; control and systems engineering; electrical and electronic engineering

  82. On the design of distributed air quality monitoring systems
    A. Velasco, R. Ferrero, F. Gandino, B. Montrucchio, M. Rebaudengo
    KEYWORDS: air pollutants; wireless sensor network; pervasive monitoring
    ABSTRACT: Nowadays, the air quality is considered a key point, and its monitoring is not only suggested but it is even required in many countries. Since traditional standard monitors for air quality are very expensive, the use of a low-cost distributed network of sensors represents a valid complementary approach. This paper discusses the benefits of a distributed approach and analyzes the main elements that should be taken into account during the design of a distributed system for the air quality monitoring. This paper aims at representing a valuable aid for researchers and practitioners interested in the topic

  83. Operator Selection using Improved Dynamic Multi-Armed Bandit
    J. Belluz, M. Gaudesi, G. Squillero, A. Tonda
    GECCO '15 Proceedings of the 2015 on Genetic and Evolutionary Computation Conference
    DOI: 10.1145/2739480.2754712
    ABSTRACT: Evolutionary algorithms greatly benefit from an optimal application of the different genetic operators during the optimization process: thus, it is not surprising that several research lines in literature deal with the self-adapting of activation probabilities for operators. The current state of the art revolves around the use of the Multi-Armed Bandit (MAB) and Dynamic Multi-Armed bandit (D-MAB) paradigms, that modify the selection mechanism based on the rewards of the different operators. Such methodologies, however, update the probabilities after each operator's application, creating possible issues with positive feedbacks and impairing parallel evaluations, one of the strongest advantages of evolutionary computation in an industrial perspective. Moreover, D-MAB techniques often rely upon measurements of population diversity, that might not be applicable to all real-world scenarios. In this paper, we propose a generalization of the D-MAB approach, paired with a simple mechanism for operator management, that aims at removing several limitations of other D-MAB strategies, allowing for parallel evaluations and self-adaptive parameter tuning. Experimental results show that the approach is particularly effective with frameworks containing many different operators, even when some of them are ill-suited for the problem at hand, or are sporadically failing, as it commonly happens in the real world

  84. Permanent Fault Detection and Diagnosis in the Lightweight Dual Modular Redundancy Architecture
    R. Ferreira, E. Sanchez, J. Da Rolt, G. Nazar, A. Moreira, L. Carro, M. Sonza Reorda
    KEYWORDS: modular redundancy; error detection; reliable architecture

  85. Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG
    N. Palermo, V. Tihhomirov, T. Copetti, M. Jenihhin, J. Raik, S. Kostin, M. Gaudesi, G. Squillero, M. Reorda, F. Vargas, L. Poehls
    2015 16th Latin-American Test Symposium, LATS 2015
    DOI: 10.1109/LATW.2015.7102405
    KEYWORDS: aging; critical path identification; evolutionary computation; hardware rejuvenation; logic circuit; microgp; nbti; zamiacad; hardware and architecture; electrical and electronic engineering; computer science applications1707 computer vision and pattern recognition; software; control and systems engineering; safety, risk, reliability and quality
    ABSTRACT: One of the main reliability concerns in the nanoscale logic is the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). It increases the threshold voltage of pMOS transistors, which slows down signal propagation along the paths between flip-flops. As a consequence, NBTI may cause transient faults and, ultimately, permanent circuit functional failure. In this paper, we propose an innovative NBTI mitigation approach by rejuvenation of nanoscale logic along NBTI-critical paths. The method is based on hierarchical NBTI-critical paths identification and rejuvenation stimuli generation using an Evolutionary Algorithm. The rejuvenation stimuli are used to drive to the recovery phase the pMOS transistors that are the most significant for the NBTI-induced path delay. This rejuvenation procedure is to be applied to the circuit as an execution overhead at predefined periods. The proposed approach is aimed at extending the reliable lifetime of nanoelectronics. Experimental results are demonstrated by electrical simulations of an ALU circuit design

  86. SET-PAR: Place and Route Tools for the Mitigation of Single Event Transients on Flash-Based FPGAs
    B. L. Sterpone
    Applied Reconfigurable Computing
    DOI: 10.1007/978-3-319-16214-0_11
    KEYWORDS: fault tolerance; reconfigurable; radiation effects; test; fpga; place and route

  87. SW-Based Transparent In-Field Memory Testing
    P. Bernardi, L. Ciganda, M. Sonza Reorda, S. Hamdioui
    16th IEEE Latin American Test Symposium
    ABSTRACT: With continuous technology scaling, both quality and reliability are becoming major concerns for ICs due to extreme variations, non-ideal voltage scaling, etc. (not to mention the business pressure leading to shorter-time to market). One-time-factory manufacturing test is not sufficient anymore, and in-field testing (e.g., periodically, at power-on, during idle times) is becoming mandatory. Due to the strict constraints of in-field test, transparent BIST is extremely attractive, since it allows to minimize test invasiveness. This paper presents a cheap, high quality and practical SW-based transparent in-field test approach for memories within a system. Instead of using hardware BIST, the proposed scheme re-uses the CPU to perform in-field testing for all memories within the system. All quality metrics of the proposed solution (such as defect coverage, test time and code size) are analyzed. Case studies using the ARM instruction set architecture are provided to demonstrate the applicability of the solution. With the proposed approach no hardware BIST is necessary and speed-related faults are tackled, whereas results show the test time complexity of the SW-based transparent tests is the same as the one of the standard hardware BIST test. Moreover, data previously present in the memory is not corrupted with, in average, only a 30% increase in test program size with respect to non-transparent SW-based test

  88. Scan-Chain Intra-Cell Defects Grading
    A. Touati, A. Bosio, L. Dilillo, P. Girard, A. Virazel, P. Bernardi, M. Sonza Reorda
    10th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)
    DOI: 10.1109/DTIS.2015.7127349
    KEYWORDS: intra-cell defect; test; fault simulation; scan-chain testing
    ABSTRACT: With the continuous scaling down of the transistor size, the so-called intra-cell defects are more and more frequent. Several works analyze the impact of intra-cell defects w.r.t. the test quality. However, to the best of our knowledge, none of them target intra-cell defects affecting scan flip-flops. This paper presents an evaluation of the effectiveness of the ATPG test patterns in terms of intra-cell defect coverage affecting scan flip-flops. The experimental results show that a meaningful test solution has to be developed to improve the overall defect coverage for the scan chain testing

  89. Software-based self-test techniques of computational modules in dual issue embedded processors
    P. Bernardi, C. Bovi, R. Cantoro, S. De Luca, R. Meregalli, D. Piumatti, E. Sanchez, A. Sansonetti
    DOI: 10.1109/ETS.2015.7138730
    KEYWORDS: embedded systems; software-based self-test; sbst; system-on-chip; microprocessor testing; embedded systems; software-based self-test; sbst; system-on-chip; microprocessor testing
    ABSTRACT: Self-Test strategies for testing embedded processors are increasingly diffused. In this paper, we describe a set of self-test techniques tackling dual issue embedded processors. The paper details how to produce test programs suitable to detect stuck-at faults in computational modules belonging to dual issue processors. The proposed technique is aimed at extending single issue test programs; results are illustrated for a 32-bit processor included in an automotive System-on-Chip manufactured by STMicroelectronics and implementing a dual issue strategy with static dispatch of instructions.

  90. The EcoThermo project: key and innovative aspects
    F. Bari, D. Mereu, C. Damarco, C. Greco, S. Malan, G. Marchetto, S. Roa Tirado, R. Tisseur, M. Violante, G. Zangari, S. Caruso, M. Masoero, F. Saba
    Energy Procedia
    DOI: 10.1016/j.egypro.2015.11.697
    KEYWORDS: thermal comfort; energy efficiency; energy control; smart buildings; eu project
    ABSTRACT: In this paper we present the most innovative aspects of the EC-FP7 EcoThermo project. The main aim of the project consists on innovating the technique of heat cost allocation in buildings with a centralized heating system, overcoming the heat cost allocator drawbacks for reliability, measurement reproducibility and traceability and contexts of applications. Given the complexity of the project, we will focus on its main aspects, such as the use of a virtual sensor to estimate the radiators heating power, the design of electronic valves fitted out with an energy harvesting system and the original wireless communication protocol

  91. Towards automatic StarCraft strategy generation using genetic programming
    P. Garcia-Sanchez, A. Tonda, A. Mora, G. Squillero, J. Merelo
    Proceedings 2015 IEEE Conference on Computational Intelligence and Games
    DOI: 10.1109/CIG.2015.7317940
    KEYWORDS: starcraft; evolutionary computation; games; real-time strategy
    ABSTRACT: Among Real-Time Strategy games few titles have enjoyed the continued success of StarCraft. Many research lines aimed at developing Artificial Intelligences, or "bots", capable of challenging human players, use StarCraft as a platform. Several characteristics make this game particularly appealing for researchers, such as: asymmetric balanced factions, considerable complexity of the technology trees, large number of units with unique features, and potential for optimization both at the strategical and tactical level. In literature, various works exploit evolutionary computation to optimize particular aspects of the game, from squad formation to map exploration; but so far, no evolutionary approach has been applied to the development of a complete strategy from scratch. In this paper, we present the preliminary results of StarCraftGP, a framework able to evolve a complete strategy for StarCraft, from the building plan, to the composition of squads, up to the set of rules that define the bot's behavior during the game. The proposed approach generates strategies as C++ classes, that are then compiled and executed inside the OpprimoBot open-source framework. In a first set of runs, we demonstrate that StarCraftGP ultimately generates a competitive strategy for a Zerg bot, able to defeat several human-designed bots

  92. A New Solution to On-Line Detection of Control Flow Errors
    B. Du, M. Sonza Reorda, L. Sterpone, L. Parra, M. Portela-Garcia, A. Lindoso, L. Entrena
    Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium (IOLTS)
    KEYWORDS: on-line test; debug interface; control flow checking
    ABSTRACT: Transient faults can affect the behavior of electronic systems, and represent a major issue in many safety-critical applications. This paper focuses on Control Flow Errors (CFEs) and extends a previously proposed method, based on the usage of the debug interface existing in several processors/controllers. The new method achieves a good detection capability with very limited impact on the system development flow and reduced hardware cost: moreover, the proposed technique does not involve any change either in the processor hardware or in the application software, and works even if the processor uses caches. Experimental results are reported, showing both the advantages and the costs of the method

  93. A comparison of graphics processor architectures for RFID simulation
    R. Ferrero, B. Montrucchio, L. David, K. Ebrahim, L. Graglia, Giovanni Di Dio Iovino, M. Ribero
    DOI: 10.1109/NBiS.2014.37
    KEYWORDS: pervasive computing; parallel computing; nvidia cuda; opencl; gpgpu
    ABSTRACT: Graphics Processing Units (GPUs) have a huge number of cores to speed up graphical computations and they are being used in a wide area of general-purpose applications that require high performances. In this paper, GPU computing is exploited to model the signal propagation and the interference in large RFID systems, which are a promising solution for achieving pervasive computing since they offer the automatic object identification. The speedup of the parallel algorithm is evaluated with respect to a sequential version. Two popular frameworks for general-purpose computing on GPU are considered in the comparison, i.e. CUDA and OpenCL, and distinct implementations are provided for them, highlighting their differences in code optimization and performance

  94. A parallel fuzzy scheme to improve power consumption management in Wireless Sensor Networks
    M. Collotta, G. Scatà, S. Tirrito, R. Ferrero, M. Rebaudengo
    DOI: 10.1109/ETFA.2014.7005363
    ABSTRACT: Wireless Sensor Networks (WSNs) are increasingly used in different application fields thanks to several advantages such as cost-effectiveness, scalability, flexibility and selforganization. A hot research topic concerns the study of algorithms and mechanisms for reducing the power consumption of the nodes in order to maximize their lifetime. To this end, this paper proposes an approach based on two fuzzy controllers that determine the sleeping time and the transmission power. Simulation results reveal that the device lifetime is increased by 30% with respect to the use of fixed sleeping time and transmission power and by 25% with respect to a state-of-the-art work that adjusts only the sleeping time

  95. An effective approach to automatic functional processor test generation for small-delay faults
    R. Andreas, C. Lyl, S. Matthias, P. Bernardi, M. Sonza Reorda, B. Bernd
    Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014
    DOI: 10.7873/DATE2014.140
    ABSTRACT: Functional microprocessor test methods provide several advantages compared to DFT approaches, like reduced chip cost and at-speed execution. However, the automatic generation of functional test patterns is an open issue. In this work we present an approach for the automatic generation of functional microprocessor test sequences for small-delay faults based on Bounded Model Checking. We utilize an ATPG framework for small-delayfaults in sequential, non-scan circuits and propose a method for constraining the input space for generating functional test sequences (i.e., test programs). We verify our approach by evaluating the miniMIPS microprocessor. In our experiments we were able to reach over 97 % fault efficiency. To the best of our knowledge, this is the ?rst fully automated approach to functional microprocessor test for small-delay faults

  96. Analysis and mitigation of single event effects on flash-based FPGAS
    L. Sterpone, B. Du
    PROCEEDINGS 2014 19TH IEEE EUROPEAN TEST SYMPOSIUM (ETS)
    DOI: 10.1109/ETS.2014.6847804
    KEYWORDS: flash-based fpgas; place and route; single event effects; single event transients; single event upsets; static analysis
    ABSTRACT: In the present paper, we propose a new design flow for the analysis and the implementation of circuits on Flash-based FPGAs hardened against Single Event Effects (SEEs). The solution we developed is based on two phases: 1) an analyzer algorithm able to evaluate the propagations of SETs through logic gates; 2) a hardening algorithm able to place and route a circuit by means of optimal electrical filtering and selective guard gates insertions. The effectiveness of the proposed design flow has been evaluated by performing hardening on seven benchmark circuits and comparing the results using different implementation approaches on 130nm Flash-based technology. The obtained results have been validated against radiation-beam testing using heavy-ions and demonstrated that our solution is able to decrease the circuits sensitivity versus SEE by two orders of magnitude with a reduction of resource overhead of 83 % with respect to traditional mitigation approaches

  97. Diagnostic Test Generation for Statistical Bug Localization using Evolutionary Computation
    M. Gaudesi, M. Jenihhin, J. Raik, E. Sanchez, G. Squillero, V. Tihhomirov, R. Ubar
    Lecture Notes in Computer Science
    DOI: 10.1007/978-3-662-45523-4_35
    KEYWORDS: evolutionary computation; design error localization; automatic test pattern generation; diagnostics
    ABSTRACT: Verification is increasingly becoming a bottleneck in the process of designing electronic circuits. While there exists several verification tools that assist in detecting occurrences of design errors, or bugs, there is a lack of solutions for accurately pin-pointing the root causes of these errors. Statistical bug localization has proven to be an approach that scales up to large designs and is widely utilized both in debugging hardware and software. However, the accuracy of localization is highly dependent on the quality of the stimuli. In this paper we formulate diagnostic test set generation as a task for an evolutionary algorithm, and propose dedicated fitness functions that closely correlate with the bug localization capabilities. We perform experiments on the register-transfer level design of the Plasma microprocessor coupling an evolutionary test-pattern generator and a simulator for fitness evaluation. As a result, the diagnostic resolution of the tests is significantly improved

  98. Early Reliability Evaluation of a Biomedical System
    H. Hakobyan, P. Rech, M. Sonza Reorda, M. Violante
    2014 9th International Design & Test Symposium
    ABSTRACT: Early reliability evaluation for safety-critical applications is crucial, since it may allow to spot critical parts of the design and to introduce suitable countermeasures. In some domains it is common to adopt a design flow exploiting a high-level description of the system behavior and architecture; out of this description, suitable tools then automatically generate the software (and eventually the hardware) needed to perform the required tasks. This paper describes an enhanced version of such a design flow in which reliability is also considered and evaluated. The model of a pacemaker is developed and used for early estimation of its robustness with respect to a subset of the possible faults. The paper highlights why it is important to take into account the environment the target system is designed to interact with (in this case the heart), thus making possible to identify the most critical faults, based on the severity of their effects

  99. Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs
    E. Sanchez, L. Sterpone, U. Anees
    Proceedings of 24th International Conference on Field Programmable Logic and Applications (FPL), 2014
    DOI: 10.1109/FPL.2014.6927478

  100. Fault Injection in GPGPU Cores to Validate and Debug Robust Parallel Applications
    M. De Carvalho, D. Sabena, M. Sonza Reorda, L. Sterpone, P. Rech, L. Carro
    Proceedings of IEEE 20th International On-Line Testing Symposium (IOLTS)
    KEYWORDS: fault injection; reliable gpgpu applications; robust algorithms; transient faults
    ABSTRACT: General Purpose Graphic Processing Units (GPGPUs) are more efficient than CPUs for processing parallel data. Unfortunately, GPGPUs are sensible to radiation. Hence, several software mitigation techniques, as well as robust algorithms, are being developed to overcome reliability problems. In this paper we propose a software debugger-based fault injection mechanism to evaluate the resiliency of applications running on a GPGPU and to validate the software hardening techniques it possibly embeds. We report some experimental results gathered on selected case studies to show the proposed approach advantages and limitations

  101. Fault Injection in the Process Descriptor of a Unix-based Operating System
    B. Montrucchio, M. Rebaudengo, A.D. Velasco
    Proceedings of the 28th Defect and Fault Tolerance in VLSI and Nanotechnology Systems Symposium
    KEYWORDS: operating system; fault injection
    ABSTRACT: Transient faults in computer-based systems for which high availability is a strict requirement, originated from several sources, like high energy particles, are a major issue. Fault injection is a commonly used method to evaluate the sensitivity of such systems. The paper presents an evaluation of the effects of faults in the memory containing the process descriptor of a Unix-based Operating System. In particular the state field has been taken into consideration as the main target, changing the current state value into another one that could be valid or invalid. An experimental analysis has been conducted on a large set of different tasks, belonging to the operating system itself. Results of tests show that the state field in the process descriptor represents a critical variable as far as dependability is considered

  102. Fault injection and fault tolerance methodologies for assessing device robustness and mitigating against ionizing radiation
    A. Dan, L. Sterpone, Lopez-Ongil Celia
    Proceedings of the 19th IEEE European Test Symposium
    DOI: 10.1109/ETS.2014.6847812
    KEYWORDS: fpgas; reliability; heavy ions; test facility
    ABSTRACT: Traditionally, heavy ion radiation effects affecting digital systems working in safety critical application systems has been of huge interest. Nowadays, due to the shrinking technology process, Integrated Circuits became sensitive also to other kinds of radiation particles such as neutron that can exist at the earth surface and affects ground-level safety critical applications such as automotive or medical systems. The process of analyzing and hardening digital devices against soft errors implies rising the final cost due to time expensive fault injection campaigns and radiation tests, as well as reducing system performance due to the insertion of redundancy-based mitigation solutions. The main industrial problem arising is the localization of the critical elements in the circuit in order to apply optimal mitigation techniques. The proposal of this tutorial is to present and discuss different solutions currently available for assessing and implementing the fault tolerance of digital circuits, not only when the unique design description is provided but also at the component level, especially when Commercial-of-the-shelf (COTS) devices are selected

  103. GPGPUs: How to combine high computational power with high reliability
    L. Bautista Gomez, F. Cappello, L. Carro, N. Debardeleben, B. Fang, S. Gurumurthi, K. Pattabiraman, P. Rech, M. Sonza Reorda
    Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014
    DOI: 10.7873/DATE2014.354
    ABSTRACT: GPGPUs are used increasingly in several domains, from gaming to different kinds of computationally intensive applications. In many applications GPGPU reliability is becoming a serious issue, and several research activities are focusing on its evaluation. This paper offers an overview of some major results in the area. First, it shows and analyzes the results of some experiments assessing GPGPU reliability in HPC datacenters. Second, it provides some recent results derived from radiation experiments about the reliability of GPGPUs. Third, it describes the characteristics of an advanced fault-injection environment, allowing effective evaluation of the resiliency of applications running on GPGPUs

  104. High Quality System Level Test and Diagnosis
    A. Jutman, M. Sonza Reorda, Hans-Joachim Wunderlich
    2014 IEEE 23rd Asian Test Symposium
    DOI: 10.1109/ATS.2014.62
    ABSTRACT: This survey introduces into the common practices, current challenges and advanced techniques of high quality system level test and diagnosis. Specialized techniques and industrial standards of testing complex boards are introduced. The reuse for system test of design for test structures and test data developed at chip level is discussed, including the limitations and research challenges. Structural test methods have to be complemented by functional test methods. State-of-the-art and leading edge research for functional testing will be covered

  105. In-field testing of SoC devices: Which solutions by which players?
    A. Jacob, G. Xinli, T. Maclaurin, J. Rajski, G. Paul, D. Gizopoulos, M. Sonza Reorda
    2014 IEEE 32nd VLSI Test Symposium (VTS)
    DOI: 10.1109/VTS.2014.6818780
    ABSTRACT: In-field testing of SoC devices is increasingly important to face the dependability requirements of several application domains. Different solutions can be devised and adopted. We summarize the main solutions currently adopted by industry, identify the most critical open issues, and discuss important future trends

  106. Layout and radiation tolerance issues in high-speed links for TDAQ systems
    V. Bocci, M. Capodiferro, R. Giordano, V. Izzo
    Real Time Conference (RT), 2014 19th IEEE-NPSS
    DOI: 10.1109/RTC.2014.7097548

  107. On the Functional Test of the Register Forwarding and Pipeline Interlocking Unit in Pipelined Processors
    P. Bernardi, R. Cantoro, L. Ciganda, B. Du, E. Sanchez, M. Sonza Reorda, M. Grosso, O. Ballan
    Proceedigns on 14th International Workshop on Microprocessor Test and Verification (MTV), 2013
    DOI: 10.1109/MTV.2013.10
    KEYWORDS: microprocessor testing; functional testing
    ABSTRACT: When the result of a previous instruction is needed in the pipeline before it is available, a "data hazard" occurs. Register Forwarding and Pipeline Interlock (RF&PI) are mechanisms suitable to avoid data corruption and to limit the performance penalty caused by data hazards in pipelined microprocessors. Data hazards handling is part of the 1microprocessor control logic; its test can hardly be achieved with a functional approach, unless a specific test algorithm is adopted. In this paper we analyze the causes for the low functional testability of the RF&PI logic and propose some techniques able to effectively perform its test. In particular, we describe a strategy to perform Software-Based Self-Test (SBST) on the RF&PI unit. The general structure of the unit is analyzed, a suitable test algorithm is proposed and the strategy to observe the test responses is explained. The method can be exploited for test both at the end of manufacturing and in the operational phase. Feasibility and effectiveness of the proposed approach are demonstrated on both an academic MIPS-like processor and an industrial System-on-Chip based on the Power ArchitectureTM

  108. On the In-Field Test of Branch Prediction Units using the Correlated Predictor mechanism
    M. Gaudesi, S. Saleem, E. Sanchez, M. Sonza Reorda, E. Tanowe
    KEYWORDS: sbst; branch history table; branch prediction unit
    ABSTRACT: Branch Prediction Units (BPUs) are widely used to reduce the performance penalties caused by branch instructions in pipelined processors. BPUs may be implemented in different forms: the Branch History Table (BHT) is an effective solution when the goal is predicting the result of conditional branches. In this paper we propose a method to generate test programs able to detect faults affecting the memory existing within a BHT implementing the correlated predictors approach. Our method is particularly suited to be used for the in-field test of a processor and allows detecting any stuck-at fault in the BPU memory. The method does not require the detailed knowledge of the BPU implementation, but only relies on the key parameters of its architecture. We gathered experimental results using the SimpleScalar environment

  109. On the in-Field Functional Testing of Decode Units in Pipelined RISC Processors
    P. Bernardi, R. Cantoro, L. Ciganda, E. Sanchez, M. Sonza Reorda, S. De Luca, R. Meregalli, A. Sansonetti
    Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
    KEYWORDS: software-based self-test; decode unit; instruction coverage; fault grading
    ABSTRACT: The paper is dealing with the in-field test of the decode unit of RISC processors through functional test programs following the SBST approach. The paper details a strategy based on instruction classification and manipulation, and signatures collection. The method does not require the knowledge of detailed implementation information (e.g., the netlist), but is based on the Instruction Set of the processor. The proposed method is evaluated on an industrial SoC device, which includes a PowerPC derived processor. Results demonstrate the efficiency and effectiveness of the strategy; the proposed solution reaches over 90% of stuck-at fault coverage while an instruction coverage based approach does not overcome 70%

  110. Permanent faults on LIN networks: On-line test generation
    A. Vaskova, M. Portela-Garcia, M. Garcia-Valderas, C. Lopez-Ongil, M. Sonza Reorda
    2014 IEEE 20th International On-Line Testing Symposium (IOLTS)
    DOI: 10.1109/IOLTS.2014.6873665

  111. Reconfigurable High Performance Architectures: How much are they ready for safety-critical applications
    D. Sabena, L. Sterpone, M. Schölzel, T. Koal, H. Vierhaus, S. Wong, R. Glein, F. Rittner, C. Stender, M. Porrmann, J. Hagemeyer
    Proceedings of 19th IEEE European Test Symposium (ETS)
    KEYWORDS: reconfigurable systems; vliw processor
    ABSTRACT: Reconfigurable architectures are increasingly employed in a large range of embedded applications, mainly due to their ability to provide high performance and high flexibility, combined with the possibility to be tuned according to the specific task they address. Reconfigurable systems are today used in several application areas, and are also suitable for systems employed in safety-critical environments. The actual development trend in this area is focused on the usage of the reconfigurable features to improve the fault tolerance and the self-test and the self-repair capabilities of the considered systems. The state-of-the-art of the reconfigurable systems is today represented by Very Long Instruction Word (VLIW) processors and reconfigurable systems based on partially reconfigurable SRAM-based FPGAs. In this paper, we present an overview and accurate analysis of these two type of reconfigurable systems. The content of the paper is focused on analyzing design features, fail-safe and reconfigurable features oriented to self-adaptive mitigation and redundancy approaches applied during the design phase. Experimental results reporting a clear status of the test data and fault tolerance robustness are detailed and commented

  112. Reducing SEU Sensitivity in LIN Networks: Selective and Collaborative Hardening Techniques
    A. Vaskova, A. Fabregat, M. Portela-García, M. García-Valderas, C. López-Ongil, M. Sonza Reorda
    2014 15th Latin American Test Workshop - LATW
    DOI: 10.1109/LATW.2014.6841924
    ABSTRACT: Digital electronic systems in automotive applications are in charge of different tasks, ranging from very critical control functions (e.g., airbag, ABS, ESP) to comfort services (e.g., handling of mirrors, seats, windows, wipers). Hardening these systems involves suitably trading off cost and reliability. Due to standards and regulations in the area, the reliability of subsystems involved even in the least critical applications has to be evaluated, and in most cases hardening has to be performed with very low extra cost. In this work, two approaches are proposed for hardening the LIN bus, which implements a serial communication network typically used in low-throughput and low-cost sub-systems in automotive applications. First, critical elements in LIN nodes are identified and some techniques to harden them are proposed following a selective hardening approach. Secondly, collaborative hardening techniques are proposed for reducing global sensitivity in a LIN network built with commercial devices, trying to achieve a high degree of robustness in the network with low cost solutions. We report some experimental results allowing evaluating the hardware cost and the robustness of the proposed techniques

  113. Soft Error Effects Analysis and Mitigation in VLIW Safety-Critical Applications
    D. Sabena, M. Sonza Reorda, L. Sterpone
    Proceedings of IFIP/IEEE 22nd International Conference on Very Large Scale Integration (VLSI-SoC)
    KEYWORDS: hardening technique; vliw processor; cross domain error
    ABSTRACT: VLIW architectures are widely employed in several embedded signal applications since they offer the opportunity to obtain high computational performances while maintaining reduced clock rate and power consumption. Recently, VLIW processors are being considered for employment in various embedded processing systems, including safety-critical ones (e.g., in the aerospace, automotive and rail transport domains). Terrestrial safety-critical applications based on newer nano-scale technologies raise increasing concerns about transient errors induced by neutrons. Therefore, techniques to effectively estimate and improve the reliability of VLIW processors are of great interest. In this paper, we present a novel technique aimed to further improve the efficiency of the Triple Modular Redundancy (TMR) hardening-technique applied at the software level on VLIW processors. In particular, we first experimentally demonstrate that the TMR-based software technique, when applied at the C code level, is not able to cope with most of the failures affecting user logic resources. Then, we propose a method able to analyze and modify the TMR-based code for a generic VLIW processor in order to improve the fault tolerance of the executed application without modifying the VLIW processor. In details, the proposed technique is able to reduce the number of cross-domain errors affecting the TMR-hardened code of a VLIW processor data path. We provide figures about performance and fault coverage for both the un-protected and protected versions of a set of benchmark applications, thus demonstrating the benefits and limitations of our approach

  114. Software-implemented Fault Injection in Operating System Kernel Mutex Data Structure
    B. Montrucchio, M. Rebaudengo, A.D. Velasco
    Proceedings of 5th IEEE Latin American Symposium on Circuits and Systems (LASCAS)
    DOI: 10.1109/LASCAS.2014.6820257
    KEYWORDS: software-implemented fault injection; mutex data structure; operating system
    ABSTRACT: Embedded and Computer-based systems are subject to transient errors originated from several sources, including the impact of high energy particles on sensitive areas of integrated circuits. The evaluation of the sensitivity of the applications to transient faults is a major issue. The paper presents a new approach for testing the effects of transient faults on the Operating System kernel, specifically focusing on kernel mutex data structure, a key component of the kernel. A Software-implemented Fault Injection tool able to inject faults guaranteeing the non-intrusiveness and repeatability of the fault injection campaign is proposed. An analysis of the results has been performed on a large set of mutexes, in order to evaluate their criticality, in particular during input/output operations. Experimental results, executed on a set of benchmarks programs, show the relevance of the effects of the transient faults on this set of variables. Moreover, a significant percentage of faults can lead to a damage of the system also producing an application failure

  115. TURAN: Evolving non-deterministic players for the iterated prisoner's dilemma
    M. Gaudesi, E. Piccolo, G. Squillero, A. Tonda
    Evolutionary Computation (CEC), 2014 IEEE Congress on
    DOI: 10.1109/CEC.2014.6900564
    ABSTRACT: The iterated prisoner's dilemma is a widely known model in game theory, fundamental to many theories of cooperation and trust among self-interested beings. There are many works in literature about developing efficient strategies for this problem, both inside and outside the machine learning community. This paper shift the focus from finding a "good strategy" in absolute terms, to dynamically adapting and optimizing the strategy against the current opponent. Turan evolves competitive non-deterministic models of the current opponent, and exploit them to predict its moves and maximize the payoff as the game develops. Experimental results show that the proposed approach is able to obtain good performances against different kind of opponent, whether their strategies can or cannot be implemented as finite state machines

  116. The tradeoffs between data delivery ratio and energy costs in wireless sensor networks
    D. Bucur, G. Iacca, G. Squillero, A. Tonda
    Proceedings of the 2014 conference on Genetic and evolutionary computation - GECCO '14
    DOI: 10.1145/2576768.2598384
    ABSTRACT: Wireless sensor network (WSN) routing protocols, e.g., the Collection Tree Protocol (CTP), are designed to adapt in an ad-hoc fashion to the quality of the environment. WSNs thus have high internal dynamics and complex global behavior. Classical techniques for performance evaluation (such as testing or verification) fail to uncover the cases of extreme behavior which are most interesting to designers. We contribute a practical framework for performance evaluation of WSN protocols. The framework is based on multi-objective optimization, coupled with protocol simulation and evaluation of performance factors. For evaluation, we consider the two crucial functional and non-functional performance factors of a WSN, respectively: the ratio of data delivery from the network (DDR), and the total energy expenditure of the network (COST). We are able to discover network topological configurations over which CTP has unexpectedly low DDR and/or high COST performance, and expose full Pareto fronts which show what the possible performance tradeoffs for CTP are in terms of these two performance factors. Eventually, Pareto fronts allow us to bound the state space of the WSN, a fact which provides essential knowledge to WSN protocol designers

  117. Towards Automated Malware Creation: Code Generation and Code Integration
    A. Cani, M. Gaudesi, E. Sanchez, G. Squillero, A. Tonda
    Towards Automated Malware Creation: Code Generation and Code Integration
    KEYWORDS: malware; virus; evolutionary algorithms; security
    ABSTRACT: The analogies between computer malware and biological viruses are more than obvious. The very idea of an artificial ecosystem where malicious software can evolve and autonomously find new, more effective ways of attacking legitimate programs and damaging sensitive information is both terrifying and fascinating. The paper proposes two different ways for exploiting an evolutionary algorithm to devise malware: the former targeting heuristic-based antivirus scanner; the latter optimizing a Trojan attack. Testing the stability of a system against a malware-based attack, or checking the reliability of the heuristic scan of anti-virus software against an original malware application could be interesting for the research community and advantageous to the IT industry. Experimental results shows the feasibility of the proposed approaches on simple real-world test cases

  118. Universal information distance for genetic programming
    M. Gaudesi, G. Squillero, A. Tonda
    Proceedings of the 2014 conference companion on Genetic and evolutionary computation companion - GECCO Comp '14
    DOI: 10.1145/2598394.2598440
    KEYWORDS: distance metric; algorithms; fitness sharing; individual encoding; symbolic regression; diversity preservation; genetic programming; measurements; experimental analysis
    ABSTRACT: This paper presents a genotype-level distance metric for Genetic Programming (GP) based on the symmetric difference concept: first, the information contained in individuals is expressed as a set of symbols (the content of each node, its position inside the tree, and recurring parent-child structures); then, the difference between two individuals is computed considering the number of elements belonging to one, but not both, of their symbol sets

  119. Validation of a tool for estimating the effects of Soft- Errors on modern SRAM-based FPGAs
    M. Desogus, L. Sterpone, D.M. Codinachs
    Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium (IOLTS)
    KEYWORDS: fault tolerance; experimental validation; fpgas
    ABSTRACT: Predicting soft errors on SRAM-based FPGAs without a wasteful time-consuming or a high-cost has always been a very difficult goal. Among the available methods, we proposed an updated version of analytical approach to predict Single Event Effects (SEEs) based on the analysis of the circuit the FPGA implements. In this paper, we provide an experimental validation of this approach, by comparing the results it provides with a fault injection campaign. We adopted our analytical method for computing the error-rate of a design implemented on SRAM-based FPGA. Furthermore, we compared the obtained soft-error figure with the one measured by fault injection. Experimental analysis demonstrated the analytical method closely match the effective soft-error rates becoming a viable solution for the soft-error estimation at early design phases

  120. A Functional Test Algorithm for the Register Forwarding and Pipeline Interlocking unit in Pipelined Microprocessors
    P. Bernardi, D. Boyang, L. Ciganda, E. Sanchez, M. Sonza Reorda, M. Grosso, O. Ballan
    IEEE 7th International Design and Test Symposium (IDT)
    DOI: 10.1109/IDT.2013.6727120
    ABSTRACT: When the result of a previous instruction is needed in the pipeline before it is available, a "data hazard" occurs. Register Forwarding and Pipeline Interlock (RF&PI) are mechanisms suitable to avoid data corruption and to limit the performance penalty caused by data hazards in pipelined microprocessors. Data hazards handling is part of the microprocessor control logic; its test can hardly be achieved with a functional approach, unless a specific test algorithm is adopted. In this paper we analyze the causes for the low functional testability of the RF&PI logic and propose some techniques able to effectively perform its test. In particular, we describe a strategy to perform Software-Based Self-Test (SBST) on the RF&PI unit. The general structure of the unit is analyzed, a suitable test algorithm is proposed and the strategy to observe the test responses is explained. The method can be exploited for test both at the end of manufacturing and in the operational phase. Feasibility and effectiveness of the proposed approach are demonstrated on both an academic MIPS-like processor and an industrial System-on-Chip based on the Power Architecture

  121. A Memetic Approach to Bayesian Network Structure Learning
    A. Tonda, E. Lutton, G. Squillero, Pierre-Henri Wuillemin
    Applications of Evolutionary Computation
    DOI: 10.1007/978-3-642-37192-9_11
    KEYWORDS: memetic algorithms; evolutionary algorithms; local optimization; bayesian networks; model learning
    ABSTRACT: Bayesian networks are graphical statistical models that represent inference between data. For their effectiveness and versatility, they are widely adopted to represent knowledge in different domains. Several research lines address the NP-hard problem of Bayesian network structure learning starting from data: over the years, the machine learning community delivered effective heuristics, while different Evolutionary Algorithms have been devised to tackle this complex problem. This paper presents a Memetic Algorithm for Bayesian network structure learning, that combines the exploratory power of an Evolutionary Algorithm with the speed of local search. Experimental results show that the proposed approach is able to outperform state-of-the-art heuristics on two well-studied benchmarks

  122. Accounting for Post-Transcriptional Regulation in Boolean Networks Based Regulatory Models
    A. Benso, S. Di Carlo, H. Rehman, G. Politano, A. Savino, G. Squillero, A. Vasciaveo, S. Benedettini
    International Work-Conference on Bioinformatics and Biomedical Engineering (IWBBIO) 2013
    KEYWORDS: mirna; gene regulatory networks; post-transcriptional regulation; boolean networks; complex systems; network analysis; bioinformatics
    ABSTRACT: Boolean Networks are emerging as a simple yet powerful for- malism to model and study Gene Regulatory Networks. Nevertheless, the most widely used Boolean Network-based models do not include any post-transcriptional regulation mechanism. In this paper we discuss how the post-transcriptional regulation mechanism mediated by miRNAs can be included in a Boolean Network based model to have a more realistic representation of a Gene Regulatory Networks. This contribution con- stitutes a critical preparatory step in the study of the topological and structural role of miRNAs in complex regulatory networks

  123. Accurate Mitigation of Single Event Effects on Flash-based FPGAs: A new Design Flow
    L. Sterpone, B. Du, D. Merodio Codinachs, V. Ferlet Cavrois
    Proceedings of RADECS
    KEYWORDS: fpga; single event transients (sets)
    ABSTRACT: We propose a new design flow for implementing circuits hardened against SET effects af- fecting Flash-based FPGAs. Experimental results on RISC microprocessors show an in- crease of robustenss of more than 70% wrt traditional mitigation approaches

  124. An Efficient Distance Metric for Linear Genetic Programming
    M. Gaudesi, G. Squillero, A. Tonda
    Proceeding of the fifteenth annual conference on Genetic and evolutionary computation conference
    DOI: 10.1145/2463372.2463495
    KEYWORDS: measurement; algorithms
    ABSTRACT: Defining a distance measure over the individuals in the population of an Evolutionary Algorithm can be exploited for several applications, ranging from diversity preservation to balancing exploration and exploitation. When individuals are encoded as strings of bits or sets of real values, computing the distance between any two can be a straightforward process; when individuals are represented as trees or linear graphs, however, quite often the user must resort to phenotype-level problem-specific distance metrics. This paper presents a generic genotype-level distance metric for Linear Genetic Programming: the information contained by an individual is represented as a set of symbols, using n-grams to capture significant recurring structures inside the genome. The difference in information between two individuals is evaluated resorting to a symmetric difference. Experimental evaluations show that the proposed metric has a strong correlation with phenotype-level problem-specific distance measures in two problems where individuals represent string of bits and Assembly-language programs, respectively

  125. An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable Systems
    M. Sonza Reorda, L. Sterpone, A. Ullah

  126. An Evolutionary Approach to Wetlands Design
    M. Gaudesi, A. Marion, T. Musner, G. Squillero, A. Tonda
    Lecture Notes in Computer Science (vol 7833)
    DOI: 10.1007/978-3-642-37189-9_16
    KEYWORDS: evolutionary algorithms; wetlands design; ecological modelling
    ABSTRACT: Wetlands are artificial basins that exploit the capabilities of some species of plants to purify water from pollutants. The design process is currently long and laborious: such vegetated areas are inserted within the basin by trial and error, since there is no automatic system able to maximize the efficiency in terms of filtering. Only at the end of several attempts, experts are able to determine which is the most convenient configuration and choose up a layout. This paper proposes the use of an evolutionary algorithm to automate both the placement and the sizing of vegetated areas within a basin. The process begins from a random population of solutions and, evaluating their efficiency with an state-of-the-art fluid-dynamics simulation framework, the evolutionary algorithm is able to automatically find optimized solution whose performance are comparable with those achieved by human experts

  127. An Evolutionary Framework for Routing Protocol Analysis in Wireless Sensor Networks
    D. Bucur, G. Iacca, G. Squillero, A. Tonda
    Lecture Notes in Computer Science (vol 7835)
    DOI: 10.1007/978-3-642-37192-9-1
    ABSTRACT: Wireless Sensor Networks (WSNs) are widely adopted for applications ranging from surveillance to environmental monitoring. While powerful and relatively inexpensive, they are subject to behavioural faults which make them unreliable. Due to the complex interactions between network nodes, it is difficult to uncover faults in a WSN by resorting to formal techniques for verification and analysis, or to testing. This paper proposes an evolutionary framework to detect anomalous behaviour related to energy consumption in WSN routing protocols. Given a collection protocol, the framework creates candidate topologies and evaluates them through simulation on the basis of metrics measuring the radio activity on nodes. Experimental results using the standard Collection Tree Protocol show that the proposed approach is able to unveil topologies plagued by excessive energy depletion over one or more nodes, and thus could be used as an offline debugging tool to understand and correct the issues before network deployment and during the development of new protocols

  128. An efficient method for the test of embedded memory cores during the operational phase
    P. Bernardi, L. Ciganda, M. Sonza Reorda, S. Hamdioui
    2013 22nd Asian Test Symposium
    ABSTRACT: System on Chip devices include an increasing number of embedded memory cores, whose test during the operational phase is often a strict requirement, especially for safety-critical applications. This paper proposes a new memory test method combining the characteristics of hardware and software solutions: the test is performed by the microcontroller/processor, while the code of the test instructions to be executed is generated on-the-fly by an ad hoc module, also in charge of checking the memory behavior. The solution is modular and does not require any modification either in the memory cores or in the processor. Moreover, it is well suited to be used for test during the operational phase. Experimental results, gathered by implementing some representative March elements and algorithms, show that the method guarantees higher defect coverage than software BIST and a test time comparable with that of traditional hardware BIST solutions with a reduced hardware cost

  129. Dynamic Neutron Testing of Dynamically Reconfigurable Processing Modules Architecture
    L. Sterpone, D. Sabena, A. Ullah, M. Porrmann, J. Hagemeyer, J. Ilstad

  130. EXPLOITING THE DEBUG INTERFACE TO SUPPORT ON LINE TEST OF CONTROL FLOW ERRORS
    B. Du, M. Sonza Reorda, L. Sterpone, L. Parra, M. Portela Garcia, A. Lindoso, L. Entrena
    DOI: 10.1109/IOLTS.2013.6604058

  131. Evolutionary Optimization of Wetlands Design
    M. Gaudesi, A. Marion, T. Musner, G. Squillero, A. Tonda
    Proceedings of the 28th Annual ACM Symposium on Applied Computing
    DOI: 10.1145/2480362.2480400
    KEYWORDS: wetlands design; evolutionary algorithms; optimization
    ABSTRACT: Wetlands are artificial ponds, designed to filter and purify running water through the contact with plant stems and roots. Wetland layouts are traditionally designed by experts through a laborious and time-consuming procedure: in principle, small patches of vegetation with purifying properties are tentatively placed, then the resulting water flow is verified by fluid dynamics simulators and when a satisfying outcome is reached, the wetland final layout is decided. This paper proposes to automate wetland design exploiting an evolutionary algorithm: a population of candidate solutions is cultivated by the evolutionary core, and their efficiency is evaluated using a state-of-the-art fluid-dynamics simulation framework. Experimental results show that the results obtained by the proposed approach are qualitatively comparable with those provided by experts, despite the complete absence of human intervention during the optimization process

  132. Fault detection in RNS Montgomery modular multiplication
    J. Jean-Claude Bajard, F. Gandino
    DOI: 10.1109/ARITH.2013.31
    KEYWORDS: base conversions; fault detection; montgomery reduction; rns
    ABSTRACT: Recent studies have demonstrated the importance of protecting the hardware implementations of cryptographic functions against side channel and fault attacks. In last years, very efficient implementations of modular arithmetic have been done in RNS (RSA, ECC, pairings) as well on FPGA as on GPU. Thus the protection of RNS Montgomery modular multiplication is a crucial issue. For that purpose, some techniques have been proposed to protect this RNS operation against side channel analysis. Nevertheless, there are still no effective and generic approaches for the detection of fault injection, which would be additionnally compatible with a leak resistant arithmetic. This paper proposes a new RNS Montgomery multiplication algorithm with fault detection capability. A mathematical analysis demonstrates the validity of the proposed approach. Moreover, an architecture that implements the proposed algorithm is presented. A comparative analysis shows that the introduction of the proposed fault detection technique requires only a limited increase in area

  133. Hardening of serial communication protocols for potentially critical systems in automotive applications: LIN bus
    A. Vaskova, M. Portela-Garcia, M. Garcia-Valderas, C. Lopez-Ongil, M. Sonza Reorda
    DOI: 10.1109/IOLTS.2013.6604044

  134. Hierarchical Key Negotiation Technique for Transitory Master Key Schemes in Wireless Sensor Networks
    C. Celozzi, F. Gandino, M. Rebaudengo
    KEYWORDS: key management; wireless sensor network; transitory master key
    ABSTRACT: Wireless sensor networks have been applied in various contexts where hardware and network data are exposed to security threats, such as tampering or eavesdropping. The majority of the security approaches adopted in this context are based on symmetric encryption, which requires keys shared among the nodes. Many key management schemes, like the transitory master key scheme LEAP+, have been proposed for the negotiation of keys. In this paper a new key negotiation technique suitable for LEAP+ protocol is described. The proposed protocol significantly reduces the time of exposition of sensitive information through a new organization of handshake operations and of key establishment. A comparison with the original version of LEAP+ was performed to evaluate the improvements achieved by the proposed approach

  135. Improving Key Negotiation in Transitory Master Key Schemes for Wireless Sensor Networks
    C. Celozzi, F. Gandino, M. Rebaudengo
    LECTURE NOTES OF THE INSTITUTE FOR COMPUTER SCIENCES, SOCIAL INFORMATICS AND TELECOMMUNICATIONS ENGINEERING
    DOI: 10.1007/978-3-319-04166-7_1
    KEYWORDS: key management; wireless sensor networks; transitory master key
    ABSTRACT: In recent years, wireless sensor networks have been adopted in different areas of daily life, exposing the network data and the hardware to different security threats. Many key management schemes have been proposed aiming at securing the communications among nodes, for instance the popular LEAP+ protocol. This paper proposes an enhanced variant of the LEAP+ protocol that decreases the key setup time through the reduction of the number of exchanged packets thus improving the security of communications. The results extracted from extensive test sessions obtained by network simulation have been compared to the corresponding data derived from the LEAP+ protocol in order to quantify the improvements

  136. Increasing fault coverage during functional test in the operational phase2013 IEEE 19th International On-Line Testing Symposium (IOLTS)
    M. De Carvalho, P. Bernardi, E. Sanchez, M. Sonza Reorda, O. Ballan
    2013 IEEE 19th International On-Line Testing Symposium (IOLTS)
    DOI: 10.1109/IOLTS.2013.6604049

  137. Industrial applications of evolutionary algorithms
    G. Squillero
    Proceeding of the fifteenth annual conference companion on Genetic and evolutionary computation conference companion - GECCO '13 Companion
    DOI: 10.1145/2464576.2480814

  138. On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors
    D. Sabena, L. Sterpone, M. Sonza Reorda
    VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design
    DOI: 10.1007/978-3-642-45073-0_9
    KEYWORDS: fault simulation; fault diagnosis; vliw processor; sbst
    ABSTRACT: Software-Based Self-Test (SBST) approaches have shown to be an effective solution to detect permanent faults, both at the end of the production process, and during the operational phase. However, when Very Long Instruction Word (VLIW) processors are addressed these techniques require some optimization steps in order to properly exploit the parallelism intrinsic in these architectures. In this chapter we present a new method that, starting from previously known algorithms, automatically generates an effective test program able to still reach high fault coverage on the VLIW processor under test, while minimizing the test duration and the test code size. Moreover, using this method, a set of small SBST programs can be generated aimed at the diagnosis of the VLIW processor. Experimental results gathered on a case study show the effectiveness of the proposed approach

  139. On the On-line Functional Test of the Reorder Buffer Memory in Superscalar Processors
    S. Di Carlo, E. Sanchez, M. Sonza Reorda
    Proceedings of the IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems 2013
    DOI: 10.1109/DDECS.2013.6549785
    KEYWORDS: microprocessor testing; software-based self-test; embedded memory test; on-line test; reorder buffer; digital system design test and verification
    ABSTRACT: The Reorder Buffer (ROB) is a key component in superscalar processors. It enables both in-order commitment of instructions and precise exception management even in those architectures that support out-of-order execution. The ROB architecture typically includes a memory array whose size may reach several thousands of bits. Testing this array may be important to guarantee the correct behavior of the processor. Proprietary BIST solutions typically adopted by manufacturers for end-of-production test are not always suitable for on-line test. In fact, they require the usage of test infrastructures that may be expensive, or may not be accessible and/or documented. This paper proposes an alternative solution, based on a functional approach, which has been validated resorting to both an architectural and a memory fault simulator

  140. On the Optimal Reconfiguration Times for TMR Circuits on SRAM based FPGAs
    L. Sterpone, A. Ullah

  141. On the development of diagnostic test programs for VLIW processors
    D. Sabena, M. Sonza Reorda, L. Sterpone
    Proceedings of 21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
    KEYWORDS: software-based fault diagnosis; fault simulation; vliw processors; software-based self-test
    ABSTRACT: Software-Based Self-Test (SBST) approaches have shown to be an effective solution to detect permanent faults, both at the end of the production process, and during the operational phase. When partial reconfiguration is adopted to deal with permanent faults, we also need to identify the faulty module, which is then substituted with a spare one. Software-based Diagnosis techniques can be exploited for this purpose, too. When Very Long Instruction Word (VLIW) processors are addressed, these techniques can effectively exploit the parallelism intrinsic in these architectures. In this paper we propose a new approach that starting from existing detection-oriented programs generates a diagnosis-oriented test program which in most cases is able to identify the faulty module. Experimental results gathered on a case study show the effectiveness of the proposed approach

  142. On the evaluation of soft-errors detection techniques for GPGPUs
    D. Sabena, M. Sonza Reorda, L. Sterpone, P. Rech, L. Carro
    Proceedings of 2013 8th IEEE International Design and Test Symposium (IDT)
    KEYWORDS: soft errors; redundancy techniques; radiation testing; gpgpu
    ABSTRACT: Recently, General Purpose Graphic Processing Units (GPGPUs) have begun to be preferred to CPUs for several computationally intensive applications, not necessarily related to computer graphics. However, due to their complexity GPGPUs also show a relatively high sensitivity to soft errors. Hence, there is some interest in devising and applying software techniques able to exploit their computational power by just acting on the executed code. In this paper we report some preliminary results obtained by applying two different software redundancy techniques aimed at soft-error detection; these techniques are completely algorithm independent, and have been applied on a sample application running on a Commercial-Off-The-Shelf GPGPU. The results have been gathered resorting to a neutron testing campaign. Some experimental results, explaining the capabilities of the methods, are presented and commented

  143. On the functional test of the BTB logic in pipelined and superscalar processors
    D. Changdao, M. Graziano, E. Sanchez, M. Sonza Reorda, M. Zamboni, N. Zhifan
    Test Workshop (LATW), 2013 14th Latin American
    DOI: 10.1109/LATW.2013.6562677
    KEYWORDS: test program generation; branch prediction unit; sbst; branch target buffer
    ABSTRACT: Electronic systems are increasingly used for safety-critical applications, where the effects of faults must be taken under control and hopefully avoided. For this purpose, test of manufactured devices is particularly important, both at the end of the production line and during the operational phase. This paper describes a method to test the logic implementing the Branch Prediction Unit in pipelined and superscalar processors when this follows the Branch Target Buffer (BTB) architecture; the proposed approach is functional, i.e., it is based on forcing the processor to execute a suitably devised test program and observing the produced results. Experimental results are provided on the DLX processor, showing that the method can achieve a high value of stuck-at fault coverage while also testing the memory in the BTB

  144. On-line functionally untestable fault identification in embedded processor cores
    P. Bernardi, M. Bonazza, E. Sanchez, M. Sonza Reorda, O. Ballan

  145. On-line testing of permanent radiation effects in reconfigurable systems
    L. Cassano, D. Cozzi, S. Korf, J. Hagemeyer, M. Porrmann, L. Sterpone
    DOI: 10.7873/DATE.2013.154

  146. Reliability Analysis Reloaded: How Will We Survive?
    R. Aitken, Görschwin Fey, T. Zbigniew, F. Reichenbach, M. Sonza Reorda
    ABSTRACT: In safety related applications and in products with long lifetimes reliability is a must. Moreover, facing future technology nodes of integrated circuit device level reliability may decrease, i.e., counter-measures have to be taken to ensure product level reliability. But assessing the reliability of a large system is not a trivial task. This paper revisits the state-of-the-art in reliability evaluation starting from the physical device level, to the software system level, all the way up to the product level. Relevant standards and future trends are discussed

  147. Simulating reader-to-reader interference in RFID systems
    R. Ferrero, F. Gandino, L. Zhang, B. Montrucchio, M. Rebaudengo
    DOI: 10.1109/WAINA.2013.90
    KEYWORDS: topology; rfid; reader-to-reader interference; anti-collision protocol; mobility model; network modeling
    ABSTRACT: Reader-to-reader interference significantly affects the performance of RFID applications. The design of an RFID system should carefully consider this phenomenon. Simulation can dramatically speed up the design and testing phase, by deferring the implementation of a prototype to the last phase of the development. Unfortunately, no specific simulators of interference in RFID networks are currently available. Previous works exploited either general purpose network simulators, which often do not provide the required features for simulating an RFID network, or self deployed tools, which are not publicly available and therefore do not allow the validation and reproducibility of the results. This paper identifies the requirements that a simulator of reader-to-reader interference should satisfy and presents the R2RIS simulator, which has been specifically designed to evaluate the performance of reader-to reader anti-collision protocols

  148. Simulation and evaluation of the interference models for RFID reader-to-reader collisions
    L. Zhang, R. Ferrero, F. Gandino, M. Rebaudengo
    Proceedings of 11th International Conference on Advances in Mobile Computing & Multimedia (MoMM2013)
    DOI: 10.1145/2536853.2536877
    KEYWORDS: performance evaluation; additive interference model; rfid; unit disk graph
    ABSTRACT: When numerous RFID readers are placed in the same area, they may interfere with each other due to the reader collision problem. In recent years, many studies have been presented to address the reader collision problem. However, there is no consonance on the interference model to use in the analysis of the protocols. The main adopted models are the single interference model, which is simple and fast, but only consid- ers the readers within a threshold distance, and the additive interference model, which sums the interferences of all the concurrent interrogations. Recent studies have shown that the single interference model cannot detect a relevant part of the possible collisions detected by the additive one. This paper analyzes and compares the network performance of an RFID system by applying both the models. Considering two proposed scenarios, the performance of the two models are evaluated and presented

  149. Validation and robustness assessment of an automotive system
    M. Desogus, M. Sonza Reorda, L. Sterpone, V. Avantaggiati, G. Audisio, M. Sabatini
    Proceedings of 8th IEEE International Design & Test Symposium
    KEYWORDS: embedded system; debug; soc; validation; fpga
    ABSTRACT: Due to the growing complexity of automotive systems, including various modules (e.g., microcontrollers, DSPs, memories and IP cores), validation and debug have become increasingly complex, with consequent impact on time-to-market and quality. In this paper we propose a novel flow for hardware and software validation and debug through the use of an FPGA-based emulation platform, which provides a valuable support for these important phases of the development flow. The same emulation platform is also able to support faults injection in the device under validation. Fault injection is intended not only to provide an evaluation of the system fault tolerance, but also to support the debug of the embedded fault tolerance mechanisms. Experimental results on a real industrial case study allow to evaluate the effectiveness and costs of the proposed solution

  150. A Comparison between Single and Additive Contribution in RFID Reader-to-Reader Interference Models
    L. Zhang, R. Ferrero, F. Gandino, M. Rebaudengo
    DOI: 10.1109/IMIS.2012.122
    KEYWORDS: reader-to-reader collision; rfid; interference models
    ABSTRACT: The RFID reader-to-reader collision is a wellknown interference problem that affects large RFID systems with many readers. In recent years, several anti-collision protocols have been proposed in order to address this problem. However, the evaluation of these approaches is often based on simple models that consider only direct collisions among two readers. Instead, more complex models capture the total signal power emitted by each reader and assume that the power of each signal decays as distance grows. In this paper, the main models of the two families are described, and a comparison is presented, in order to investigate their effectiveness for the study and the evaluation of reader-to-reader collision

  151. A New Fault Injection Approach for Testing Network-on-Chips
    L. Sterpone, D. Sabena, M. Sonza Reorda
    DOI: 10.1109/PDP.2012.82
    ABSTRACT: Packet-based on-chip interconnection networks, or Network-on-Chips (NoCs) are progressively replacing global on-chip interconnections in Multi-processor System-on-Chips (MP-SoCs) thanks to better performances and lower power consumption. However, modern generations of MP-SoCs have an increasing sensitivity to faults due to the progressive shrinking technology. Consequently, in order to evaluate the fault sensitivity in NoC architectures, there is the need of accurate test solution which allows to evaluate the fault tolerance capability of NoCs. This paper presents an innovative test architecture based on a dual-processor system which is able to extensively test mesh based NoCs. The proposed solution improves previously developed methods since it is based on a NoC physical implementation which allows to investigate the effects induced by several kind of faults thanks to the execution of on-line fault injection within all the network interface and router resources during NoC run-time operations. The solution has been physically implemented on an FPGA platform using a NoC emulation model adopting standard communication protocols. The obtained results demonstrated the effectiveness of the developed solution in term of testability and diagnostic capabilities and make our solutions suitable for testing large scale NoC design

  152. A New SBST Algorithm for Testing the Register File of VLIW Processors
    L. Sterpone, D. Sabena, M. Sonza Reorda

  153. A SBST strategy to test microprocessors' branch target buffer
    P. Bernardi, L. Ciganda, M. Grosso, E. Sanchez, M. Sonza Reorda
    KEYWORDS: testing, microprocessors, branch prediction, sbst, branch target buffer
    ABSTRACT: A Branch Target Buffer (BTB) is a mechanism to support speculative execution in order to overcome the performance penalty caused by branch instructions in pipelined microprocessors. Being an intrinsically fault tolerant unit, it is hard to achieve a good fault coverage resorting to plain functional testing methods. In this paper we analyze the causes for low functional testability and propose some techniques able to effectively face these issues. In particular, we describe a strategy to perform SBST on fully associative BTB units. The unit's general structure is analyzed, a suitable test program is proposed and the strategy to observe the test responses is explained. Feasibility and effectiveness of the proposed approach are shown on a MIPS-like processor

  154. A new IP core for fast error detection and fault tolerance in COTS-based solid state mass memories
    E. Costenaro, M. Violante, D. Alexandrescu
    DOI: 10.1109/IOLTS.2011.5993810

  155. A scalable platform for run-time reconfigurable satellite payload processing
    J. Hagemeyer, A. Hilgenstein, D. Jungewelter, D. Cozzi, C. Felicetti, U. Rueckert, S. Korf, M. Koester, F. Margaglia, M. Porrmann, F. Dittmann, M. Ditze, J. Harris, L. Sterpone, J. Ilstad
    DOI: 10.1109/AHS.2012.6268642
    KEYWORDS: fpga; fault tolerance; reconfiguration

  156. Accurate simulation of SEUs in the configuration memory of SRAM-based FPGAs
    C. Bernardeschi, L. Cassano, A. Domenici, L. Sterpone
    DOI: 10.1109/DFT.2012.6378210
    KEYWORDS: fault tolerance; seu; fpga

  157. An hybrid architecture to detect transient faults in microprocessors: An experimental validation
    V. Campagna S.
    ABSTRACT: Due to performance issues commercial off the shelf components are becoming more and more appealing in application fields where fault tolerant computing is mandatory. As a result, to cope with the intrinsic unreliability of such components against certain fault types like those induced by ionizing radiations, cost-effective fault tolerant architectures are needed. In this paper we present an in-depth experimental evaluation of a hybrid architecture to detect transient faults affecting microprocessors. The architecture leverages an hypervisor-based task-level redundancy scheme that operates in conjunction with a custom-developed hardware module. The experimental evaluation shows that our lightweight redundancy scheme is able to effectively cope with malicious faults as those affecting the pipeline of a RISC microprocessor

  158. Automatic Generation of On-Line Test Programs through a Cooperation Scheme
    L. Ciganda, M. Gaudesi, E. Lutton, E. Sanchez, G. Squillero, A. Tonda
    DOI: 10.1109/MTV.2012.17
    KEYWORDS: group evolution; software-based self-test; on-line testing; pipelined processors; soc
    ABSTRACT: Test programs for Software-based Self-Test (SBST) can be exploited during the mission phase of microprocessor-based systems to periodically assess hardware integrity. However, several additional constraints must be imposed due to the coexistence of test programs with the mission application. This paper proposes a method for the generation of SBST on-line test programs for embedded RISC processors, systems where the impact of on-line constraints is significant. The proposed strategy exploits an evolutionary optimizer that is able to create a complete test set of programs relying on a new cooperative scheme. Experimental results showed high fault coverage values on two different modules of a MIPS-like processor core. These two case studies demonstrate the effectiveness of the technique and the low human effort required for its implementation

  159. Evaluation of the Additive Interference Model for RFID Reader Collision Problem
    L. Zhang, F. Gandino, R. Ferrero, M. Rebaudengo
    KEYWORDS: reader-to-reader collision; interference models; rfid
    ABSTRACT: The reader collision problem is a critical issue in RFID systems, since it affects the reliability and the efficiency of the network. Although several solutions have been proposed to address the reader collision problem, they are usually based on models that consider only direct collisions among two readers. In real deployments, the additive interference model that captures the accumulation of n concurrent readers' interference is more accurate. Furthermore, even if an additive interference model is considered, it is important to decide how many concurrent readers' interferences have to be considered. The value of n determines a trade-off between the reliability and the efficiency of the RFID system. In this paper, the additive interference model with different values of n is evaluated. The proposed model provides an evaluation tool to select a suitable value of n according to the system requirements and the simulation results have shown the impact of n in a specific deployment

  160. High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies
    C. Bolchini, A. Miele, C. Sandionigi, M. Ottavi, S. Pontarelli, A. Salsano, C. Metra, M. Omana, D. Rossi, M. Sonza Reorda, L. Sterpone, M. Violante, S. Gerardin, M. Bagatin, A. Paccagnella
    DOI: 10.1109/DFT.2012.6378211
    ABSTRACT: This paper reports the main contribution of a project devoted to the definition of techniques to design and evaluate fault tolerant systems implemented using the SoPC paradigm, suitable for missionand safety-critical application environments. In particular, the effort of the five involved research units has been devoted to address some of the main issues related to the specific technological aspects introduced by these flexible platforms. The overall target of the research is the development of a design methodology for highly reliable systems realized on reconfigurable platforms based on a System-on-Programmable Chip (SoPC), as discussed in the next section

  161. Latch-up test measurement for long duration space missions
    L. Sterpone, R. Mancini, D. Gelfusa
    DOI: 10.1109/I2MTC.2012.6229561
    KEYWORDS: asic latch-up; radiation; test

  162. On the Functional Test of Branch Prediction Units Based on the Branch History Table Architecture
    E. Sanchez, M. Sonza Reorda, A.P. Tonda
    VLSI-SoC: Advanced Research for Systems on Chip 19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2011, Hong Kong, China, October 3-5, 2011, Revised Selected Papers
    DOI: 10.1007/978-3-642-32770-4
    ABSTRACT: Branch Prediction Units (BPUs) are commonly used in pipelined processors, since they can significantly decrease the negative impact of branches in superscalar and RISC architectures. Traditional solutions, mainly based on scan, are often inadequate to effectively test these modules: in particular, scan does not represent a viable solution when Incoming Inspection or on-line test are considered. Functional test may stand as an effective solution in these situations, but requires effective algorithms to be available. In this paper we propose a functional approach targeting the test of BPUs based on the Branch History Table (BHT) architecture; the proposed approach is independent on the specific implementation of the BPU, and is thus widely applicable. Its effectiveness has been validated on a BPU resorting to an open-source computer architecture simulator and to an ad hoc developed HDL testbench. Experimental results show that the proposed method is able to thoroughly test the BPU, reaching complete static fault coverage with reasonable requirements in terms of test program size and execution time

  163. On the development of Software-Based Self-Test methods for VLIW processors
    D. Sabena, M. Sonza Reorda, L. Sterpone
    DOI: 10.1109/DFT.2012.6378194
    KEYWORDS: vliw; fault simulation; sbst
    ABSTRACT: Software-Based Self-Test (SBST) approaches are an effective solution for detecting permanent faults; this technique has been widely used with a good success on generic processors and processors-based architectures; however, when VLIW processors are addressed, traditional SBST techniques and algorithms must be adapted to each particular VLIW architecture. In this paper, we present a method that formalizes the development flow to write effective SBST programs for VLIW processors, starting from known algorithms addressing traditional processors. In particular, the method addresses the parallel Functional Units, such as ALUs and MULs, embedded into a VLIW processor. Fault simulation campaigns confirm the validity of the proposed method

  164. On the functional test of L2 caches
    M. Riga, E. Sanchez, M. Sonza Reorda
    KEYWORDS: sbst; functional testing; l2 cache testing
    ABSTRACT: Caches are crucial components in today's processors (both stand-alone or integrated into SoCs) and they account for a growing percentage of the occupied silicon area. Therefore, their test (both at the end of the manufacturing and on-line) is crucial for the quality and reliability of the whole product. While in many cases cache test is based on Design for Testability (DfT) techniques, there are situations in which the functional approach is the only viable one. Previous papers addressed the issue of developing test programs for testing caches: since the constant trend is to organize them in different levels, in this paper we address the test of second level caches (L2). To the best of our knowledge, the paper presents the first functional test method for L2 caches: some experimental results also are provided to assess its effectiveness on the OpenSPARC T1 processor

  165. On the optimized generation of Software-Based Self-Test programs for VLIW processors
    D. Sabena, M. Sonza Reorda, L. Sterpone
    DOI: 10.1109/VLSI-SoC.2012.6379018
    KEYWORDS: test program generation; sbst; vliw
    ABSTRACT: Software-Based Self-Test (SBST) approaches have shown to be an effective solution to detect permanent faults, both at the end of the production process, and during the operational phase. However, when Very Long Instruction Word (VLIW) processors are addressed these techniques require some optimization steps in order to properly exploit the parallelism intrinsic in these architectures. In this paper we present a new method that, starting from previously known algorithms, automatically generates an effective test program able to still reach high fault coverage on the VLIW processor under test, while reducing the test duration and the test code size. The method consists of three parametric phases and can deal with different VLIW processor models. The main goal of the proposed method is to automatically obtain a test program able to effectively reduce the test time and the required resources. Experimental results gathered on a case study show the effectiveness of the proposed approach

  166. On-Line Software-Based Self-Test of the Address Calculation Unit in RISC Processors
    P. Bernardi, L. Ciganda, M. De Carvalho, M. Grosso, J. Lagos-Benites, E. Sanchez, M. Sonza Reorda, O. Ballan

  167. On-line test of embedded systems: Which role for functional test?
    M. Sonza Reorda
    DOI: 10.1109/DDECS.2012.6219007

  168. Peak Power Estimation: A Case Study on CPU Cores
    P. Bernardi, M. De Carvalho, E. Sanchez, M. Sonza Reorda, A. Bosio, L. Dilillo, P. Girard, M. Valka
    DOI: 10.1109/ATS.2012.58

  169. SEU effects on power consumption in FPGAs
    A. Aloisio, V. Bocci, G. Chiodi, R. Giordano, V. Izzo, L. Sterpone, M. Violante
    DOI: 10.1109/RTC.2012.6418110
    KEYWORDS: power consumption; fpga; seu

  170. A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing
    M. Valka, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, E. Sanchez, M. De Carvalho, M. Sonza Reorda
    DOI: 10.1109/ETS.2011.21

  171. A Low-cost Emulation System for Fast Co-verification and Debug
    J. Lagos-Benites, M. Grosso, L. Sterpone, M. Sonza Reorda, G. Audisio, M. Pipponzi, M. Sabatini
    DOI: 10.1109/ETS.2011.32
    KEYWORDS: verification; validation; fpga; soc

  172. A New Reconfigurable Clock-gating Technique for Low Power SRAM-based FPGAs
    L. Sterpone, D. Matos, L. Carro, S. Wong, F. Anjam

  173. A general approach for improving RNS Montgomery exponentiation using pre-processing
    F. Gandino, F. Lamberti, J. Bajard, P. Montuschi
    Proc. 20th IEEE Symposium on Computer Arithmetic (ARITH2011)
    DOI: 10.1109/ARITH.2011.35

  174. A new Architecture to Cross-Fertilize On-line and Manufacturing Testing
    P. Bernardi, M. Sonza Reorda

  175. A novel access scheme for online test in RFID memories
    R. Sanchez E.R.
    DOI: 10.1109/LASCAS.2011.5750307
    KEYWORDS: online test; rfid

  176. Adaptive fuzzy-MAC for power reduction in wireless sensor networks
    E. Sanchez, B. Montrucchio, L. Murillo, M. Rebaudengo
    DOI: 10.1109/NTMS.2011.5720629
    KEYWORDS: preamble sampling; fuzzy logic; wireless sensor networks; mac
    ABSTRACT: Wireless Sensor Networks (WSNs) are used in an increasing number of applications in different fields, from agricultural monitoring to energy-saving systems for buildings. The development of WSNs has been always constrained by the power consumption of nodes that constitute the network since they should be as much autonomous as possible and human intervention must be reduced to the minimum. Several algorithms and protocols have been designed with the goal of reducing power consumption. Related works take into consideration Media Access Control (MAC) protocols that keep sensors' power consumption low at that layer. Nevertheless, these protocols require some parameters, e.g. duty cycle, to be configured according to network characteristics in order to achieve an acceptable level of efficiency. In this work, we propose a Fuzzy Logic Controller (FLC) which adapts the MAC protocol parameters by employing local node inputs such as battery power and average packet traffic. We present the FLC design and perform simulations that show its feasibility. We evaluate the FLC in terms of its power savings capabilities and show that for high-traffic and low-energy nodes power consumption may be reduced up to 50%

  177. Adaptive opponent modelling for the iterated prisoner's dilemma
    E. Piccolo, G. Squillero
    DOI: 10.1109/CEC.2011.5949705
    ABSTRACT: This paper describes the design of Laran, an intelligent player for the iterated prisoner's dilemma. Laran is based on an evolutionary algorithm, but instead of using evolution as a mean to define a suitable strategy, it uses evolution to model the behavior of its adversary. In some sense, it understands its opponent, and then exploits such knowledge to devise the best possible conduct. The internal model of the opponent is continuously adapted during the game to match the actual outcome of the game, taking into consideration all played actions. Whether the model is correct, Laran is likely to gain constant advantages and eventually win. A prototype of the proposed approach was matched against twenty players implementing state-of-the art strategies. Results clearly demonstrated the claims

  178. An Effective Methodology for On-line Testing of Embedded Microprocessors
    P. Bernardi, L. Ciganda, E. Sanchez, M. Sonza Reorda
    DOI: 10.1109/IOLTS.2011.5994541
    KEYWORDS: on-line test; microprocessor test; hardware bist

  179. An FPGA-emulation-based platform for characterization of digital baseband communication systems
    J. Lagos-Benites, M. Grosso, M. Sonza Reorda, G. Audisio, M. Pipponzi, M. Sabatini, V. Avantaggiati
    DOI: 10.1109/DFT.2011.1

  180. An adaptive power-aware multi-hop routing algorithm for wireless sensor networks
    E. Sanchez, L. Murillo, B. Montrucchio, M. Rebaudengo
    DOI: 10.1109/ITNG.2011.27
    KEYWORDS: wireless sensor network; adaptive routing algorithm

  181. An adaptively reconfigurable computing framework for intelligent robotics
    M. Hussain, A. Din, M. Violante, B. Bona

  182. Analysis of SEU Effects in Partially Reconfigurable SoPCs
    L. Sterpone, F. Margaglia, M. Koester, J. Hagemeyer, M. Porrman
    DOI: 10.1109/AHS.2011.5963926

  183. Automatic Generation of Software-based Functional Failing Test for Speed Debug and On-silicon Timing Verification2011 12th International Workshop on Microprocessor Test and Verification
    E. Sanchez, G. Squillero, A. Tonda
    2011 12th International Workshop on Microprocessor Test and Verification
    DOI: 10.1109/MTV.2011.19
    ABSTRACT: The 40 years since the appearance of the Intel 4004 deeply changed how microprocessors are designed. Today, essential steps in the validation process are performed relying on physical dices, analyzing the actual behavior under appropriate stimuli. This paper presents a methodology that can be used to devise assembly programs suitable for a range of on-silicon activities, like speed debug, timing verification or speed binning. The methodology is fully automatic. It exploits the feedback from the microprocessor under examination and does not rely on information about its microarchitecture, nor does it require design-for-debug features. The experimental evaluation performed on a Intel Pentium Core i7-950 demonstrates the feasibility of the approach

  184. Control flow checking through embedded debug interface
    L. Parra, A. Lindoso, M. Portela, L. Entrena, M. Grosso, M. Sonza Reorda

  185. Covariance Matrix Adaptation Evolutionary Strategy for Drift Correction of Electronic Nose Data
    S. Di Carlo, M. Falasconi, E. Sanchez, G. Sberveglieri, A. Scionti, G. Squillero, A. Tonda
    AIP CONFERENCE PROCEEDINGS
    DOI: 10.1063/1.3626293
    KEYWORDS: sensor drift; data acquisition; optimisation; self-organising feature maps; chemical sensors; pattern recognition; bioinformatics
    ABSTRACT: Electronic Noses (ENs) might represent a simple, fast, high sample throughput and economic alternative to conventional analytical instruments. However, gas sensors drift still limits the EN adoption in real industrial setups due to high recalibration effort and cost. In fact, pattern recognition (PaRC) models built in the training phase become useless after a period of time, in some cases a few weeks. Although algorithms to mitigate the drift date back to the early 90 this is still a challenging issue for the chemical sensor community. Among other approaches, adaptive drift correction methods adjust the PaRC model in parallel with data acquisition without need of periodic calibration. Self-Organizing Maps (SOMs) and Adaptive Resonance Theory (ART) networks have been already tested in the past with fair success. This paper presents and discusses an original methodology based on a Covariance Matrix Adaptation Evolution Strategy (CMA-ES), suited for stochastic optimization of complex problems

  186. Degree Distribution of Unit Disk Graphs with Uniformly Deployed Nodes on a Rectangular Surface
    F. R. Ferrero
    DOI: 10.1109/BWCCA.2011.38
    KEYWORDS: wireless network modeling; degree distribution; unit disk graph

  187. Efficient energy-aware routing for sensor networks
    E. Sanchez, L. Murillo, B. Montrucchio, M. Rebaudengo
    DOI: 10.1109/LASCAS.2011.5750315
    KEYWORDS: wireless sensor networks; energy-aware; routing protocols
    ABSTRACT: The energy and computational constraints of Wireless Sensor Networks (WSN) have motivated the exploration of efficient routing algorithms. In this paper, a new routing approach is presented which attains the best trade-off between energy expenditure and hop-distance to the sink. The routing algorithm exploits a low-computation metric based on the node's remaining battery. Routing is performed by means of a modified Dijkstra's algorithm which calculates the node's position in the routing tree while computes the least-cost path of all nodes towards the sink. Simulations were performed for different network densities demonstrating that the proposed algorithm enhances the overall energy conservation of the network while efficiently routing data traffic

  188. Evaluation Framework of Opportunistic Flooding in Wireless Sensor Networks
    L. Zhang, E. Sanchez Sanchez, M. Rebaudengo

  189. Evolution of Test Programs Exploiting a FSM Processor Model
    E. Sanchez, G. Squillero, A. Tonda
    Lecture Notes in Computer Science (vol 6625)
    DOI: 10.1007/978-3-642-20520-0_17
    ABSTRACT: Microprocessor testing is becoming a challenging task, due to the increasing complexity of modern architectures. Nowadays, most architectures are tackled with a combination of scan chains and Software-Based Self-Test (SBST) methodologies. Among SBST techniques, evolutionary feedback-based ones prove effective in microprocessor testing: their main disadvantage, however, is the considerable time required to generate suitable test programs. A novel evolutionary-based approach, able to appreciably reduce the generation time, is presented. The proposed method exploits a high-level representation of the architecture under test and a dynamically built Finite State Machine (FSM) model to assess fault coverage without resorting to time-expensive simulations on low-level models. Experimental results, performed on an OpenRISC processor, show that the resulting test obtains a nearly complete fault coverage against the targeted fault model

  190. Evolutionary failing-test generation for modern microprocessors
    E. Sanchez, G. Squillero, A. Tonda
    GECCO '11 Proceedings of the 13th annual conference companion on Genetic and evolutionary computation
    DOI: 10.1145/2001858.2001985
    ABSTRACT: The incessant progress in manufacturing technology is posing new challenges to microprocessor designers. Nowadays, comprehensive verification of a chip can only be performed after tape-out, when the first silicon prototypes are available. Several activities that were originally supposed to be part of the pre-silicon design phase are migrating to this post-silicon time as well. The short paper describes a post-silicon methodology that can be exploited to devise functional failing tests. Such tests are essential to analyze and debug speed paths during verification, speed-stepping, and other critical activities. The proposed methodology is based on the Genetic Programming paradigm, and exploits a versatile toolkit named µGP. The paper demonstrates that an evolutionary algorithm can successfully tackle a significant and still open industrial problem. Moreover, it shows how to take into account complex hardware characteristics and architectural details of such complex devices

  191. Fault Injection Analysis of Transient Faults in Clustered VLIW Processors
    L. Sterpone, D. Sabena, S. Campagna, M. Sonza Reorda

  192. Fault grading of software-based self-test procedures for dependable automotive applications
    P. Bernardi, M. Grosso, E. Sanchez, O. Ballan

  193. Functional test generation for the pLRU replacement mechanism of embedded cache memories
    W. Perez Holgin, E. Sanchez, M. Sonza Reorda, A. Tonda, J. Velasco-Medina
    DOI: 10.1109/LATW.2011.5985898
    ABSTRACT: Testing cache memories is a challenging task, especially when targeting complex and high-frequency devices such as modern processors. While the memory array in a cache is usually tested exploiting BIST circuits that implement March-based solutions, there is no established methodology to tackle the cache controller logic, mainly due to its limited accessibility. One possible approach is Software-Based Self Testing (SBST): however, devising test programs able to thoroughly excite the replacement logic and made the results observable is not trivial. A test program generation approach, based on a Finite State Machine (FSM) model of the replacement mechanism, is proposed in this paper. The effectiveness of the method is assessed on a case study considering a data cache implementing the pLRU replacement policy

  194. Group evolution: Emerging synergy through a coordinated effort
    E. Sanchez, G. Squillero, A. Tonda
    Evolutionary Computation (CEC), 2011 IEEE Congress on
    DOI: 10.1109/CEC.2011.5949951
    ABSTRACT: Abstract-A huge number of optimization problems, in the CAD area as well as in many other fields, require a solution composed by a set of structurally homogeneous elements. Each element tackles a subset of the original task, and they cumulatively solve the whole problem. Sub-tasks, however, have exactly the same structure, and the splitting is completely arbitrary. Even the number of sub-tasks is not known and cannot be determined a-priori. Individual elements are structurally homogeneous, and their contribution to the main solution can be evaluated separately. We propose an evolutionary algorithm able to optimize groups of individuals for solving this class of problems. An individual of the best solution may be sub-optimal when considered alone, but the set of individuals cumulatively represent the optimal group able to completely solve the whole problem. Results of preliminary experiments show that our algorithm performs better than other techniques commonly applied in the CAD field

  195. Implementing a safe embedded computing system in SRAM-based FPGAs using IP cores: A case study based on the Altera NIOS-II soft processor
    J. Perez Acle, M. Sonza Reorda, M. Violante
    DOI: 10.1109/LASCAS.2011.5750278

  196. Increasing Throughput in RFID Multi-Reader Environments Avoiding Reader-to-Reader Collisions
    F. Gandino, R. Ferrero, B. Montrucchio, M. Rebaudengo
    DOI: 10.1109/ICCE.2011.5722638
    KEYWORDS: rfid; reader-to-reader collision

  197. La formazione a distanza al Politecnico di Torino: nuovi modelli e strumenti
    S. Barbagallo, R. Bertonasco, F. Corno, M. Mezzalama, M. Sonza Reorda, E. Venuto

  198. Lamps: A Test Problem for Cooperative Coevolution
    A. Tonda, E. Lutton, G. Squillero
    Nature Inspired Cooperative Strategies for Optimization
    DOI: 10.1007/978-3-642-24094-2_7
    ABSTRACT: We present an analysis of the behaviour of Cooperative Co-evolution algorithms (CCEAs) on a simple test problem, that is the optimal placement of a set of lamps in a square room, for various problems sizes. Cooperative Co-evolution makes it possible to exploit more efficiently the artificial Darwinism scheme, as soon as it is possible to turn the optimisation problem into a co-evolution of interdependent sub-parts of the searched solution. We show here how two cooperative strategies, Group Evolution (GE) and Parisian Evolution (PE) can be built for the lamps problem. An experimental analysis then compares a classical evolution to GE and PE, and analyses their behaviour with respect to scale

  199. Monitoring and modeling building energy expenditure with sensor networks
    E. Sanchez, B. Montrucchio, M. Rebaudengo

  200. On the Functional Test of Branch Prediction Units based on Branch History Table
    E. Sanchez, M. Sonza Reorda, A. Tonda

  201. On the Modeling of Gate Delay Faults by Means of Transition Delay Faults
    P. Bernardi, M. Sonza Reorda, A. Bosio, P. Girard, S. Pravossoudovitch
    DOI: 10.1109/DFT.2011.53

  202. On the functional test of MESI controllers
    M. Ernesto Sanchez
    DOI: 10.1109/LATW.2011.5985909

  203. Optimized embedded memory diagnosis
    M. De Carvalho, P. Bernardi, M. Sonza Reorda, N. Campanelli, T. Kerekes, D. Appello, M. Barone, V. Tancorre, M. Terzi
    DOI: 10.1109/DDECS.2011.5783109

  204. Performance Evaluation of Reliable and Unreliable Opportunistic Flooding in Wireless Sensor Network
    L. Zhang, E. Sanchez Sanchez, M. Rebaudengo
    DOI: 10.1109/ICON.2011.6168498

  205. Post-silicon failing-test generation through evolutionary computation
    E. Sanchez, G. Squillero, A. Tonda
    DOI: 10.1109/VLSISoC.2011.6081667
    ABSTRACT: The incessant progress in manufacturing technology is posing new challenges to microprocessor designers. Several activities that were originally supposed to be part of the pre-silicon design phase are migrating after tape-out, when the first silicon prototypes are available. The paper describes a post-silicon methodology for devising functional failing tests. Therefore, suited to be exploited by microprocessor producer to detect, analyze and debug speed paths during verification, speed-stepping, or other critical activities. The proposed methodology is based on an evolutionary algorithm and exploits a versatile toolkit named µGP. The paper describes how to take into account complex hardware characteristics and architectural details of such complex devices. The experimental evaluation clearly demonstrates the potential of this line of research

  206. A New Placement Algorithm for the Mitigation of Multiple Cell Upsets in SRAM-based FPGAs
    L. Sterpone, N. Battezzati
    IEEE Design, Automation and Test in Europe 2010

  207. A Novel Scalable and Reconfigurable Emulation Platform for Embedded Systems Verification
    M. Di Marzio, M. Grosso, M. Sonza Reorda, L. Sterpone, G. Audisio, M. Sabatini
    Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
    DOI: 10.1109/ISCAS.2010.5537422

  208. A Programmable BIST for DRAM Testing and Diagnosis
    M. Grosso, P. Bernardi, M. Sonza Reorda, Y. Zhang

  209. A Software-based self-test methodology for system peripherals
    M. Grosso, H. Perez, D. Ravotto, E. Sanchez, M. Sonza Reorda, J. Velasco Medina
    KEYWORDS: cache; processori; collaudo

  210. A fault grading methodology for software-based self-test programs in systems-on-chip
    O. Ballan, P. Bernardi, G. Fontana, M. Grosso, E. Sanchez
    DOI: 10.1109/MTV.2010.16

  211. A framework to support the design of COTS-based reliable space computers for on-board data handling
    V. Campagna S.
    DOI: 10.1109/IOLTS.2010.5560229

  212. A hardware accelerated framework for the generation of design validation programs for SMT processors
    E. Sanchez, D. Ravotto, M. Sonza Reorda
    13th IEEE International Symposium on Design & Diagnostics of Elctronic Circuits and Systems

  213. A new framework for the automatic insertion of mitigation structures in circuits netlists
    N. Battezzati, D. Serrone, M. Violante

  214. A tester architecture suitable for MEMS calibration and testing
    L. Ciganda, P. Bernardi, M. Sonza Reorda, D. Barbieri, M. Straiotto, L. Bonaria
    KEYWORDS: mems calibration and testing; tester architecture; parallelism

  215. An Exact and Efficient Critical Path Tracing Algorithm
    A. Bosio, P. Girard, S. Pravossoudovitch, P. Bernardi, M. Sonza Reorda
    DOI: 10.1109/DELTA.2010.35

  216. An On-line Fault Detection Technique based on Embedded Debug Features
    M. Grosso, M. Sonza Reorda, M. Portela-Garcia, M. Garcia-Valderas, C. Lopez-Ongil, L. Entrena
    KEYWORDS: debug; circuiti integrati; collaudo; affidabilità; processori

  217. An adaptive tester architecture for volume diagnosis
    P. Bernardi, M. Grosso, M. Sonza Reorda
    KEYWORDS: circuiti integrati; ate; collaudo

  218. An enhanced strategy for functional stress pattern generation for system-on-chip reliability characterization
    M. De Carvalho, P. Bernardi, E. Sanchez, M. Sonza Reorda
    KEYWORDS: reliability characterization; automatic stress pattern generation; functional stress; system-on-chip

  219. An integrated flow for the design of hardened circuits on SRAM-based FPGAs
    C. Bolchini, A. Miele, C. Sandionigi, N. Battezzati, L. Sterpone, M. Violante
    DOI: 10.1109/ETSYM.2010.5512757

  220. Analysis of Root Causes of Alpha Sensitivity Variations on Microprocessors Manufactured using Different Cell Layouts
    P. Rech, M. Grosso, F. Melchiori, D. Loparco, D. Appello, L. Dilillo, A. Paccagnella, M. Sonza Reorda
    KEYWORDS: fault tolerance circuiti integrati radiazioni

  221. Application-oriented SEU cross-section of a processor soft core for Atmel RHBD FPGAs
    N. Battezzati, F. Margaglia, M. Violante, F. Decuzzi, D. Merodio Codinachs, B. Bancelin

  222. CUMULATIVE EMBEDDED MEMORY FAILURE BITMAP DISPLAY ANALYSIS
    P. Bernardi, A. Panariti, M. Sonza Reorda, T. Kerekes, D. Appello, M. Barone
    13th IEEE International Symposium on Design & Diagnostics of Electronic Circuits and Systems

  223. Cumulative embedded memory failure bitmap display & analysis
    N. Campanelli, T. Kekeres, P. Bernardi, M. De Carvalho, A. Panariti, M. Sonza Reorda, D. Appello, M. Barrone
    DOI: 10.1109/DDECS.2010.5654683
    KEYWORDS: memory test; system-on-chip; bist

  224. Enhanced Observability in Microprocessor-based Systems for Permanent and Transient Fault Resiliency
    L. Entrena, M. Gallardo-Campos, M. Garcia-Valderas, M. Grosso, C. Lopez-Ongil, M. Portela-Garcia, M. Sonza Reorda

  225. Evolving Individual Behavior in a Multi-Agent Traffic Simulator
    E. Sanchez, G. Squillero, A. Tonda
    Applications of Evolutionary Computation
    DOI: 10.1007/978-3-642-12239-2_2

  226. Exploiting Evolution for an Adaptive Drift-Robust Classifier in Chemical Sensing
    S. Di Carlo, M. Falasconi, E. Sanchez, A. Scionti, G. Squillero, A. Tonda
    Proceedings of EvoApplicatons 2010: EvoCOMPLEX, EvoGAMES, EvoIASP, EvoINTELLIGENCE, EvoNUM, and EvoSTOC
    DOI: 10.1007/978-3-642-12239-2_43
    KEYWORDS: real-valued function optimization; parameter optimization; realworld application; chemical sensors; artificial olfaction; bioinformatics
    ABSTRACT: Gas chemical sensors are strongly affected by drift, i.e., changes in sensors' response with time, that may turn statistical models commonly used for classification completely useless after a period of time. This paper presents a new classifier that embeds an adaptive stage able to reduce drift effects. The proposed system exploits a state-of-the-art evolutionary strategy to iteratively tweak the coefficients of a linear transformation able to transparently transform raw measures in order to mitigate the negative effects of the drift. The system operates continuously. The optimal correction strategy is learnt without a-priori models or other hypothesis on the behavior of physical-chemical sensors. Experimental results demonstrate the efficacy of the approach on a real problem

  227. Exploiting Wireless Sensor Networks for Monitoring Building Performance
    D. Apiletti, E. Baralis, T. Cerquitelli, S. Chiusano, B. Montrucchio, L. Murillo, M. Rebaudengo, E. Sanchez, D. Tonelli

  228. Fair Anti-Collision Protocol in Dense RFID Networks
    R. Ferrero, F. Gandino, B. Montrucchio, M. Rebaudengo
    KEYWORDS: reader-to-reader anti-collision; rfid

  229. Functional Test Generation for DMA Controllers
    M. Grosso, W. Perez H, D. Ravotto, E. Sanchez, M. Sonza Reorda, J. Velasco Medina
    11th IEEE Latin-American Test Workshop 2010

  230. Generating Power-Hungry Test Programs for Power-Aware Validation of Pipelined Processors
    A. Calimera, E. Macii, D. Ravotto, E. Sanchez, M. Sonza Reorda

  231. Hypervisor-Based Virtual Hardware for Fault Tolerance in COTS Processors Targeting Space Applications
    S. Campagna, M. Hussain, M. Violante
    DOI: 10.1109/DFT.2010.12

  232. On the mitigation of SET broadening effects in integrated circuits
    B. Sterpone L.
    DOI: 10.1109/DDECS.2010.5491820

  233. Towards Drift Correction in Chemical Sensors Using an Evolutionary Strategy
    S. Di Carlo, M. Falasconi, E. Sanchez, A. Scionti, G. Squillero, A. Tonda
    Proceedings of the ACM 12th Annual Conference on Genetic and Evolutionary Computation (GECCO)
    DOI: 10.1145/1830483.1830727
    KEYWORDS: algorithms applications; artificial olfaction; drift correction; evolutionary strategies; bioinformatics
    ABSTRACT: Gas chemical sensors are strongly affected by the so-called drift, i.e., changes in sensors' response caused by poisoning and aging that may significantly spoil the measures gathered. The paper presents a mechanism able to correct drift, that is: delivering a correct unbiased fingerprint to the end user. The proposed system exploits a state-of-the-art evolutionary strategy to iteratively tweak the coefficients of a linear transformation. The system operates continuously. The optimal correction strategy is learnt without a-priori models or other hypothesis on the behavior of physical-chemical sensors. Experimental results demonstrate the efficacy of the approach on a real problem

  234. A Deterministic Methodology for Identifying Functionally Untestable Path-Delay Faults in Microprocessor Cores
    P. Bernardi, M. Grosso, E. Sanchez, M. Sonza Reorda
    9th International Workshop on Microprocessor Test and Verification (MTV'08)
    DOI: 10.1109/MTV.2008.9

  235. A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips
    M. Sonza Reorda, M. Violante, C. Meinhardt, R. Reis
    Design, Automation & Test in Europe Conference & Exhibition (DATE '09)

  236. A low-cost solution for developing reliable Linux-based space computers for on-board data handling
    M. Violante, M. Esposti
    DOI: 10.1109/IOLTS.2009.5195982

  237. A new RC design for mixed-grain based dynamically reconfigurable architectures
    E. Rhod, L. Sterpone, L. Carro
    IEEE International Conference on Electronics Circuits and Systems
    DOI: 10.1109/ICECS.2009.5410843

  238. A study of the Single Event Effects Impact on Functional Mapping within Flash-based FPGAs
    F. Abate, F. Lima Kastensmidt, L. Sterpone, M. Violante
    DATE'09

  239. An Enhanced FPGA-Based Low-Cost Tester Platform Exploiting Effective Test Data Compression for SoCs
    L. Ciganda, F. Abate, P. Bernardi, M. Bruno, M. Sonza Reorda
    12th IEEE Symposium on Design and Diagnostics of Electronic Systems (DDECS)

  240. An I-IP Based Approach for the Monitoring of NBTI Effects in SoCs
    D. Appello, P. Bernardi, C. Guardiani, A. Shibkov, A. Brambilla, G. Storti Gajani, F. Piazza
    IEEE Internation On-Line Test Symposium (IOLTS'09)
    DOI: 10.1109/IOLTS.2009.5195977

  241. An In-Vehicle Infotainment Software Architecture Based on Google Android
    G. Macario, M. Torchiano, M. Violante
    IEEE Symposium on Industrial Embedded Systems (SIES) 2009
    DOI: 10.1109/SIES.2009.5196223
    ABSTRACT: The automotive infotainment industry is currently pressured with many challenges. Tier-one manufactures must accommodate disparate and quickly changing features for different carmakers. Moreover, the use of a dedicated platform for each brand and model is no more viable. The use of an open platform would permit sharing costs across the whole customer spectrum, and it will allow products to grow and adapt to the user preferences, by providing the possibility of executing third-party applications. Google Android is a recent operating system, designed for mobile devices that perfectly fits to embedded devices such as those used for automotive infotainment. In this paper we present a proof-of-concept architecture developed in cooperation between Magneti Marelli and Politecnico di Torino, whose main contribution is an automotive-oriented extension of Google Android that provides features for combining extendibility and safety requirements

  242. An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAs
    M. Sonza Reorda, M. Violante, C. Meinhardt
    24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009 (DFT09)
    DOI: 10.1109/DFT.2009.35

  243. An efficient fault simulation technique for transition faults in non-scan sequential circuits
    A. Bosio, P. Girard, S. Pravossoudovich, P. Bernardi, M. Sonza Reorda
    Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009
    DOI: 10.1109/DDECS.2009.5012098
    ABSTRACT: This paper proposes an efficient technique for transition delay fault coverage measurement in synchronous sequential circuits. The proposed strategy is based on a combination of multi-valued algebra simulation, critical path tracing and deductive fault simulation. The main advantages of the proposed approach are that it is highly computationally efficient with respect to state-of-the-art fault simulation techniques, and that it encompasses different delay sizes in one simulation pass without resorting to an improved transition fault model. Preliminary results on ITC'99 benchmarks show that the gain in terms of CPU time is up to one order of magnitude compared to previous existing techniques

  244. An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs
    L. Ciganda, F. Abate, P. Bernardi, M. Bruno, M. Sonza Reorda
    DOI: 10.1109/DDECS.2009.5012141
    KEYWORDS: fpga based tester; test compression/decompression

  245. Application-oriented SEU sensitiveness analysis of Atmel rad-hard FPGAs
    N. Battezzati, F. Decuzzi, M. Violante, M. Briet
    Proceedings of the 15th IEEE International On-Line Testing Symposium

  246. Automatic Detection of Software Defects: an Industrial Experience
    S. Gandini, D. Ravotto, W. Ruzzarin, E. Sanchez, G. Squillero, A. Tonda
    Proceedings GECCO 2009

  247. Automatic Functional Stress Pattern Generation for SoC Reliability Characterization
    D. Appello, P. Bernardi, R. Cagliesi, M. Giancarlini, M. Grosso, E. Sanchez, M. Sonza Reorda
    DOI: 10.1109/ETS.2009.16

  248. Curricula design flow with embedded accreditation
    D. Del Corso, M. Gola, M. Rebaudengo
    DOI: 10.1109/EAEEIE.2009.5335480
    ABSTRACT: EAEEIE Annual Conference, Valencia, Spain, 22-24 June 2009

  249. Design validation of multithreaded architectures using concurrent threads evolution
    D. Ravotto, E. Sanchez, M. Sonza Reorda, G. Squillero
    22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
    DOI: 10.1145/1601896.1601964

  250. DfT Reuse for Low-Cost Radiation Testing of SoCs: A Case Study
    D. Appello, P. Bernardi, S. Gerardin, M. Grosso, A. Paccagnella, P. Rech, M. Sonza Reorda
    27th IEEE VLSI Test Symposium (VTS '09)
    DOI: 10.1109/VTS.2009.26

  251. Diseño de placas con lógica programable como experiencia educativa en cursos de grado
    S. Fernández, A. Bergeret, L. Ciganda, J. Oliver
    Actas de las IX jornadas de computación reconfigurable y aplicaciones
    KEYWORDS: fpga

  252. Evaluating Alpha-induced Soft Errors in Embedded Microprocessors
    P. Bernardi, M. Grosso, M. Sonza Reorda, D. Appello, P. Rech, S. Gerardin, A. Paccagnella
    IEEE Internation On-Line Test Symposium (IOLTS'09)
    DOI: 10.1109/IOLTS.2009.5195985

  253. Evaluating the impact of DFM library optimizations on alpha-induced SEU sensitivity in a microprocessor core
    P. Rech, A. Paccagnella, M. Grosso, M. Sonza Reorda, F. Melchiori, D. Appello
    DOI: 10.1109/RADECS.2009.5994699

  254. Exploiting Embedded FPGA in On-line Software-based Test Strategies for Microprocessor Cores
    M. Grosso, M. Sonza Reorda
    15th IEEE International On-Line Testing Symposium
    DOI: 10.1109/IOLTS.2009.5195989

  255. Gene expression reliability estimation through cluster-based analysis
    L. Sterpone, A. Benso, Di Carlo.S., G. Politano
    DOI: 10.1109/MEMEA.2009.5167990
    KEYWORDS: bioinformatics; gene expression; image analysis; cdna microarray
    ABSTRACT: Gene expression is the fundamental control of the structure and functions of the cellular versatility and adaptability of any organisms. The measurement of gene expressions is performed on images generated by optical inspection of microarray devices which allow the simultaneous analysis of thousands of genes. The images produced by these devices are used to calculate the expression levels of mRNA in order to draw diagnostic information related to human disease. The quality measures are mandatory in genes classification and in the decision-making diagnostic. However, microarrays are characterized by imperfections due to sample contaminations, scratches, precipitation or imperfect gridding and spot detection. The automatic and efficient quality measurement of microarray is needed in order to discriminate faulty gene expression levels. In this paper we present a new method for estimate the quality degree and the data's reliability of a microarray analysis. The efficiency of the proposed approach in terms of genes expression classification has been demonstrated through a clustering supervised analysis performed on a set of three different histological samples related to the Lymphoma's cancer disease

  256. Improving Preamble Sampling Performance in Wireless Sensor Networks with State Information
    E. Sanchez, C. Chaudet, M. Rebaudengo

  257. Introducing Probability in RFID Reader-to-Reader Anti-collision
    F. Gandino, R. Ferrero, B. Montrucchio, M. Rebaudengo
    The 8th IEEE International Symposium on Network Computing and Applications (IEEE NCA09)

  258. Layout-aware multi-cell upsets effects analysis on TMR circuits implemented on SRAM-based FPGAs
    L. Sterpone, M. Violante, A. Bocquillon, F. Miller, N. Buard, A. Manuzzato, S. Gerardin, A. Pacagnella
    DOI: 10.1109/RADECS.2009.5994561

  259. On the Generation of Functional Test Programs for the Cache Replacement Logic
    W. Perez H, D. Ravotto, E. Sanchez, M. Sonza Reorda, A. Tonda
    Asian Test Symposium, ATS'09

  260. Random Key Pre-Distribution with Transitory Master Key for Wireless Sensor Networks
    F. Gandino, B. Montrucchio, M. Rebaudengo
    CoNEXT Student Workshop'09

  261. Recovery scheme for hardening system on programmable chips
    C. Meinhardt, R. Reis, M. Violante, M. Sonza Reorda
    10th IEEE Latin American Test Workshop (LATW '09)
    DOI: 10.1109/LATW.2009.4813816

  262. Soft Errors in Flash-based FPGAs: Analysis Methodologies and First Results
    N. Battezzati, F. Decuzzi, L. Sterpone, M. Violante
    proceedings of IEEE International Conference on Field Programmable Logic and Applications
    DOI: 10.1109/FPL.2009.5272321

  263. Timing driven placement for fault tolerant circuits implemented on SRAM-based FPGAs
    L. Sterpone
    Lecture Notes in Computer Science (vol 5453)
    DOI: 10.1007/978-3-642-00641-8_11
    ABSTRACT: Electronic systems for safety critical applications such as space and avionics need the maximum level of dependability for guarantee the success of their missions. Contrariwise the computation capabilities required in these fields are constantly increasing for afford the implementation of different kind of applications ranging from the signal processing to the networking. SRAM-based FPGA is the candidate device for achieve this goal thanks to their high versatility of implementing complex circuits with a very short development time. However, in critical environments, the presence of Single Event Upsets (SEUs) affecting the FPGA's functionalities, requires the adoption of specific fault tolerant techniques, like Triple Modular Redundancy (TMR), able to increase the protection capability against radiation effects, but on the other side, introducing a dramatic penalty in terms of performances. In this paper, it is proposed a new timing-driven placement algorithm for implementing soft-errors resilient circuits on SRAM-based FPGAs with a negligible degradation of performance. The algorithm is based on a placement heuristic able to remove the crossing error domains while decreasing the routing congestions and delay inserted by the TMR routing and voting scheme. Experimental analysis performed by timing analysis and SEU static analysis point out a performance improvement of 29% on the average with respect to standard TMR approach and an increased robustness against SEU affecting the FPGA's configuration memory

  264. A Hybrid Approach to the Test of Cache Memory Controllers Embedded in SoCs
    W. Perez, J. Velasco-Medina, D. Ravotto, E. Sanchez, M. Sonza Reorda
    Proceedings of the 2008 14th IEEE International On-Line Testing Symposium

  265. A Novel Design Flow for the Performance Optimization of Fault Tolerant Circuits on SRAM-based FPGAs
    L. Sterpone, N. Battezzati
    NASA/ESA Conference on Adaptive Hardware and Systems, 2008. AHS '08
    DOI: 10.1109/AHS.2008.59

  266. A graph-based representation of Gene Expression profiles in DNA microarrays
    A. Benso, S. Di Carlo, G. Politano, L. Sterpone
    Proceedings of IEEE Symposium on Computational Intelligence in Bioinformatics and Computational Biology (CIBCB) 2008
    DOI: 10.1109/CIBCB.2008.4675762
    KEYWORDS: genetic expression; gene expression; diseases; data structures; data models; dna; classification algorithms; chemical technology; artificial neural networks; bioinformatics
    ABSTRACT: This paper proposes a new and very flexible data model, called gene expression graph (GEG), for genes expression analysis and classification. Three features differentiate GEGs from other available microarray data representation structures: (i) the memory occupation of a GEG is independent of the number of samples used to built it; (ii) a GEG more clearly expresses relationships among expressed and non expressed genes in both healthy and diseased tissues experiments; (iii) GEGs allow to easily implement very efficient classifiers. The paper also presents a simple classifier for sample-based classification to show the flexibility and user-friendliness of the proposed data structure

  267. A new low-cost non intrusive platform for injecting soft errors in SRAM-based FPGAs
    N. Battezzati, L. Sterpone, M. Violante
    ISIE2008
    DOI: 10.1109/ISIE.2008.4677077

  268. A new placement algorithm for the optimization of fault tolerant circuits on reconfigurable devices
    L. Sterpone, N. Battezzati, M. Violante
    DOI: 10.1145/1366224.1366228
    ABSTRACT: Reconfigurable logic devices such as SRAM-based Field Programmable Gate Arrays (FPGAs) are nowadays increasingly popular thanks to their capability of implementing complex circuits with very short development time and for their high versatility in implementing different kind of applications, ranging from signal processing to the networking. The usage of reconfigurable devices in safety critical fields such as space or avionics require the adoption of specific fault tolerant techniques, like Triple Modular Redundancy (TMR), in order to protect their functionality against radiation effects. While these techniques allow to increase the protection capability against radiation effects, they introduce several penalties to the design particularly in terms of performances. In this paper, we present an innovative placement algorithm able to implement fault tolerant circuits on SRAM-based FPGAs while reducing the performance penalties. This algorithm is based on a model-based topology heuristic that address the arithmetic modules implemented on the FPGA reducing the interconnection delays between their resources. Experimental evaluations performed by means of timing analysis and fault injection on two industrial-like case studies demonstrated that the proposed algorithm is able to improve the running frequency up to the 44% versus standard TMR-based techniques while maintaining complete fault tolerance capabilities

  269. A novel SBST generation technique for path-delay faults in microprocessors based on BDD analysis and evolutionary algorithm
    K. Christou, M. Michael, P. Bernardi, M. Grosso, E. Sanchez, M. Sonza Reorda
    26th IEEE VLSI Test Symposium
    DOI: 10.1109/VTS.2008.37

  270. A novel methodology for diversity preservation in evolutionary algorithms
    G. Squillero, A. Tonda
    roceedings of the 2008 GECCO conference companion on Genetic and evolutionary computation
    DOI: 10.1145/1388969.1389049

  271. AN EFFICIENT METHODOLOGY FOR REDUCING SoC TEST DATA VOLUME ON LOW-COST TESTERS
    P. , M. Sonza Reorda

  272. An Anti-Counterfeit Mechanism for the Application Layer in Low-Cost RFID Devices
    P. Bernardi, F. Gandino, F. Lamberti, B. Montrucchio, M. Rebaudengo, E. Sanchez
    Proc. 4th European Conference on Circuits and Systems for Communications

  273. An Automatic Functional Stress Pattern Generation Technique Suitable for SoC Reliability Characterization
    D. Appello, P. Bernardi, M. Bruno, R. Cagliesi, M. Giancarlini, M. Grosso, E. Sanchez, M. Sonza Reorda

  274. An Evolutionary Methodology for Test Generation for Peripheral Cores Via Dynamic FSM Extraction
    D. Ravotto, E. Sanchez, M. Schillaci, G. Squillero
    Lecture Notes in Computer Science (vol 4974)
    DOI: 10.1007/978-3-540-78761-7_22
    ABSTRACT: Traditional test generation methodologies for peripheral cores are performed by a skilled test engineer, leading to long generation times. In this paper a test generation methodology based on an evolutionary tool which exploits high level metrics is presented. To strengthen the correlation between high-level coverage and the gate-level fault coverage, in the case of peripheral cores, the FSMs embedded in the system are identified and then dynamically extracted via simulation, while transition coverage is used as a measure of how much the system is exercised. The results obtained by the evolutionary tool outperform those obtained by a skilled engineer on the same benchmark

  275. An Innovative and Low-Cost Industrial Flow for Reliability Characterization of SoCs
    D. Appello, P. Bernardi, R. Cagliesi, M. Giancarlini, M. Grosso
    13th IEEE European Test Symposium, 2008
    DOI: 10.1109/ETS.2008.27

  276. An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers
    P. Bernardi, M. Sonza Reorda
    DOI: 10.1109/DATE.2008.4484685

  277. Coping with Obsolescence of Processor Cores in Critical Applications
    F. Abate, M. Violante

  278. Differential gene expression graphs: A data structure for classification in DNA microarrays
    A. Benso, S. Di Carlo, G. Politano, L. Sterpone
    Proceedings of IEEE 8th International Conference on BioInformatics and BioEngineering (BIBE) 2008
    DOI: 10.1109/BIBE.2008.4696689
    KEYWORDS: bioinformatics; classification tree analysis; dna; data analysis; data structures; decision trees; feature extraction; gene expression
    ABSTRACT: This paper proposes an innovative data structure to be used as a backbone in designing microarray phenotype sample classifiers. The data structure is based on graphs and it is built from a differential analysis of the expression levels of healthy and diseased tissue samples in a microarray dataset. The proposed data structure is built in such a way that, by construction, it shows a number of properties that are perfectly suited to address several problems like feature extraction, clustering, and classification

  279. Experimental Validation of Lockstep, Checkpoint, and Rollback Recovery to Detect and Correct Soft Errors in System-On-Programmable-Chips
    F. Abate, L. Sterpone, M. Violante

  280. Exploiting MOEA to Automatically Generate Test Programs for Path-delay Faults in Microprocessors
    P. Bernardi, K. Christou, M. Grosso, M. Michael, E. Sanchez, M. Sonza Reorda
    Lecture Notes in Computer Science (vol 4974)
    DOI: 10.1007/978-3-540-78761-7_23
    ABSTRACT: This paper presents an innovative approach for the generation of test programs detecting path-delay faults in microprocessors. The proposed method takes advantage of the multiobjective implementation of a previously devised evolutionary algorithm and exploits both gate- and RT-level descriptions of the processor: the former is used to build Binary Decision Diagrams (BDDs) for deriving fault excitation conditions; the latter is used for the automatic generation of test programs able to excite and propagate fault effects, based on a fast RTL simulation. Experiments on an 8-bit microcontroller show that the proposed method is able to generate suitable test programs more efficiently compared to existing approaches

  281. On Automatic Test Block Generation for Peripheral Testing in SoCs via Dynamic FSMs Extraction
    D. Ravotto, E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero
    DOI: 10.1109/MTV.2007.14

  282. On the Static Cross Section of SRAM-Based FPGAs
    A. Manuzzato, S. Gerardin, A. Paccagnella, L. Sterpone, M. Violante
    DOI: 10.1109/REDW.2008.24

  283. On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications
    L. Sterpone, M. Aguirre, J. Tombs, H. Guzman
    IEEE Design, Automation and Test in Europe

  284. On the evaluation of radiation-induced transient faults in Flash-based FPGAs
    N. Battezzati, S. Gerardin, A. Manuzzato, A. Paccagnella, S. Rezgui, L. Sterpone, M. Violante
    14th IEEE International On-Line Testing Symposium
    DOI: 10.1109/IOLTS.2008.47

  285. On the generation of test programs for chip multithread computer architectures
    D. Ravotto, E. Sanchez, M. Sonza Reorda, G. Squillero
    IEEE International Test Conference (ITC)
    DOI: 10.1109/TEST.2008.4700678

  286. RFID for agri-food traceability: methods for authentication, integrity and privacy
    C. Demartini, F. Gandino, B. Montrucchio, M. Rebaudengo, E. Sanchez

  287. Robustness analysis of soft error accumulation in SRAM-FPGAs using FLIPPER and STAR/RoRA
    M. Alderighi, F. Casini, S. D'Angelo, M. Mancini, D. Merodio Codinachs, S. Pastore, G. Sorrenti, L. Sterpone, R. Weigand, M. Violante
    DOI: 10.1109/RADECS.2008.5782703

  288. SoC Symbolic Simulation: a case study on delay fault testing
    Bosio, A, P. Girard, S. Pravossoudovich, P. Bernardi
    DOI: 10.1109/DDECS.2008.4538810

  289. Software-Based Self-Test Strategy for Data Cache Memories Embedded in SoCs
    W. Perez, J. Velasco Medina, D. Ravotto, E. Sanchez, M. Sonza Reorda

  290. A Hybrid Approach to Fault Detection and Correction in SoCs
    P. Bernardi, L. Bolzani, M. Sonza Reorda

  291. A Software-based Methodology for the Generation of Peripheral Test Sets Based on High-level Descriptions
    L. Bolzani, E. Sanchez, M. Sonza Reorda
    Proceedings of the 20th annual conference on Integrated circuits and systems design

  292. A local analysis of an incremental evolutionary tool for processor diagnosis
    D. Ravotto, E. Sanchez, M. Schillaci, G. Squillero
    DOI: 10.1109/CEC.2007.4424921
    ABSTRACT: This paper details an evolutionary tool targeted at increasing the diagnostic power of a set of assembly programs. The underlying evolutionary scheme is quite peculiar in some aspect and present interesting characteristics The effectiveness of the generated set has recently been demonstrated. Here the use of the tool is further motivated through a deep experimental analysis that provides insight on the obtainable results and better explains the design choices. The use of the tool is validated against a widely used microprocessor core and results are provided

  293. A new FPGA-based edge detection system for the gridding of DNA microarray images
    L. Sterpone, M. Violante

  294. A new decompression system for the configuration process of SRAM-based FPGAs
    L. Sterpone, M. Violante

  295. A new hardware architecture for performing the gridding of DNA microarray images
    L. Sterpone, M. Violante

  296. A new hardware/software platform for the soft-error sensitivity evaluation of FPGA devices
    M. Violante, M. Sonza Reorda, L. Sterpone, A. Manuzzato, S. Gerardin, P. Rech, M. Bagatin, A. Paccagnella, C. Andreani, G. Gorini, A. Pietropaolo, G. Cardarilli, A. Salsano, S. Pontarelli, C. Frost

  297. A new mitigation approach for soft errors in embedded processors
    F. Abate, L. Sterpone, M. Violante
    DOI: 10.1109/RADECS.2007.5205504

  298. Agri-Food Traceability Management using a RFID System with Privacy Protection
    P. Bernardi, C. Demartini, F. Gandino, B. Montrucchio, M. Rebaudengo, Sanchez E.R
    DOI: 10.1109/AINA.2007.29
    ABSTRACT: In this paper an agri-food traceability system based on public key cryptography and Radio Frequency Identification (RFID) technology is proposed. In order to guarantee safety in food, an efficient tracking and tracing system is required. RFID devices allow recording all useful information for traceability directly on the commodity. The security issues are discussed and two different methods based on public cryptography are proposed and evaluated. The first algorithm uses a nested RSA based structure to improve security, while the second also provides authenticity of data. An experimental analysis demonstrated that the proposed system is well suitable on PDAs too

  299. An Analysis of SEU Effects in Embedded Operating Systems for Real-Time Applications
    L. Sterpone, M. Violante
    International Symposium on Industrial Electronics
    DOI: 10.1109/ISIE.2007.4375152

  300. An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores
    L. Bolzani, E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero
    DOI: 10.1109/IOLTS.2007.14

  301. An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains
    J. Lagos-Benites, D. Appello, P. Bernardi, M. Grosso, D. Ravotto, E. Sanchez, M. Sonza Reorda

  302. An Enhanced Technique for the Automatic Generation of Effective Diagnosis-oriented Test Programs for Processors
    E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero
    DOI: 10.1109/DATE.2007.364451

  303. An Extensible Evolutionary-based General-purpose Optimizer
    E. Sanchez, M. Schillaci, G. Squillero

  304. An experimental analysis of SEU sensitiveness of recursive-oriented hardening techniques
    L. Sterpone, P. Reyes Moreno, J. Maestro, O. Ruano, P. Reviriego

  305. An optimized hybrid approach to provide fault detection and correction in SoCs
    L. Bolzani, P. Bernardi, M. Sonza Reorda

  306. Analysis of an RFID-based Information System for Tracking and Tracing in an Agri-Food chain
    F. Gandino, B. Montrucchio, M. Rebaudengo, E. Sanchez Sanchez
    IEEE RFID Eurasia Conference

  307. Analytical analysis of the MCUs sensitiveness of TMR architectures in SRAM-based FPGAs
    L. Sterpone, M. Violante
    DOI: 10.1109/RADECS.2007.5205501

  308. Automotive Microcontroller End-of-Line Test via Software-Based Methodologies
    W. Di Palma, D. Ravotto, E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero
    Eighth International Workshop on Microprocessor Test and Verification, 2007. MTV '07
    DOI: 10.1109/MTV.2007.15

  309. Co-evolution of Test Programs and Stimuli Vectors for Testing of Embedded Peripheral Cores
    L. Bolzani, E. Sanchez, M. Schillaci, G. Squillero

  310. Coupling EA and High-Level Metrics for the Automatic Generation of Test Blocks for Peripheral Cores
    L. Bolzani, E. Sanchez, M. Schillaci, G. Squillero
    GECCO'07
    DOI: 10.1145/1276958.1277342

  311. Design of an UHF RFID Transponder for Secure Authentication
    P. Bernardi, F. Gandino, B. Montrucchio, M. Rebaudengo, Sanchez E.R
    ABSTRACT: RFID technology increases rapidly its applicability in new areas of interest without guaranteeing security and privacy issues. This paper presents a new architecture of an RFID transponder with cryptographic capabilities. Other than being compatible with the EPC Class-1 Gen-2 communication protocol, our tag implements an asymmetric ciphering module that proved useful in authentication and anti-counterfeit schemes, particularly critical in many application fields. Experimental results concerning area requirements and power consumption indicate its feasibility

  312. Effectiveness of TMR-based techniques to mitigate alpha-induced SEU accumulation in commercial SRAM-based FPGAs
    A. Manuzzato, S. Gerardin, A. Paccagnella, L. Sterpone, M. Violante
    DOI: 10.1109/RADECS.2007.5205499

  313. Extended Fault Detection Techniques for Systems-on-Chip
    P. Bernardi, L. Bolzani, M. Sonza Reorda

  314. Hardware-Accelerated Path-Delay Fault Grading of Functional Test Programs for Processor-based Systems
    P. Bernardi, M. Grosso, M. Sonza Reorda
    Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI
    DOI: 10.1145/1228784.1228881

  315. Increasing Effective Radiated Power in Wireless Sensor Networks with Channel Coding Techniques
    Sanchez E.R, F. Gandino, B. Montrucchio, M. Rebaudengo
    IEEE International Conference on Electromagnetics in Advanced Applications, ICEAA '07
    DOI: 10.1109/ICEAA.2007.4387323
    ABSTRACT: In this paper we analyzed classical forward error correction (FEC) algorithms implemented in wireless sensor networks (WSNs). We adopted FEC algorithms in sensor network nodes and evaluated performance and cost related to their covered area. Experimental results show how FEC adoption increases bit error tolerance in additive white Gaussian noise channels while rising computational costs in an acceptable fashion; coding gains reach values higher than 1 dB with a time latency that is negligible when compared with WSN data rates

  316. On Test Program Generation for Peripheral Components in a SoC Resorting to High-Level Metrics
    L. Bolzani, E. Sanchez, M. Sonza Reorda

  317. On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores
    P. Bernardi, M. Grosso, E. Sanchez, M. Sonza Reorda
    European Test Symposium, 2007. ETS '07. 12th IEEE
    DOI: 10.1109/ETS.2007.28

  318. Optimization of Self Checking FIR filters by means of Fault Injection Analysis
    S. Pontarelli, L. Sterpone, G. Cardarilli, M. Re, M. Sonza Reorda, A. Salsano, M. Violante
    22th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

  319. Safety Evaluation of NanoFabrics
    M. Grosso, M. Rebaudengo, M. Sonza Reorda
    22th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2007

  320. Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders
    S. Pontarelli, L. Sterpone, G. Cardarilli, M. Re, M. Sonza Reorda, A. Salsano, M. Violante

  321. Sensitivity evaluation of TMR-hardened circuits to multiple SEUs induced by alpha particles in commercial SRAM-based FPGAs
    A. Manuzzato, P. Rech, S. Gerardin, A. Paccagnella, L. Sterpone, M. Violante
    International Symposium on Defect and Fault Tolerance in VLSI Systems

  322. Soft errors in SRAM-FPGAs: A comparison of two complementary approaches
    M. Alderighi, F. Casini, S. D'Angelo, M. Mancini, S. Pastore, L. Sterpone, M. Violante
    DOI: 10.1109/RADECS.2007.5205521

  323. Static and Dynamic Analysis of SEU effects in SRAM-based FPGAs
    L. Sterpone, M. Violante

  324. Validating the Dependability of Embedded Systems through Fault Injection by Means of Loadable Kernel Modules
    M. Murciano, M. Violante
    Proceedings of the 2007 IEEE International High Level Design Validation and Test Workshop

  325. µGP an evolutionary test program generator
    G. Squillero, M. Schillaci, E. Sanchez

  326. A Fault Injection Environment for SoPC's Embedded Microprocessors
    M. Portela-Garcia, L. Sterpone, C. Lopez-Ongil, M. Sonza Reorda, M. Violante

  327. A new approach to compress the configuration information of programmable devices
    M. Martina, G. Masera, A. Molino, F. Vacca, L. Sterpone, M. Violante
    DOI: 10.1109/DATE.2006.243747

  328. A new approach to cope with single event upsets in processor-based systems
    M. Schillaci, M. Sonza Reorda, M. Violante

  329. A pattern ordering algorithm for reducing the size of fault dictionaries
    P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda
    VLSI Test Symposium, 2006. Proceedings. 24th IEEE
    DOI: 10.1109/VTS.2006.9

  330. A survey of µGP
    E. Sanchez, M. Schillaci
    SIGEvolution, newsletter of the ACM Special Interest Group on Genetic and Evolutionary Computation

  331. An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs
    P. Bernardi, E. Sanchez, M. Schillaci, G. Squillero, M. Sonza Reorda
    DOI: 10.1109/DATE.2006.243795

  332. An Evolutionary Methodology to Enhance Processor Software-Based Diagnosis
    P. Bernardi, E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero

  333. An Experimental Analysis of a New Mixed Grain-Based Dynamically Reconfigurable Architecture
    L. Sterpone

  334. Anatomy of an extensible evolutionary tool
    E. Sanchez, M. Schillaci, G. Squillero

  335. Combined software and hardware techniques for the design of reliable IP processors
    M. Rebaudengo, L. Sterpone, M. Violante, C. Bolchini, A. Miele, D. Sciuto
    DOI: 10.1109/DFT.2006.18

  336. Dependability Evaluation of Transient Fault Effects in Reconfigurable Compute Fabric Devices
    L. Sterpone, M. Violante
    International On-Line Testing Symposium
    DOI: 10.1109/IOLTS.2006.20

  337. Embedded Memory Diagnosis: An Industrial Workflow
    D. Appello, P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda, V. Tancorre
    IEEE International Test Conference
    DOI: 10.1109/TEST.2006.297672

  338. Enhanced Test Program Compaction Using Genetic Programming
    E. Sanchez, M. Schillaci, G. Squillero

  339. Evolving Warriors for the Nano Core
    E. Sanchez, M. Schillaci, G. Squillero

  340. Fault Injection-based Reliability Evaluation of SoPCs
    M. Sonza Reorda, L. Sterpone, M. Violante, M. Portela-Garcia, C. Lopez-Ongil, L. Entrena
    DOI: 10.1109/ETS.2006.24

  341. Hardware-in-the-Loop-Based Dependability Analysis of Automotive Systems
    M. Sonza Reorda, M. Violante
    International On-Line Testing SYmposium
    DOI: 10.1109/IOLTS.2006.41

  342. Laboratorios en casa: Una Nueva Alternativa Para Cursos Masivos de Diseño Lógico Digital
    J. Oliver, F. Haim, S. Fernández, J. Rodríguez, L. Ciganda, Rolando, P.
    KEYWORDS: diseño digital; laboratorios; educación; kits

  343. Laboratory at Home: Actual Circuit Design and Testing Experiences in Massive Digital Design Courses
    F. Haim, S. Fernández, J. Rodríguez, L. Ciganda, P. Rolando, J. Oliver
    KEYWORDS: digital design; laboratory; electronics

  344. On the automation of the test flow of complex SoCs
    D. Appello, P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda, V. Tancorre
    VLSI Test Symposium, 2006. Proceedings. 24th IEEE
    DOI: 10.1109/VTS.2006.51

  345. Online hardening of programs against SEUs and SETs
    Lisboa C.A.L, L. Carro, Reorda M.S, M. Violante
    DOI: 10.1109/DFT.2006.49

  346. ReCoM: A new Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications
    L. Sterpone, M. Violante
    DOI: 10.1109/DDECS.2006.1649570

  347. Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications
    P. Bernardi, L. Bolzani, M. Violante, M. Sonza Reorda, A. Manzone, M. Ossela
    DOI: 10.1109/MTV.2006.19

  348. Test Considerations about the Structured ASIC Paradigm
    P. Bernardi, M. Grosso
    Design and Diagnostics of Electronic Circuits and systems, 2006 IEEE

  349. A Tool for Supporting and Automating the Test of Complex System-on-Chips
    P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda, D. Appello, R. Mattiuzzo, V. Tancorre

  350. A design flow for protecting FPGA-based systems against single event upsets
    L. Sterpone, M. Violante
    DOI: 10.1109/DFTVS.2005.5

  351. A modular Architecture for a Populationless Evolutionary Algorithm for MIP
    E. Sanchez, M. Schillaci, G. Squillero

  352. A new DFM-proactive technique
    D. Appello, P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda, V. Tancorre

  353. An I-IP for the Debug of Microprocessor Cores
    D. Appello, M. Grosso, M. Rebaudengo, M. Sonza Reorda

  354. An experimental analysis of hardening techniques for SRAM-based FPGAs
    L. Sterpone, S. Rezgui, M. Violante
    DOI: 10.1109/RADECS.2005.4365639

  355. An experimental analysis of hardening techniques for SRAM-based FPGAs
    L. Sterpone, M. Violante, S. Rezgui
    8th IEEE European Conference on Radiation and Its Effects on Component and Systems

  356. An integrated approach for increasing the soft-error detection capabilities in SoCs processors
    P. Bernardi, L. Bolzani, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DOI: 10.1109/DFTVS.2005.17

  357. Automatic Completion and Refinement of Verification Sets for Microprocessor Cores
    E. Sanchez, G. Squillero, M. Sonza Reorda
    LECTURE NOTES IN COMPUTER SCIENCE
    DOI: 10.110.1007/978-3-540-32003-6_21007/b106856
    ABSTRACT: In the design cycle of a microprocessor core, the unit is usually refined through a series of subsequent steps. To deliver a flaw free unit at the end of the process, in each stage a verification step is required. While it would be useful to automatically develop the set of test programs for verification concurrently to the design, in most of the existing approach verification is performed manually and starting from scratch. This paper presented a methodology for the automatic completion and refinement of existing verification programs. It shows a new technique for allowing a Genetic Programming-based framework to import an existing test-program set and assimilate it for further test generation. A case study is considered, in which a sample pipelined processor is used, and new test programs are generated starting from existing functional ones. Different metrics are targeted, and preliminary results are reported, showing the effectiveness of the method with respect to a pure random approach

  358. Automatic Generation of Test Sets for SBST of Microprocessor IP Cores
    E. Sanchez, M. Sonza Reorda, G. Squillero, M. Violante
    DOI: 10.1145/1081081.1081105

  359. Automatic completion and refinement of verification sets for microprocessor cores
    E. Sánchez, M. Sonza Reorda, G. Squillero
    DOI: 10.1007/978-3-540-32003-6_21

  360. Diagnosing faulty functional units in processors by using automatically generated test sets
    P. Bernardi, E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero
    DOI: 10.1109/MTV.2005.10
    ABSTRACT: Microprocessor technology is increasingly used for many applications; the large market volumes call for cost containment in the production phase. Process yield for processor production is, however, far from ideal. To increase it fault diagnosis is an important means, since it can allow both process characterization and product repair by the usage of backup resources. This paper presents a novel methodology to discriminate faulty modules, rather than gates, in a microprocessor based on the automatic construction of diagnostic software-based test sets. The approach exploits a post-production test set, designed for software-based self-test, and an infrastructure IP to perform the diagnosis. An initial diagnostic test set is built, and then iteratively refined resorting to an evolutionary method. Experimental results are reported in the paper showing the feasibility and effectiveness of the approach for an Intel i8051 processor core

  361. Efficient estimation of SEU effects in SRAM-based FPGAs
    M. Sonza Reorda, L. Sterpone, M. Violante
    DOI: 10.1109/IOLTS.2005.26

  362. Exploiting an I-IP for both test and silicon debug of microprocessor cores
    P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda
    Microprocessor Test and Verification, 2005. MTV '05. Sixth International Workshop on
    DOI: 10.1109/MTV.2005.11

  363. Exploiting an Infrastructure-IP to reduce memory diagnosis costs in SoCs
    P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda
    Test Symposium, 2005. European
    DOI: 10.1109/ETS.2005.23

  364. Improved Software-Based Processor Control-Flow Errors Detection Technique
    O. Goloubeva, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DOI: 10.1109/RAMS.2005.1408426

  365. Integrating BIST techniques for on-line SoC testing
    P. Bernardi, M. Grosso, A. Manzone, M. Rebaudengo, E. Sanchez, M. Sonza Reorda
    On-Line Testing Symposium, 2005. IOLTS 2005. 11th IEEE International
    DOI: 10.1109/IOLTS.2005.38

  366. Multiple errors produced by single upsets in FPGA configuration memory: a possible solution
    M. Sonza Reorda, L. Sterpone, M. Violante
    DOI: 10.1109/ETS.2005.29

  367. New Evolutionary Techniques for Test-Program Generation for Complex Microprocessor Cores
    E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero, L. Sterpone, M. Violante
    Proceedings of the 2005 conference on Genetic and evolutionary computation
    DOI: 10.1145/1068009.1068370

  368. On the diagnosis of SoCs including multiple memory cores
    P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda
    Design and Diagnostics of Electronic Circuits and Systems. IEEE Workshop on
    DOI: 10.1109/DDECS.2006.1649622

  369. On the optimal design of triple modular redundancy logic for SRAM-based FPGAs
    F. Kastensmidt, L. Sterpone, M. Sonza Reorda, L. Carro
    DOI: 10.1109/DATE.2005.229

  370. On the transformation of manufacturing test sets into on-line test sets for microprocessors
    E. Sanchez, Reorda M.S, G. Squillero
    roceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)
    DOI: 10.1109/DFTVS.2005.53

  371. On-line Detection of Control-Flow Errors in SoCs by means of an Infrastructure IP core
    P. Bernardi, L. Bolzani, M. Rebaudengo, M. Sonza Reorda, F. Vargas, M. Violante
    DOI: 10.1109/DSN.2005.74

  372. Pandora I-IP: an HW/SW approach to Control Flow Checking
    P. Bernardi, L. Bolzani, M. Rebaudengo, M. Sonza Reorda, F. Vargas, M. Violante

  373. RoRA: a reliability-oriented place and route algorithm for SRAM-based FPGAs
    L. Sterpone, M. Sonza Reorda, M. Violante
    Research in Microelectronics and Electronics
    DOI: 10.1109/RME.2005.1543031

  374. Testing logic cores using a BIST P1500 compliant approach: a case of study
    P. Bernardi, G. Masera, F. Quaglio, M. Sonza Reorda
    Proceedings of DATE2005
    DOI: 10.1109/DATE.2005.305

  375. A Local Analysis of the Genotype-Fitness Mapping in Hardware Optimization Problems
    E. Sanchez, G. Squillero, M. Violante
    DOI: 10.1109/CEC.2004.1330952

  376. A multi-level approach to the dependability analysis of CAN networks for automotive applications
    F. Corno, J. Perez, M. Ramasso, M. Sonza Reorda, M. Violante

  377. A multi-level approach to the dependability analysis of networked systems based on the CAN protocol
    F. Corno, J. Perez, M. Sonza Reorda, M. Violante

  378. An Infrastructure IP for Soft Error Detection
    L. Bolzani, M. Rebaudengo, M. Sonza Reorda, F. Vargas, M. Violante

  379. Approaching production diagnostic for BIST-based testing
    D. Appello, P. Bernardi, D. Chindamo, M. Rebaudengo, M. Sonza Reorda, V. Tancorre

  380. Automatic Generation of Validation Stimuli for Application-Specific Processors
    O. Goloubeva, M. Sonza Reorda, M. Violante
    DOI: 10.1109/DATE.2004.1268847

  381. Automatic Test Programs Generation Driven by Internal Performance Counters
    W. Lindsay, E. Sanchez, M. Sonza Reorda, G. Squillero
    Proceedings of the Fifth International Workshop on Microprocessor Test and Verification
    DOI: 10.1109/MTV.2004.5

  382. Automatic Verification of RT-Level Microprocessor Cores Using Behavioral Specifications: a Case Study
    L. Anghel, E. Sanchez, M. Sonza Reorda, G. Squillero, R. Velazco

  383. Automatic generation of validation stimuli for application-specific processors
    O. Goloubeva, M. Sonza Reorda, M. Violante
    DOI: 10.1109/DATE.2004.1268847

  384. Cerberus I-IP: an HW/SW approach to Control Flow Checking
    P. Bernardi, L. Bolzani, M. Rebaudengo, M. Sonza Reorda, F. Vargas, M. Violante

  385. Coupling different methodologies to validate obsolete microprocessors
    L. Anghel, E. Sanchez, M. Sonza Reorda, G. Squillero, R. Velazco
    Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium on (DFT'04)
    DOI: 10.1109/DFTVS.2004.1347846

  386. Dynamic Optimization of Semantic Annotation Relevance
    D. Bonino, F. Corno, G. Squillero
    Proceedings of CEC2004, Congress on Evolutionary Computation

  387. Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA
    M. Bellato, P. Bernardi, D. Bortolato, A. Candelori, M. Ceschia, A. Paccagnella, M. Rebaudengo, M. Sonza Reorda, M. Violante, P. Zambolin
    DOI: 10.1109/DATE.2004.1268908

  388. Evaluating the effects of transient faults on vehicle dynamic performance in automotive systems
    F. Corno, F. Esposito, M. Sonza Reorda, S. Tosato

  389. Exploiting HW Acceleration for Classifying Complex Test Program Generation Problems
    E. Sanchez, G. Squillero, M. Violante
    Lecture Notes in Computer Science (vol 3005)
    DOI: 10.1007/978-3-540-24653-4_24

  390. Exploiting an I-IP for In-field SOC test
    P. Bernardi, M. Rebaudengo, M. Sonza Reorda
    DOI: 10.1109/DFTVS.2004.1347865

  391. Hybrid Soft Error Detection by means of Infrastructure IP cores
    L. Bolzani, M. Rebaudengo, M. Sonza Reorda, F. Vargas, M. Violante

  392. On the diagnosis of embedded memory cores through Programmable BIST
    D. Appello, P. Bernardi, M. Rebaudengo, M. Sonza Reorda, V. Tancorre

  393. On the evaluation of SEU sensitiveness in SRAM-based FPGAs
    P. Bernardi, M. Sonza Reorda, L. Sterpone, M. Violante

  394. On the evolution of corewar warriors
    F. Corno, E. Sanchez, G. Squillero
    DOI: 10.1109/CEC.2004.1330848

  395. On-line Analysis and Perturbation of CAN Networks
    M. Sonza Reorda, M. Violante
    DOI: 10.1109/DFTVS.2004.1347867

  396. Using Infrastructure IPs to support SW-based Self-Test of Processor Cores
    P. Bernardi, M. Rebaudengo, M. Sonza Reorda

  397. Validation of the dependability of CAN-based networked systems
    F. Corno, J. Perez, M. Ramasso, M. Sonza Reorda, M. Violante
    DOI: 10.1109/HLDVT.2004.1431262

  398. A P1500-compatible programmable BIST approach for the test of embedded flash memories
    P. Bernardi, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DOI: 10.1109/DATE.2003.1253692
    ABSTRACT: In this paper we present a microprocessor-based approach suitable for embedded flash memory testing in a System-on-a-chip (SoC) environment. The main novelty of the approach is the high flexibility, which guarantees easy exploitation of the same architecture to different memory cores. The proposed approach is compatible with the P1500 standard. A case study has been developed and demonstrates the advantages of the proposed core test strategy in terms of area overhead and test application time

  399. A new Software-based technique for low-cost Fault-Tolerant application
    M. Rebaudengo, M. Sonza Reorda, M. Violante

  400. A programmable BIST approach for the diagnosis of embedded memory cores
    D. Appello, P. Bernardi, A. Fudoli, M. Rebaudengo, M. Sonza Reorda, V. Tancorre, M. Violante

  401. A real-time evolutionary algorithm for Web prediction
    D. Bonino, F. Corno, G. Squillero
    Proceedings of the IEEE/WIC International Conference on Web Intelligence

  402. Accurate Dependability Analysis of CAN-based Networked Systems
    J. Perez, M. Sonza Reorda, M. Violante

  403. Accurate and Efficient Analysis of Single Event Transients in VLSI Circuits
    M. Violante, M. Sonza Reorda

  404. Accurate and efficient analysis of single event transients in VLSI circuits
    V. Sonza Reoda M
    DOI: 10.1109/OLT.2003.1214374

  405. An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor
    M. Rebaudengo, M. Sonza Reorda, M. Violante

  406. An Enhanced Framework for Microprocessor Test-Program Generation
    F. Corno, G. Squillero
    Lecture Notes in Computer Science (vol 2610)
    DOI: 10.1007/3-540-36599-0_28
    ABSTRACT: Test programs are fragment of code, but, unlike ordinary application programs, they are not intended to solve a problem, nor to calculate a function. Instead, they are supposed to give information about the machine that actually executes them. Today, the need for effective test programs is increasing, and, due to the inexorable increase in the number of transistor that can be integrated onto a single silicon die, devising effective test programs is getting more problematical. This paper presents µGP, an efficient and versatile approach to testprogram generation based on an evolutionary algorithm. The proposed methodology is highly versatile and improves previous approaches, allowing the testprogram generator generating complex assembly programs that include subroutines calls

  407. An Evolutionary Approach to Web Request Prediction
    D. Bonino, F. Corno, G. Squillero

  408. An RT-level concurrent error detection technique for data dominated systems
    O. Golubeva, M. Sonza Reorda, M. Violante
    DOI: 10.1109/OLT.2003.1214385

  409. An RT-level concurrent error detection technique for data dominated systems
    O. Goubeva, M. Sonza Reorda, M. Violante
    DOI: 10.1109/OLT.2003.1214385

  410. An efficient algorithm for the extraction of compressed diagnostic information from embedded memory cores
    P. Bernardi, M. Rebaudengo, M. Sonza Reorda

  411. Analyzing SEU Effects in SRAM-based FPGAs
    M. Violante, M. Ceschia, M. Sonza Reorda, A. Paccagnella, P. Bernardi, M. Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, A. Candelori
    DOI: 10.1109/OLT.2003.1214377

  412. Automatic Test Program Generation for Pipelined Processors
    F. Corno, M. Sonza Reorda, G. Squillero
    Proceedings of the 2003 ACM symposium on Applied computing
    DOI: 10.1145/952532.952676

  413. Code generation for functional validation of pipelined microprocessors
    F. Corno, G. Squillero, M. Sonza Reorda
    Proceedings of the 8th IEEE European Test Workshop

  414. Dependability Analysis of CAN Networks: an emulation-based approach
    J. Perez, M. Sonza Reorda, M. Violante

  415. Detailed comparison of dependability analyses performed at RT and gate levels
    A. Ammari, R. Leveugle, M. Sonza Reorda, M. Violante

  416. Dynamic Prediction of Web Requests
    F. Corno, D. Bonino, G. Squillero
    CEC03: 2003 IEEE Congress on Evolutionary Computation

  417. Emulation-based Analysis of Soft Errors in Deep Sub-micron Circuits
    M. Sonza Reorda, M. Violante
    DOI: 10.1007/b12007

  418. Exploiting Auto-Adaptive microGP for Highly Effective Test Programs Generation
    F. Corno, G. Squillero
    Lecture Notes in Computer Science (vol 2606)
    DOI: 10.1007/3-540-36553-2_24

  419. Exploiting co-evolution and a modified island model to climb the Core War hill
    F. Corno, E. Sanchez, G. Squillero
    DOI: 10.1109/CEC.2003.1299947

  420. Exploiting programmable BIST for the diagnosis of embedded memory cores
    D. Appello, P. Bernardi, A. Fudoli, M. Rebaudengo, M. Sonza Reorda, V. Tancorre, M. Violante
    DOI: 10.1109/TEST.2003.1270861

  421. Fully automatic test program generation for microprocessor cores
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

  422. High-level test generation for hardware testing and software validation
    O. Goloubeva, M. Sonza Reorda, M. Violante
    DOI: 10.1109/HLDVT.2003.1252488

  423. Soft-error Detection Using Control Flow Assertions
    O. Goloubeva, M. Rebaudengo, M. Sonza Reorda, M. Violante

  424. Soft-error detection using control flow assertions
    O. Goloubeva, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DOI: 10.1109/DFTVS.2003.1250158

  425. A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques
    D. Appello, A. Fudoli, V. Tancorre, F. Corno, M. Rebaudengo, M. Sonza Reorda

  426. A Hierarchical Approach for Designing Dependable Systems
    M. Sonza Reorda, M. Violante, N. Mazzocca, S. Venticinque, A. Bobbio, G. Franceschinis

  427. A New Methodology for Debugging Embedded Cores
    D. Appello, L. Bouzaida, A. Fudoli, R. Mattiuzzo, R. Kapur, M. Rebaudengo, M. Sonza Reorda

  428. A Software Fault Tolerance Method for Safety-Critical Systems: Effectiveness and Drawbacks
    B. Nicolescu, R. Velazco, M. Sonza Reorda, M. Rebaudengo, M. Violante

  429. A Transparent Search Agent for Closed Collections
    F. Bota, F. Corno, L. Farinetti, G. Squillero

  430. A new approach to software-implemented fault tolerance
    M. Rebaudengo, M. Sonza Reorda, M. Violante

  431. A new functional fault model for FPGA Application-Oriented testing
    M. Rebaudengo, M. Sonza Reorda, M. Violante

  432. A simplified gate-level fault model for crosstalk effects analysis
    P. Civera, L. Macchiarulo, M. Violante
    Proceedings. 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002
    DOI: 10.1109/DFTVS.2002.1173499

  433. An Evolutionary Algorithm for Reducing Integrated-Circuit Test Application Time
    F. Corno, M. Sonza Reorda, G. Squillero
    Proceedings of the 2002 ACM symposium on Applied computing
    DOI: 10.1145/508791.508908

  434. An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation
    L. Berrojo, F. Corno, L. Entrena, I. Gonzlez, C. Lopez, M. Sonza Reorda, G. Squillero

  435. Analysis of SEU effects in a pipelined processor
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    DOI: 10.1109/OLT.2002.1030193
    ABSTRACT: Modern processors embed features such as pipelined execution units and cache memories that can hardly be controlled by programmers through the processor instruction set. As a result, software-based fault injection approaches are no longer suitable for assessing the effects of SEUs in modern processors, since they are not able to evaluate the effects of SEUs affecting pipelines and caches. In this paper we report an analysis of a commercial processor core where the effects of SEUs located in the processor pipeline and cache memories are studied. Moreover the obtained results are compared with those software-based approaches provide. Experimental results show that software-based approaches may lead to errors during the failure rate estimation of up to 400%

  436. Analysis of the Equivalences and Dominances of Transient Faults at the Register-Transfer Level
    L. Errojo, I. Gonzlez, F. Corno, M. Sonza Reorda, G. Squillero, L. Entrena, C. Lopez
    Proceedings of the Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02)

  437. Automatic Test Program Generation from RT-level MicroprocessorDescriptions
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero

  438. Efficient Machine-Code Test-Program Induction
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero

  439. Evolutionary Techniques for Minimizing Test Signals Application Time
    F. Corno, M. Sonza Reorda, G. Squillero
    Lecture Notes in Computer Science (vol 2279)
    DOI: 10.1007/3-540-46004-7_19
    ABSTRACT: Reducing production-test application time is a key problem for modern industries. Several different hardware solutions have been proposed in the literature to ease such process. However, each hardware architecture must be coupled with an effective test signals generation algorithm. This paper propose an evolutionary approach for minimizing the application time of a test set by opportunely extending it and exploiting a new hardware architecture, named interleaved scan. The peculiarities of the problem suggest the use of a slightly modified genetic algorithm with concurrent populations. Experimental results show the effectiveness of the approach against the traditional ones

  440. Evolutionary Test Program Induction for Microprocessor Design Verification
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    Proceedings of the 11th Asian Test Symposium

  441. Fault list compaction through static timing analysis for efficient fault injection experiments
    V. Sonza Reorda M.
    DOI: 10.1109/DFTVS.2002.1173523

  442. High-level and hierarchical test sequence generation
    G. Jervan, Z. Peng, O. Goloubeva, M. Sonza Reorda, M. Violante
    DOI: 10.1109/HLDVT.2002.1224448

  443. New Techniques for Speeding-up Fault-injection Campaigns
    L. Berrojo, I. Gonzlez, F. Corno, M. Sonza Reorda, G. Squillero, L. Entrena, C. Lopez
    Proceedings of the conference on Design, automation and test in Europe

  444. Reducing Test Application Time through Interleaved Scan
    F. Corno, M. Sonza Reorda, G. Squillero
    Proceedings of the 15th symposium on Integrated circuits and systems design

  445. Simulation-based analysis of SEU effects on SRAM-based FPGAs
    M. Rebaudengo, M. Sonza Reorda, M. Violante

  446. Simulation-based analysis of SEU effects on SRAM-based FPGAs
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    Lecture Notes in Computer Science (vol 2438)
    DOI: 10.1007/3-540-46117-5_63

  447. A P1500 compliant BIST-based approach to embedded RAM diagnosis
    D. Appello, F. Corno, M. Giovinetto, M. Rebaudengo, M. Sonza Reorda

  448. A genetic algorithm for the computation of initialization sequences for synchronous sequential circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, G. Squillero
    10th anniversary compendium of papers from Asian Test Symposium : proceedings : 1992-2001
    DOI: 10.1109/ATS.2001.10066
    ABSTRACT: [Riedizione] Testing circuits which do not include a global reset signal requires either complex ATPG algorithms based on 9- or even 256-valued algebras, or some suitable method to generate initialization sequences. This paper follows the latter approach, and presents a new method to the automated generation of an initialization sequence for synchronous sequential circuits. We propose a Genetic Algorithm providing a sequence that aims at initializing the highest number of flip flops with the lowest number of vectors. The experimental results show that the approach is feasible to be applied even to the largest benchmark circuits and that it compares well to other known approaches in terms of initialized flip flops and sequence length. Finally, this paper shows how the initialization sequences can be fruitfully exploited by simplifying the ATPG process

  449. A source-to-source compiler for generating dependable software
    M. Rebaudengo, M. Sonza Reorda, M. Torchiano, M. Violante
    Proc. First IEEE International Workshop on Source Code Analysis and Manipulation, SCAM
    DOI: 10.1109/SCAM.2001.972664
    ABSTRACT: Over the last years, an increasing number of safety-critical tasks have been demanded for computer systems. In particular, safety-critical computer-based applications are hitting market areas where cost is a major issue, and thus solutions are required which conjugate fault tolerance with low costs. A source-to-source compiler supporting a software-implemented hardware fault tolerance approach is proposed, based on a set of source code transformation rules. The proposed approach hardens a program against transient memory errors by introducing software redundancy: every computation is performed twice and results are compared, and control flow invariants are checked explicitly. By exploiting the tool's capabilities, several benchmark applications have been hardened against transient errors. Fault injection campaigns have been performed to evaluate the fault detection capability of the hardened applications. In addition, we analyzed the proposed approach in terms of space and time overheads

  450. ARPIA: a High-Level Evolutionary Test Signal Generator
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    Applications of Evolutionary Computing
    DOI: 10.1007/3-540-45365-2_31
    ABSTRACT: The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective fault models and test signals generators are still missing. This paper proposes ARPIA, a new simulation-based evolutionary test generator. ARPIA adopts an innovative high-level fault model that enables efficient fault simulation and guarantees good correlation with gate-level results. The approach exploits an evolutionary algorithm to drive the search of effective patterns within the gigantic space of all possible signal sequences. ARPIA operates on register-transfer level VHDL descriptions and generates effective test patterns. Experimental results show that the achieved results are comparable or better than those obtained by high-level similar approaches or even by gate-level ones

  451. An Interpretation Framework for Evaluating High-Level Fault Models and ATPG Capabilities
    F. Corno, M. Sonza Reorda, G. Squillero

  452. Coping with SEUs/SETs in microprocessors by means of low-cost solutions: a comparison study
    M. Rebaudengo, M. Sonza Reorda, M. Violante, B. Nicolescu, R. Velasco
    DOI: 10.1109/RADECS.2001.1159312

  453. Devising an RT-Level ATPG for uProcessor Cores
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    WRTLT2001: 2nd Worshop on RTL, ATPG & DFT

  454. Effective Techniques for High-Level ATPG
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    Proceedings of the 10th Asian Test Symposium

  455. Evolving Effective CA/CSTP BIST Architectures for Sequential Circuits
    F. Corno, M. Sonza Reorda, G. Squillero
    Proceedings of the 2001 ACM symposium on Applied computing
    DOI: 10.1145/372202.372361

  456. Exploiting FPGA for accelerating Fault Injection Experiments
    P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante

  457. Exploiting FPGA-based Techniques for Fault Injection Campaigns on VLSI Circuits
    P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante

  458. FPGA-based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits
    P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    Lecture Notes in Computer Science (vol 2147)
    DOI: 10.1007/3-540-44687-7_51
    ABSTRACT: Designers of safety-critical VLSI systems are asking for effective tools for evaluating and validating their designs. Fault Injection is commonly adopted for this task, and its effectiveness is therefore a key factor. In this paper we propose to exploit FPGAs to speed-up Fault Injection for fault tolerance evaluation of VLSI circuits. A complete Fault Injection environment is described, relying on FPGA-based emulation of the circuit for fault effect analysis. The proposed approach allows combining the efficiency of hardware-based techniques, and the flexibility of simulation-based techniques. Experimental results are provided to support the feasibility and effectiveness of the approach. The work is partially funded by the Italian Ministry for University through the project "Sistemi di elaborazione reattivi ed affidabili per applicazioni industriali", the Italian Space Agency through the basic research project "Definizione e valutazione di tecniche software per la realizzazione di sistemi di elaborazione tolleranti ai guasti a basso costo", and by Politecnico di Torino through the Giovani Ricercatori project

  459. FPGA-based Fault Injection for Microprocessor Systems
    P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante

  460. On the Test of Microprocessor IP Cores
    F. Corno, M. Sonza Reorda, M. Violante, G. Squillero
    Proceedings of the conference on Design, automation and test in Europe

  461. System Safety through Automatic High-level Code Transformations: an Experimental Evaluation
    M. Rebaudengo, M. Sonza Reorda, M. Violante, P. Cheynet, B. Nicolescu, R. Velazco

  462. A Genetic Algorithm-based System for Generating Test Programs for Microprocessor IP Cores
    F. Corno, M. Sonza Reorda, G. Squillero, M. Violante
    ICTAI2000: The Twelfth IEEE International Conference on Tools with Artificial Intelligence, Vancouver, British Columbia, Canada, November 13-15, 2000, pp. 195-198

  463. An Intelligent User Interface oriented to non-expert users
    F. Corno, L. Farinetti, G. Squillero
    World Conference on the WWW and Internet

  464. An RT-level Fault Model with High Gate Level Correlation
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    Proceedings of the IEEE International High-Level Validation and Test Workshop (HLDVT'00)

  465. An experimental evaluation of the effectiveness of automatic rule-based transformations for safety-critical applications
    M. Rebaudengo, M. Sonza Reorda, M. Torchiano, M. Violante
    DOI: 10.1109/DFTVS.2000.887164

  466. An improved cellular automata-based BIST architecture for sequential circuits
    F. Corno, M. Sonza Reorda, G. Squillero
    DOI: 10.1109/ISCAS.2000.857030
    ABSTRACT: C2BIST (Circular CA BlST) is a Built-In Self Test (BIST) architecture for sequential circuits based on Cellular Automata (CA). When CA cells implement suitable rules, this structure shows good test generation capabilities, reaching high fault coverage. The main characteristic of this approach is that the same CA is used for both generation and compaction, leading to a trade-off between attained fault coverage and area overhead more favorable than other BIST approaches. On the other hand, the main problem is that the circuit, during the test phase, may enter a loop early, reducing the attained fault coverage. The paper analyzes this problem and proposes a solution based on the partial reset technique, that is able to break cycles by exploiting the circuit flip-flops synchronous reset signal with a small area overhead with respect to the basic C2BIST architecture. Experimental results allow a quantitative evaluation of the effectiveness of this approach

  467. Archivi on-line fruibili da utenti inesperti: un'esperienza nel campo della disabilità
    F. Corno, G. Squillero
    Convegno AICA sull'Informatica per la Didattica

  468. Automatic Test Bench Generation for Simulation-based Validation
    M. Lajolo, L. Lavagno, M. Rebaudengo, M. Sonza Reorda, M. Violante

  469. Automatic Validation of Protocol Interfaces Described in VHDL
    F. Corno, M. Sonza Reorda, G. Squillero
    Real-World Applications of Evolutionary Computing
    DOI: 10.1007/3-540-45561-2_20
    ABSTRACT: In present days, most of the design activity is performed at a high level of abstraction, thus designers need to be sure that their designs are syntactically and semantically correct before starting the automatic synthesis process. The goal of this paper is to propose an automatic input pattern generation tool able to assist designers in the generation of a test bench for difficult parts of small- or medium- sized digital protocol interfaces. The proposed approach exploit a Genetic Algorithm connected to a commercial simulator for cultivating a set of input sequence able to execute given statements in the interface description. The proposed approach has been evaluated on the new ITC'99 benchmark set, a collection of circuits offering a wide spectrum of complexity. Experimental results show that some portions of the circuits remained uncovered, and the subsequent manual analysis allowed identifying design redundancies

  470. Automatic test bench generation for validation of RT-level descriptions: an industrial experience
    F. Corno, A. Manzone, A. Pincetti, M. Sonza Reorda, G. Squillero
    DOI: 10.1145/343647.343802
    ABSTRACT: In current microprocessors and systems, an increasingly high silicon portion is derived through automatic synthesis with designers working exclusively at the RT-level, and design productivity is greatly enhanced. However, in the new design flow, validation still remains a challenge: while new technologies based on formal verification are only marginally accepted, standard techniques based on simulation are beginning to fall behind the increased circuit complexity. This paper proposes a new approach to simulation-based validation, in which a genetic algorithm helps the designer in generating useful input sequences to be included in the test bench. The technique has been applied to an industrial circuit, showing that the quality of the validation process is increased

  471. Behavioral-level test vector generation for system-on-chip designs
    M. Lajolo, M. Rebaudengo, M. Sonza-Reorda, M. Violante, L. Lavagno
    Proceedings IEEE International High-Level Design Validation and Test Workshop

  472. CA-CSTP: A new BIST Architecture for Sequential Circuit
    F. Corno, M. Sonza Reorda, G. Squillero, M. Violante
    Proceedings of the IEEE European Test Workshop

  473. Early Power Estimation for System-on-Chip Designs
    M. Lajolo, L. Lavagno, M. Sonza Reorda, M. Violante
    Integrated Circuit Design
    DOI: 10.1007/3-540-45373-3_11
    ABSTRACT: Reduction of chip packaging and cooling costs for deep sub-micron System-On-Chip (SOC) designs is an emerging issue. We present a simulationbased methodology able to realistically model the complex environment in which a SOC design operates in order to provide early and accurate power consumption estimation. We show that a rich functional test bench provided by a designer with a deep knowledge of a complex system is very often not appropriate for power analysis and can lead to power estimation errors of some orders of magnitude. To address this issue, we propose an automatic input sequence generation approach based on a heuristic algorithm able to upgrade a set of test vectors provided by the designer. The obtained sequence closely reflects the worst-case power consumption for the chip and allows looking at how the chip is going to work over time

  474. Evaluating system dependability in a co-design framework
    M. Lajolo, M. Rebaudengo, M. Sonza-Reorda, M. Violante, L. Lavagno
    Proceedings IEEE Design Automation and Test in Europe Conference

  475. Evaluating the effectiveness of a Software Fault-Tolerance technique on RISC- and CISC-based architectures
    M. Rebaudengo, M. Sonza Reorda, M. Violante, P. Cheynet, B. Nicolescu, R. Velazco
    DOI: 10.1109/OLT.2000.856606

  476. Evolving Cellular Automata for Self-Testing Hardware
    F. Corno, M. Sonza Reorda, G. Squillero
    Evolvable Systems: From Biology to Hardware
    DOI: 10.1007/3-540-46406-9_4
    ABSTRACT: Testing is a key issue in the design and production of digital circuits: the adoption of BIST (Built-In Self-Test) techniques is increasingly popular, but requires efficient algorithms for the generation of the logic which generates the test vectors applied to the Unit Under Test. This paper addresses the issue of identifying a Cellular Automaton able to generate input patterns to detect stuckat faults inside a Finite State Machine (FSM) circuit. Previous results already proposed a solution based on a Genetic Algorithm which directly identifies a Cellular Automaton able to reach good Fault Coverage of the stuck-at faults. However, such method requires 2-bit cells in the Cellular Automaton, thus resulting in a high area overhead. This paper presents a new solution, with an area occupation limited to 1 bit per cell; the improved results are possible due to the adoption of a new optimization algorithm, the Selfish Gene algorithm. Experimental results are provided, which show that in most of the standard benchmark circuits the Cellular Automaton selected by the Selfish Gene algorithm is able to reach a Fault Coverage higher that what can be obtained with current engineering practice with comparable area occupation

  477. Exploiting the selfish gene algorithm for evolving cellular automata
    F. Corno, M. Sonza Reorda, G. Squillero
    DOI: 10.1109/IJCNN.2000.859457
    ABSTRACT: This paper shows an application in the field of Electronic CAD of the Selfish Gene algorithm, an evolutionary algorithm based on a recent interpretation of the Darwinian theory. Testing is a key issue in the design and production of digital circuits and the adoption of Built-In Self-Test (BIST) techniques is increasingly popular. In this paper, the Selfish Gene algorithm is adopted for determining the logic for a BIST architecture based on Cellular Automata (CA). A Genetic Algorithm has already been proposed for identifying good BIST architectures based on CA. However, by adopting 2-bit cells, such a method introduced a significant area overhead. Thanks to the adoption of the new and more powerful search engine, we were able to identify simpler BIST structures with a lower area overhead, but still able to obtain the same fault coverage

  478. High-Level Observability for Effective High-Level ATPG
    F. Corno, M. Sonza Reorda, G. Squillero
    VTS2000: 18th IEEE VLSI Test Symposium, Montreal, Canada, May 2000, pp. 411-416

  479. Low Power BIST via Hybrid Cellular Automata
    F. Corno, M. Rebaudengo, M. Sonza Reorda, G. Squillero, M. Violante
    VTS2000: 18th IEEE VLSI Test Symposium, Montreal, Canada, May 2000, pp. 29-34

  480. Low Power BIST via Non-Linear Hybrid Cellular Automata
    F. Corno, M. Rebaudengo, M. Sonza Reorda, G. Squillero, M. Violante
    Proceedings of the 18th IEEE VLSI Test Symposium (VTS'00)

  481. New Techniques for Accelerating Fault Injection in VHDL descriptions
    B. Parrotta, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DOI: 10.1109/OLT.2000.856613

  482. Prediction of Power Requirements for High-Speed Circuits
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    Real-World Applications of Evolutionary Computing
    DOI: 10.1007/3-540-45561-2_24
    ABSTRACT: Modern VLSI design methodologies and manufacturing technologies are making circuits increasingly fast. The quest for higher circuit performance and integration density stems from fields such as the telecommunication one where high speed and capability of dealing with large data sets is mandatory. The design of high-speed circuits is a challenging task, and can be carried out only if designers can exploit suitable CAD tools. Among the several aspects of high-speed circuit design, controlling power consumption is today a major issue for ensuring that circuits can operate at full speed without damages. In particular, tools for fast and accurate estimation of power consumption of highspeed circuits are required. In this paper we focus on the problem of predicting the maximum power consumption of sequential circuits. We formulate the problem as a constrained optimization problem, and solve it resorting to an evolutionary algorithm. Moreover, we empirically assess the effectiveness of our problem formulation with respect to the classical unconstrained formulation. Finally, we report experimental results assessing the effectiveness of the prototypical tool we implemented

  483. RT-level Fault Simulation Techniques based on Simulation Command Scripts
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    DCIS2000: XV Conference on Design of Circuits and Integrated Systems, Le Corum, Montpellier, November 21-24, 2000, pp. 825-830

  484. Speeding-up Fault Injection Campaigns in VHDL models
    B. Parrotta, M. Rebaudengo, M. Sonza Reorda, M. Violante
    Lecture Notes in Computer Science (vol 1943)
    DOI: 10.1007/3-540-40891-6_3
    ABSTRACT: Simulation-based Fault Injection in VHDL descriptions is increasingly common due to the popularity of top-down design flows exploiting this language. This paper presents some techniques for reducing the time to perform the required simulation experiments. Static and dynamic methods are proposed to analyze the list of faults to be injected, removing faults as soon as their behavior is known. Common features available in most VHDL simulation environments are also exploited. Experimental results show that the proposed techniques are able to reduce the time required by a typical Fault Injection campaign by a factor ranging from 43.9% to 96.6%

  485. System-level test bench generation in a co-design framework
    M. Lajolo, M. Rebaudengo, M. Sonza-Reorda, M. Violante, L. Lavagno
    Proceedings IEEE European Test Workshop

  486. A New BIST Architecture for Low Power Circuits
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DOI: 10.1109/ETW.1999.804523

  487. A low cost programmable board for speeding-upfault-injection in Microprocessor based systems
    A. Benso, P. Civera, M. Rebaudengo, M. Sonza Reorda

  488. ALPS: a peak power estimation tool for sequential circuits
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DOI: 10.1109/GLSV.1999.757454

  489. Approximate Equivalence Verification for Protocol Interface Implementation via Genetic Algorithms
    F. Corno, M. Sonza Reorda, G. Squillero
    Lecture Notes in Computer Science (vol 1596)
    DOI: 10.1007/10704703_15
    ABSTRACT: This paper describes a new approximate approach for checking the correctness of the implementation of a protocol interface, comparing its low-level implementation with its high-level prototype. The possibility to validate protocol interfaces is extremely useful in many industrial design flows and the proposed methodology does not impose particular requirements and it is able to fit in existing design flows: the proposed approach is based on coupling a commercial simulator with a genetic algorithm that tries to disprove the equivalence of an implementation with its high-level prototype. The use of a commercial simulator guarantees a complete compatibility with current standards and the method is able to fit painlessly in an existing industrial flow. Moreover, the use of a genetic algorithm allows the analysis of large and realistic designs. Experimental results show that the proposed method is effectively able to deal with realistic designs, discovering potential problems, and, although approximate in nature, it is able to provide a high degree of confidence in the results

  490. Approximate equivalence verification of sequential circuits via genetic algorithms
    F. Corno, M. Sonza Reorda, G. Squillero
    DOI: 10.1145/307418.307431

  491. Evaluating the fault tolerance capabilities of embedded systems via BDM
    M. M. Rebaudengo
    DOI: 10.1109/VTEST.1999.766703

  492. FlexFi: A Flexible Fault Injection Environment for Microprocessor-Based Systems
    A. Benso, M. Rebaudengo, M. Sonza Reorda
    Lecture Notes in Computer Science (vol 1698)
    DOI: 10.1007/3-540-48249-0_28
    ABSTRACT: Microprocessor-based systems are increasingly used to control safety-critical systems (e.g., air and railway traffic control, nuclear plant control, aircraft and car control). In this case, fault tolerance mechanisms are introduced at the hardware and software level. Debugging and verifying the correct design and implementation of these mechanisms ask for effective environments, and Fault Injection represents a viable solution for their implementation. In this paper we present a flexible environment suitable to compute the fault coverage provided by hardware and software mechanisms existing in most microprocessor-based systems. The environment, called FlexFI, is flexible, since it allows the adoption of different solutions for implementing the most critical modules, which differ in terms of cost, speed, and intrusiveness in the original system behavior

  493. High Quality Test Pattern Generation for RT-level VHDL Descriptions
    F. Corno, M. Sonza Reorda, G. Squillero
    2nd International Workshop on Microprocessor Test and Verification Common Challenges and Solutions

  494. Optimal vector selection for low power BIST
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DOI: 10.1109/DFTVS.1999.802888

  495. Optimizing Deceptive Functions with the SG-Clans Algorithm
    F. Corno, M. Sonza Reorda, G. Squillero
    Congress on Evolutionary Computation

  496. Simulation-Based Sequential Equivalence Checking of RTL VHDL
    F. Corno, M. Sonza Reorda, G. Squillero
    Proceedings the 6th IEEE International Conference on Electronics, Circuits and Systems

  497. Soft-error detection through software fault-tolerance techniques
    M. Rebaudengo, M. Sonza Reorda, M. Torchiano, M. Violante
    DOI: 10.1109/DFTVS.1999.802887
    ABSTRACT: The paper describes a systematic approach for automatically introducing data and code redundancy into an existing program written using a high-level language. The transformations aim at making the program able to detect most of the soft-errors affecting data and code, independently of the Error Detection Mechanisms (EDMs) possibly implemented by the hardware. Since the transformations can be automatically applied as a pre-compilation phase, the programmer is freed from the cost and responsibility of introducing suitable EDMs in its code. Preliminary experimental results are reported, showing the fault coverage obtained by the method, as well as some figures concerning the slow-down and code size increase it causes

  498. Test Pattern Generation under Low Power Constraints
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    Evolutionary Image Analysis, Signal Processing and Telecommunications
    DOI: 10.1007/10704703_13
    ABSTRACT: A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunication systems, make power management during test a critical problem. A Genetic Algorithm computes a set of redundant test sequences, then a genetic optimization algorithm selects the optimal subset of sequences able to reduce the consumed power, without reducing the fault coverage. Experimental results gathered on benchmark circuits show that our approach decreases the peak power consumption by 20% on the average with respect to the original test sequence generated ignoring the power dissipation problem, without affecting the fault coverage

  499. Transformation-based peak power reduction for test sequences
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DOI: 10.1109/LPD.1999.750406

  500. Verifying the Equivalence of Sequential Circuits with Genetic Algorithms
    F. Corno, M. Sonza Reorda, G. Squillero
    Congress on Evolutionary Computation

  501. A Fault Injection Environment for Microprocessor-based Board
    A. Benso, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    DOI: 10.1109/TEST.1998.743259
    KEYWORDS: digital system design test and verification; computer testing; fault diagnosis; system testing; fault injection; fault tolerance; microprocessors
    ABSTRACT: Evaluating the faulty behaviour of low-cost microprocessor-based boards is an increasingly important issue, due to their usage in many safety critical systems. To address this issue, the paper describes a software-implemented fault injection system based on the trace exception mode available in most microprocessors. The architecture of the complete fault injection environment is proposed, integrating modules for generating a fault list, for performing their injection and for gathering the results, respectively. Data gathered from some sample benchmark applications are presented The main advantages of the approach are low cost, good portability, and high efficiency

  502. A Hybrid Fault Injection Methodology for Real Time Systems
    A. Benso, P. Civera, M. Rebaudengo, M. Sonza Reorda, A. Ferro, L. Macchiarulo, M. Violante, P. Prinetto, R. Ubar, J. Raik
    FTCS-28: 28th Annual International Symposium on Fault-Tolerant Computing

  503. A New Evolutionary Algorithm Inspired by the Selfish Gene Theory
    F. Corno, M. Sonza Reorda, G. Squillero
    IEEE International Conference on Evolutionary Computation

  504. A System for Evaluating On-Line Testability at the RT-level
    S. Chiusano, F. Corno, M. Sonza Reorda, R. Vietti

  505. A test pattern generation methodology for low power consumption
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    DOI: 10.1109/VTEST.1998.670912

  506. An integrated HW and SW fault injection environment for real-time systems
    A. Benso, P. Civera, M. Rebaudengo, M. Sonza Reorda
    DOI: 10.1109/DFTVS.1998.732158

  507. Experiences in the use of evolutionary techniques for testing digital circuits
    F. Corno, M. Rebaudengo, M. Sonza Reorda
    DOI: 10.1117/12.326704

  508. Exploiting symbolic techniques for partial scan flip flop selection
    F. Corno, P. Prinetto, M. Sonza Reorda, M. Violante
    DATE 1998 : IEEE Design Automation and Test Conference in Europe, 1998
    DOI: 10.1109/DATE.1998.655930 

  509. Exploiting the background debugging mode in a fault injection system
    P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    IPDS'98: IEEE International Computer Performance and Dependability Symposium
    DOI: 10.1109/IPDS.1998.707736

  510. Fast sequential circuit test generation using high-level and gate-level techniques
    E. Rudnick, R. Vietti, A. Ellis, F. Corno, P. Prinetto, M. Sonza Reorda
    DOI: 10.1109/DATE.1998.655915

  511. Fault-list collapsing for fault-injection experiments
    A. Benso, M. Rebaudengo, L. Impagliazzo, P. Marmo
    DOI: 10.1109/RAMS.1998.653808

  512. On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits
    P. Prinetto, M. Sonza Reorda, N. Gaudenzi, F. Corno
    DOI: 10.1109/VTEST.1998.670902

  513. The Selfish Gene Algorithm: a New Evolutionary Optimization Strategy
    F. Corno, M. Sonza Reorda, G. Squillero
    Proceedings of the 1998 ACM symposium on Applied Computing
    DOI: 10.1145/330560.330838

  514. The training environment for the course on microprocessor systems at the Politecnico di Torino
    M. M. Rebaudengo
    DOI: 10.1145/1275182.1275190

  515. VEGA: A Verification Tool Based on Genetic Algorithms
    F. Corno, M. Sonza Reorda, G. Squillero
    Proceedings the International Conference on Circuit Design

  516. A New Approach for Initialization Sequences Computation for Synchronous Sequential Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, G. Squillero
    1997 IEEE Proceedings of the International Conference on Computer Design

  517. A genetic algorithm for the computation of initialization sequences for synchronous sequential circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, G. Squillero
    DOI: 10.1109/ATS.1997.643917
    ABSTRACT: Testing circuits which do not include a global reset signal requires either complex ATPG algorithms based on 9- or even 256-valued algebras, or some suitable method to generate initialization sequences. This paper follows the latter approach, and presents a new method to the automated generation of an initialization sequence for synchronous sequential circuits. We propose a Genetic Algorithm providing a sequence that aims at initializing the highest number of flip flops with the lowest number of vectors. The experimental results show that the approach is feasible to be applied even to the largest benchmark circuits and that it compares well to other known approaches in terms of initialized flip flops and sequence length. Finally, this paper shows how the initialization sequences can be fruitfully exploited by simplifying the ATPG process

  518. A new approach to build a low-level Malicious Fault List starting from High-level description and Alternative Graphs
    A. Benso, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, R. Ubar

  519. Boolean function manipulation on a parallel system using BDDs
    F. Bianchi, F. Corno, M. Rebaudengo, M. Sonza Reorda, R. Ansaloni
    Lecture Notes in Computer Science (vol 1225)
    DOI: 10.1007/BFb0031663
    ABSTRACT: This paper describes a distributed algorithm for Boolean function manipulation. The algorithm is based on Binary Decision Diagrams (BDDs), which are one of the most commonly used data structures for representing and manipulating Boolean functions. A new distributed version of a BDD data structure and a distributed implementation of the basic operator for its manipulation are presented. The algorithm is suitable to work on a MIMD architecture and is based on a message passing master-slave paradigm. A package has been written, which uses the PVM library and is portable on different architectures. Two applications have been developed using the parallel BDD package. In both cases the results show that the new distributed version of the algorithm is able to manage BDDs much larger than the ones managed by mono-processor tools

  520. Cellular automata for deterministic sequential test pattern generation
    S. Chiusano, F. Corno, P. Prinetto, M. Sonza Reorda

  521. Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DOI: 10.1109/ATS.1997.643922

  522. Exploiting Symbolic Techniques within Genetic Algorithms for Power Optimization
    S. Chiusano, F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda

  523. Exploiting high-level descriptions for circuits fault tolerance assessment
    A. Benso, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, J. Raik, R. Ubar
    DOI: 10.1109/DFTVS.1997.628327

  524. GA-based Performance Analysis of Network Protocols
    M. Baldi, F. Corno, M. Rebaudengo, M. Sonza Reorda, G. Squillero
    9th IEEE Proceedings the International Conference on Tools with Artificial Intelligence
    DOI: 10.1109/TAI.1997.632245
    ABSTRACT: This paper tackles the problem of analyzing the correctness and performance of a computer network protocol. Given the complexity of the problem, no currently used technique is able to achieve good results: formal techniques can discover some bugs but can be applied to over-simplified models, only; on the other hand, statistical techniques relying on simulation often fail to find some critical cases for the protocol. Our proposed approach relies on coupling a genetic algorithm with a simulator of the system under verification. Genetic algorithms recently proved themselves excellent tools for giving good, yet approximate, solution to hard-to-solve problems. To prove the effectiveness of our approach, we applied it to the quantitative verification of a network protocol: the complexity of this problem prevents the application of exact techniques, while experimental results show that the verification results we obtained are better than one can achieve with traditional statistical methods. As an example, the approach is applied to the verification of the TCP protocol operating on a given network. A genetic algorithm is able to find a configuration of the traffic over the network that sensitizes a critical problem in the TCP protocol

  525. Guaranteeing Testability in Re-encoding for Low Power
    S. Chiusano, F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda

  526. Hybrid Symbolic-Explicit Techniques for the Graph Coloring Problem
    S. Chiusano, F. Corno, P. Prinetto, M. Sonza Reorda

  527. New Static Compaction Techniques of Test Sequences for Sequential Circuits
    F. Corno, M. Rebaudengo, P. Prinetto, M. Sonza Reorda

  528. Optimizing area loss in flat glass cutting
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, S. Bisotto
    DOI: 10.1049/cp:19971222

  529. SAARA: a simulated annealing algorithm for test pattern generation for digital circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    DOI: 10.1145/331697.331745

  530. Simulation-Based Verification of Network Protocols Performance
    M. Baldi, F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, G. Squillero
    Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification
    ABSTRACT: Formal verification techniques need to deal with the complexity of the systems being verified. Most often, this problem is solved by taking an abstract model of the system and aiming at a complete verification of an approximation of the system. This paper proposes a complementary verification approach, in which the approximation is introduced into the verification algorithm, instead of the system model: we achieve an approximate verification of a fairly complete and detailed system model. The proposed technique relies on coupling a Genetic Algorithm with a simulator of the system under verification, and is especially suited for verifying performance-related aspects. To prove the effectiveness of our approach, we applied it to the quantitative verification of a network protocol: the TCP protocol operating on a given network. A Genetic Algorithm is able to find a configuration of the traffic over the network that sensitizes a critical problem in the TCP protocol that would be difficult to find both with exact techniques and stochastic ones

  531. Testability analysis and ATPG on behavioral RT-level VHDL
    F. Corno, P. Prinetto, M. Sonza Reorda
    DOI: 10.1109/TEST.1997.639688

  532. A cellular genetic algorithm for the Floorplan area optimization problem on a SIMD architecture
    S. Rebaudengo M.
    Lecture Notes in Computer Science (vol 1067)
    DOI: 10.1007/3-540-61142-8_675

  533. A genetic algorithm for automatic generation of test logic for digital circuits
    F. Corno, P. Prinetto, M. Sonza Reorda
    ICTAI 1996 : 8th IEEE International Conference on Tools with Artificial Intelligence, 1996
    DOI: 10.1109/TAI.1996.560394
    ABSTRACT: Testing is a key issue in the design and production of digital circuits: the adoption of BIST (Built-in Self-Test) techniques is increasingly popular, but sometimes requires efficient algorithms for the automatic generation of the logic which generates the test vectors applied to the unit under test. This paper addresses the issue of identifying a cellular automaton able to generate input patterns to detect stuck-at faults inside a finite state machine (FSM). A suitable hardware structure is first identified. A genetic algorithm is then proposed, which directly identifies a cellular automaton able to reach a very good fault coverage of the stuck-at faults. The novelty of the method consists in combining the generation of test patterns with the synthesis of a cellular automaton able to reproduce them. Experimental results are provided, which show that in most of the standard benchmark circuits the cellular automaton selected by the genetic algorithm is able to reach a fault coverage close to the maximum one. Our approach is the first attempt of exploiting evolutionary techniques for identifying the hardware for input pattern generation in BIST structures

  534. A parallel genetic algorithm for Automatic Generation of Test Sequences for digital circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    Lecture Notes in Computer Science (vol 1067)
    DOI: 10.1007/3-540-61142-8_583
    ABSTRACT: The paper deals with the problem of Automatic Generation of Test Sequences for digital circuits. Genetic Algorithms have been successfully proposed to solve this industrially critical problem; however, they have some drawbacks, e.g., they are often unable to detect some hard to test faults, and require a careful tuning of the algorithm parameters. In this paper, we describe a new parallel version of an existing GA-based ATPG, which exploits competing sub-populations to overcome these problems. The new approach has been implemented in the PVM environment and has been evaluated on a workstation network using some of the standard benchmark circuits. The results show that it is able to significantly improve the results quality (by testing some critical faults) at the expense of increased CPU time requirements

  535. Advanced Techniques for GA-based sequential ATPGs
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, R. Mosca
    DOI: 10.1109/EDTC.1996.494328

  536. Comparing topological, symbolic and GA-based ATPGs: an experimental approach
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    DOI: 10.1109/TEST.1996.556941

  537. Exploiting competing subpopulations for automatic generation of test sequences for digital circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    Parallel Problem Solving from Nature — PPSN IV
    DOI: 10.1007/3-540-61723-X_1042
    ABSTRACT: The paper describes the application of a Parallel Genetic Algorithm to Automatic Test Pattern Generation (ATPG) for digital circuits. Genetic Algorithms have been already proposed to solve this industrially critical problem, both on mono- and multi-processor architectures. Although preliminary results are very encouraging, there are some obstacles which limit their use: in particular, GAs are often unable to detect some hard to test faults, and require a careful tuning of the algorithm parameters. In this paper, we describe a new parallel version of an existing GA-based ATPG, which exploits competing sub-populations to overcome these problems. The new approach has been implemented in the PVM environment and has been evaluated on a workstation network using standard benchmark circuits. Preliminary results show that it is able to improve the results quality (by testing additional critical faults) at the expense of increased CPU time requirements

  538. Fault Behavior Observation of a Microprocessor System through a VHDL Simulation-Based Fault Injection Experiment
    A. Amendola, A. Benso, F. Corno, L. Impagliazzo, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    DOI: 10.1109/EURDAC.1996.558255

  539. Fault Tolerant and BIST design of a FIFO cell
    F. Corno, P. Prinetto, M. Sonza Reorda
    Euro-DAC '96: IEEE European Design Automation Conference with Euro-VHDL '96 and Exhibition
    DOI: 10.1109/EURDAC.1996.558210 

  540. On-line testing of an off-the-shelf microprocessor board for safety-critical applications
    F. Corno, M. Damiani, L. Impagliazzo, P. Prinetto, M. Rebaudengo, G. Sartore, M. Sonza Reorda
    Lecture Notes in Computer Science (vol 1150)
    DOI: 10.1007/3-540-61772-8_38
    ABSTRACT: The paper describes the strategy adopted to implement on-line test procedures for a commercial microprocessor board used in an automated light-metro control system. Special care has been devoted to chose the most effective test strategy for memory elements, processors, and caches, while guaranteeing a minimum impact on the normal behavior of the whole system. Implementation of the described techniques will significantly improve the system ability to safely react to possible faults. This will be quantitatively determined in the subsequent dependability evaluation phase

  541. Partial scan flip flop selection for simulation-based sequential ATPGs
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    DOI: 10.1109/TEST.1996.557088

  542. Scan insertion criteria for low design impact
    S. Barbagallo, M. Lobetti Bodoni, D. Medina, F. Corno, P. Prinetto, M. Sonza Reorda
    VTS 1996 : IEEE VLSI Test Symposium
    DOI: 10.1109/VTEST.1996.510831

  543. Self-checking and Fault Tolerant approaches can help BIST fault coverage: a case study
    F. Corno, P. Prinetto, M. Sonza Reorda
    ED&TC 96: IEEE European Conference on Design and Test 1996
    DOI: 10.1109/EDTC.1996.494374 

  544. Using parallel genetic algorithms for solving the Min-Cut problem
    G. Godza, M. Rebaudengo, M. Sonza Reorda
    Lecture Notes in Computer Science (vol 1067)
    DOI: 10.1007/3-540-61142-8_674

  545. A Data Parallel Algorithm for Boolean Function Manipulation
    S. Gai, M. Rebaudengo, M. Sonza Reorda
    DOI: 10.1109/FMPC.1995.380467

  546. A PVM tool for automatic test generation on parallel and distributed systems
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, E. Veiluva
    Lecture Notes in Computer Science (vol 919)
    DOI: 10.1007/BFb0046607
    ABSTRACT: The use of parallel architectures for the solution of CPU and memory critical problems in the Electronic CAD area has been limited up to now by several factors, like the lack of efficient algorithms, the reduced portability of the code, and the cost of hardware. However, portable message-passing libraries are now available, and the same code runs on high-cost supercomputers, as well as on common workstation networks. The paper presents an effective ATPG system for large sequential circuits developed using the PVM library and based on a Genetic Algorithm. The tool, named GATTO *, runs on a DEC Alpha AXP farm and a CM-5. Experimental results are provided

  547. A portable ATPG tool for parallel and distributed systems
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, E. Veiluva
    DOI: 10.1109/VTEST.1995.512613

  548. An improved data parallel algorithm for Boolean function manipulation using BDDs
    S. Gai, M. Rebaudengo, M. Sonza Reorda
    DOI: 10.1109/EMPDP.1995.389132

  549. Exploiting massively parallel architectures for the solution of diffusion and propagation problems
    P. Delsanto, S. Biancotto, M. Scalerandi, M. Rebaudengo, M. Sonza Reorda
    Lecture Notes in Computer Science (vol 919)
    DOI: 10.1007/BFb0046601
    ABSTRACT: Many problems in several fields like physics, chemistry, biology and engineering lack an analytical solution able to provide a satisfactory phenomena description. Then a numerical solution becomes the only viable alternative. The use of massively parallel architectures often allows one to obtain in an easy way a comprehensive picture of the behaviour of the solution. We present here a computational model applied to two different physical problems; our work demonstrates the effectiveness of the approach and its extensibility to many classes of problems in different fields

  550. GARDA: a Diagnostic ATPG for Large Synchronous Sequential Circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    DOI: 10.1109/EDTC.1995.470385

  551. Improving topological ATPG with symbolic techniques
    F. Corno, U. Gläser, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, T. Vierhaus
    DOI: 10.1109/VTEST.1995.512658

  552. Testing a Switching Memory in a Telecommunication System
    S. Barbagallo, F. Corno, P. Prinetto, M. Sonza Reorda
    ITC 1995 : IEEE International Test Conference, 1995
    DOI: 10.1109/TEST.1995.529941

  553. Using symbolic techniques to find the maximum clique in very large sparse graphs
    F. Corno, P. Prinetto, M. Sonza Reorda
    DOI: 10.1109/EDTC.1995.470377

  554. A Genetic Algorithm for Floorplan Area Optimization
    M. Rebaudengo, M. Sonza Reorda
    DOI: 10.1109/ICEC.1994.350035

  555. A data parallel approach to Boolean function manipulation using BDDs
    G. Cabodi, S. Gai, M. Rebaudengo, M. Sonza Reorda
    DOI: 10.1109/MPCS.1994.367081

  556. An automatic test pattern generator for large sequential circuits based on Genetic Algorithms
    P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    DOI: 10.1109/TEST.1994.527955

  557. An experimental analysis of the effectiveness of the circular self-test path technique
    P. Prinetto, F. Corno, M. Sonza Reorda
    EURO-DAC '94: IEEE European design automation Conference
    DOI: 10.1145/198174.198254

  558. An industrial experience in the built-in self test of embedded RAM
    P. Camurati, P. Prinetto, M. Sonza Reorda, S. Barbagallo, A. Burri, D. Medina
    VTS 1994 : IEEE 12th VLSI Test Symposium
    DOI: 10.1109/VTEST.1994.292296 

  559. Exploiting massively parallel architectures for the analysis of growth phenomena
    P. Delsanto, G. Kaniadakis, M. Scalerandi, M. Rebaudengo, M. And Sonza Reorda

  560. Floorplan area optimization using genetic algorithms
    M. Rebaudengo, M. Sonza Reorda
    DOI: 10.1109/GLSV.1994.290002

  561. GATTO: an Intelligent Tool for Automatic Test Pattern Generation for Digital Circuits
    P. Prinetto, M. Rebaudengo, M. Sonza Reorda, E. Veiluva
    DOI: 10.1109/TAI.1994.346463

  562. Making the circular self-test path technique effective for real circuits
    F. Corno, P. Prinetto, M. Sonza Reorda
    ITC 1994 : IEEE International Test Conference, 1994
    DOI: 10.1109/TEST.1994.528044 

  563. Parallel processing analysis of the 1-D KPZ growth equation
    P. Delsanto, G. Kaniadakis, M. Scalerandi, M. Rebaudengo, M. And Sonza Reorda
    Physics Computing 1994

  564. An experimental analysis of the effects of migration in parallel genetic algorithms
    S. Rebaudengo M.
    DOI: 10.1109/EMPDP.1993.336398

  565. Finding the Maximurn Clique in a Graph Using BDDs
    F. Corno, P. Prinetto, M. Sonza Reorda
    ICVC93: IEEE 3rd International Conference on VLSI and CAD

  566. Hybrid Genetic Algorithms for the Travelling Salesman Problem
    P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    ICANNGA 1993: Artificial Neural Nets and Genetic Algorithms

  567. A new model for improving symbolic Product Machine traversal
    G. Cabodi, P. Camurati, F. Corno, S. Gai, P. Prinetto, M. Sonza Reorda

  568. A simulation-based approach to test pattern generation for synchronous circuits
    P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda
    DOI: 10.1109/VTEST.1992.232763

  569. Boolean Function Manipulation on Massively Parallel Computers
    G. Cabodi, S. Gai, M. Sonza Reorda
    DOI: 10.1109/FMPC.1992.234869

  570. Centralized vs. distributed implementation of FSM equivalence verification on a parallel system
    P. Camurati, P. Prinetto, M. Rebaudengo, Sonza Reorda M,
    EWPC '92 : the European Workshops on Parallel Computing: from theory to sound practic
    ABSTRACT: e

  571. Cross-fertilizing FSM Verification Techniques and Sequential Diagnosis
    G. Cabodi, P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda
    Proceedings of the 1992 IEEE EURO-DAC

  572. Efficient Verification of Sequential Circuits on a Parallel System
    P. Camurati, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
    DOI: 10.1109/EDAC.1992.205895

  573. Improved techniques for multiple stuck-at fault analysis using single stuck-at fault test sets
    P. Camurati, M. Rebaudengo, P. Prinetto, M. Sonza Reorda
    DOI: 10.1109/ISCAS.1992.229933

  574. Sequential circuit diagnosis based on formal verification techniques
    G. Cabodi, P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda
    ITC 1992: IEEE International Test Conference 1992

  575. An Algebraic Approach to Test Generation for Sequential Circuits
    A. Lioy, E. Macii, A. Meo, M. Sonza Reorda
    DOI: 10.1109/GLSV.1991.143952

  576. An experimental comparison of different approaches to ROM BIST
    S. Barbagallo, A. Burri, D. Medina, P. Camurati, P. Prinetto, M. Sonza Reorda
    CompEuro'91: IEEE 5th Annual European Computer Conference on VLSI and Computers
    DOI: 10.1109/CMPEUR.1991.257450

  577. Comparing ATPGs for synchronous sequential circuits
    P. Camurati, M. Gilli, A. Meo, P. Prinetto, M. Sonza Reorda
    CompEuro'91: IEEE 5th Annual European Computer Conference on VLSI and Computers
    DOI: 10.1109/CMPEUR.1991.257386

  578. Fast Differential Fault Simulation by Dynamic Fault Ordering
    G. Cabodi, S. Gai, M. Sonza Reorda

  579. Proving finite state machines correct with an automaton-based method
    P. Camurati, M. Gilli, P. Prinetto, M. Sonza Reorda
    IEEE First Great Lakes Symposium on VLSI
    DOI: 10.1109/GLSV.1991.143975

  580. The Product Machine and Implicit Enumeration to prove FSMs correct
    P. Camurati, M. Gilli, P. Prinetto, M. Sonza Reorda
    Correct Hardware Design Methodologies

  581. The use of model checking in ATPG for sequential circuits
    P. Camurati, M. Gilli, P. Prinetto, M. Sonza Reorda
    Lecture Notes in Computer Science (vol 531)
    DOI: 10.1007/BFb0023722
    ABSTRACT: Some design environments may prevent Design for Testability techniques from reducing testing to a combinational problem: ATPG for sequential devices remains a challenging field. Random and deterministic structure-oriented techniques are the state-of-the-art, but there is a growing interest in methods where the function implemented by the circuit is known. This paper shows how a test pattern may be generated while trying to disprove the equivalence of a good and a faulty machine. The algorithms are derived from Graph Theory and Model Checking. An example is analyzed to discuss the applicability and the cost of such an approach

  582. A diagnostic test pattern generation algorithm
    P. Camurati, D. Medina, P. Prinetto, M. Sonza Reorda
    ITC 1990: IEEE International Test Conference 1990
    DOI: 10.1109/TEST.1990.114000

  583. A new algorithm for diagnosis-oriented automatic test pattern generation
    P. Camurati, D. Medina, P. Prinetto, M. Sonza Reorda
    EuroASIC 1990: IEEE EURO ASIC
    DOI: 10.1109/EASIC.1990.207964

  584. Diagnosis Oriented Test Pattern Generation
    P. Camurati, A. Lioy, P. Prinetto, M. Sonza Reorda
    DOI: 10.1109/EDAC.1990.136693

  585. Model Checking and Graph Theory in sequential ATPG
    P. Camurati, M. Gilli, P. Prinetto, M. Sonza Reorda
    CAV 1990: Workshop on Computer-Aided Verification

  586. Exact probabilistic testability measures for multi-output circuits
    P. Camurati, P. Prinetto, Sonza Reorda M,
    Robotic systems and AMT: IFIP TC5/WG5.3 International Conference on CAD/CAM and AMT, 1989

  587. Probabilistic Testability Analysis
    P. Camurati, P. Prinetto, Sonza Reorda M,
    CAD&CG 1989: International Conference on Computer-Aided Design & Computer Graphics

  588. Testability measures with concurrent good simulation
    Cabodi G.P, P. Camurati, P. Prinetto, M. Sonza Reorda
    ETC'89: IEEE 1st European Test Conference
    DOI: 10.1109/ETC.1989.36236

  589. Random Testability Analysis: comparing and evaluating existing approaches
    P. Camurati, P. Prinetto, M. Sonza Reorda
    DOI: 10.1109/ICCD.1988.25662