
A New BIST Architecture for Low Power Circuits
F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
DOI: 10.1109/ETW.1999.804523 
A low cost programmable board for speedingupfaultinjection in Microprocessor based systems
A. Benso, P. Civera, M. Rebaudengo, M. Sonza Reorda 
ALPS: a peak power estimation tool for sequential circuits
F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
DOI: 10.1109/GLSV.1999.757454 
Approximate Equivalence Verification for Protocol Interface Implementation via Genetic Algorithms
F. Corno, M. Sonza Reorda, G. Squillero
Lecture Notes in Computer Science (vol 1596)
DOI: 10.1007/10704703_15
ABSTRACT: This paper describes a new approximate approach for checking the correctness of the implementation of a protocol interface, comparing its lowlevel implementation with its highlevel prototype. The possibility to validate protocol interfaces is extremely useful in many industrial design flows and the proposed methodology does not impose particular requirements and it is able to fit in existing design flows: the proposed approach is based on coupling a commercial simulator with a genetic algorithm that tries to disprove the equivalence of an implementation with its highlevel prototype. The use of a commercial simulator guarantees a complete compatibility with current standards and the method is able to fit painlessly in an existing industrial flow. Moreover, the use of a genetic algorithm allows the analysis of large and realistic designs. Experimental results show that the proposed method is effectively able to deal with realistic designs, discovering potential problems, and, although approximate in nature, it is able to provide a high degree of confidence in the results 
Approximate equivalence verification of sequential circuits via genetic algorithms
F. Corno, M. Sonza Reorda, G. Squillero
DOI: 10.1145/307418.307431 
Evaluating the fault tolerance capabilities of embedded systems via BDM
M. M. Rebaudengo
DOI: 10.1109/VTEST.1999.766703 
FlexFi: A Flexible Fault Injection Environment for MicroprocessorBased Systems
A. Benso, M. Rebaudengo, M. Sonza Reorda
Lecture Notes in Computer Science (vol 1698)
DOI: 10.1007/3540482490_28
ABSTRACT: Microprocessorbased systems are increasingly used to control safetycritical systems (e.g., air and railway traffic control, nuclear plant control, aircraft and car control). In this case, fault tolerance mechanisms are introduced at the hardware and software level. Debugging and verifying the correct design and implementation of these mechanisms ask for effective environments, and Fault Injection represents a viable solution for their implementation. In this paper we present a flexible environment suitable to compute the fault coverage provided by hardware and software mechanisms existing in most microprocessorbased systems. The environment, called FlexFI, is flexible, since it allows the adoption of different solutions for implementing the most critical modules, which differ in terms of cost, speed, and intrusiveness in the original system behavior 
High Quality Test Pattern Generation for RTlevel VHDL Descriptions
F. Corno, M. Sonza Reorda, G. Squillero
2nd International Workshop on Microprocessor Test and Verification Common Challenges and Solutions 
Optimal vector selection for low power BIST
F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
DOI: 10.1109/DFTVS.1999.802888 
Optimizing Deceptive Functions with the SGClans Algorithm
F. Corno, M. Sonza Reorda, G. Squillero
Congress on Evolutionary Computation 
SimulationBased Sequential Equivalence Checking of RTL VHDL
F. Corno, M. Sonza Reorda, G. Squillero
Proceedings the 6th IEEE International Conference on Electronics, Circuits and Systems 
Softerror detection through software faulttolerance techniques
M. Rebaudengo, M. Sonza Reorda, M. Torchiano, M. Violante
DOI: 10.1109/DFTVS.1999.802887
ABSTRACT: The paper describes a systematic approach for automatically introducing data and code redundancy into an existing program written using a highlevel language. The transformations aim at making the program able to detect most of the softerrors affecting data and code, independently of the Error Detection Mechanisms (EDMs) possibly implemented by the hardware. Since the transformations can be automatically applied as a precompilation phase, the programmer is freed from the cost and responsibility of introducing suitable EDMs in its code. Preliminary experimental results are reported, showing the fault coverage obtained by the method, as well as some figures concerning the slowdown and code size increase it causes 
Test Pattern Generation under Low Power Constraints
F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
Evolutionary Image Analysis, Signal Processing and Telecommunications
DOI: 10.1007/10704703_13
ABSTRACT: A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. Highspeed computation intensive VLSI systems, as telecommunication systems, make power management during test a critical problem. A Genetic Algorithm computes a set of redundant test sequences, then a genetic optimization algorithm selects the optimal subset of sequences able to reduce the consumed power, without reducing the fault coverage. Experimental results gathered on benchmark circuits show that our approach decreases the peak power consumption by 20% on the average with respect to the original test sequence generated ignoring the power dissipation problem, without affecting the fault coverage 
Transformationbased peak power reduction for test sequences
F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
DOI: 10.1109/LPD.1999.750406 
Verifying the Equivalence of Sequential Circuits with Genetic Algorithms
F. Corno, M. Sonza Reorda, G. Squillero
Congress on Evolutionary Computation 
A Fault Injection Environment for Microprocessorbased Board
A. Benso, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
DOI: 10.1109/TEST.1998.743259
KEYWORDS: digital system design test and verification; computer testing; fault diagnosis; system testing; fault injection; fault tolerance; microprocessors
ABSTRACT: Evaluating the faulty behaviour of lowcost microprocessorbased boards is an increasingly important issue, due to their usage in many safety critical systems. To address this issue, the paper describes a softwareimplemented fault injection system based on the trace exception mode available in most microprocessors. The architecture of the complete fault injection environment is proposed, integrating modules for generating a fault list, for performing their injection and for gathering the results, respectively. Data gathered from some sample benchmark applications are presented The main advantages of the approach are low cost, good portability, and high efficiency 
A Hybrid Fault Injection Methodology for Real Time Systems
A. Benso, P. Civera, M. Rebaudengo, M. Sonza Reorda, A. Ferro, L. Macchiarulo, M. Violante, P. Prinetto, R. Ubar, J. Raik
FTCS28: 28th Annual International Symposium on FaultTolerant Computing 
A New Evolutionary Algorithm Inspired by the Selfish Gene Theory
F. Corno, M. Sonza Reorda, G. Squillero
IEEE International Conference on Evolutionary Computation 
A System for Evaluating OnLine Testability at the RTlevel
S. Chiusano, F. Corno, M. Sonza Reorda, R. Vietti 
A test pattern generation methodology for low power consumption
F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
DOI: 10.1109/VTEST.1998.670912 
An integrated HW and SW fault injection environment for realtime systems
A. Benso, P. Civera, M. Rebaudengo, M. Sonza Reorda
DOI: 10.1109/DFTVS.1998.732158 
Experiences in the use of evolutionary techniques for testing digital circuits
F. Corno, M. Rebaudengo, M. Sonza Reorda
DOI: 10.1117/12.326704 
Exploiting symbolic techniques for partial scan flip flop selection
F. Corno, P. Prinetto, M. Sonza Reorda, M. Violante
DATE 1998 : IEEE Design Automation and Test Conference in Europe, 1998
DOI: 10.1109/DATE.1998.655930 
Exploiting the background debugging mode in a fault injection system
P. Prinetto, M. Rebaudengo, M. Sonza Reorda
IPDS'98: IEEE International Computer Performance and Dependability Symposium
DOI: 10.1109/IPDS.1998.707736 
Fast sequential circuit test generation using highlevel and gatelevel techniques
E. Rudnick, R. Vietti, A. Ellis, F. Corno, P. Prinetto, M. Sonza Reorda
DOI: 10.1109/DATE.1998.655915 
Faultlist collapsing for faultinjection experiments
A. Benso, M. Rebaudengo, L. Impagliazzo, P. Marmo
DOI: 10.1109/RAMS.1998.653808 
On the Identification of Optimal Cellular Automata for BuiltIn SelfTest of Sequential Circuits
P. Prinetto, M. Sonza Reorda, N. Gaudenzi, F. Corno
DOI: 10.1109/VTEST.1998.670902 
The Selfish Gene Algorithm: a New Evolutionary Optimization Strategy
F. Corno, M. Sonza Reorda, G. Squillero
Proceedings of the 1998 ACM symposium on Applied Computing
DOI: 10.1145/330560.330838 
The training environment for the course on microprocessor systems at the Politecnico di Torino
M. M. Rebaudengo
DOI: 10.1145/1275182.1275190 
VEGA: A Verification Tool Based on Genetic Algorithms
F. Corno, M. Sonza Reorda, G. Squillero
Proceedings the International Conference on Circuit Design 
A New Approach for Initialization Sequences Computation for Synchronous Sequential Circuits
F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, G. Squillero
1997 IEEE Proceedings of the International Conference on Computer Design 
A genetic algorithm for the computation of initialization sequences for synchronous sequential circuits
F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, G. Squillero
DOI: 10.1109/ATS.1997.643917
ABSTRACT: Testing circuits which do not include a global reset signal requires either complex ATPG algorithms based on 9 or even 256valued algebras, or some suitable method to generate initialization sequences. This paper follows the latter approach, and presents a new method to the automated generation of an initialization sequence for synchronous sequential circuits. We propose a Genetic Algorithm providing a sequence that aims at initializing the highest number of flip flops with the lowest number of vectors. The experimental results show that the approach is feasible to be applied even to the largest benchmark circuits and that it compares well to other known approaches in terms of initialized flip flops and sequence length. Finally, this paper shows how the initialization sequences can be fruitfully exploited by simplifying the ATPG process 
A new approach to build a lowlevel Malicious Fault List starting from Highlevel description and Alternative Graphs
A. Benso, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, R. Ubar 
Boolean function manipulation on a parallel system using BDDs
F. Bianchi, F. Corno, M. Rebaudengo, M. Sonza Reorda, R. Ansaloni
Lecture Notes in Computer Science (vol 1225)
DOI: 10.1007/BFb0031663
ABSTRACT: This paper describes a distributed algorithm for Boolean function manipulation. The algorithm is based on Binary Decision Diagrams (BDDs), which are one of the most commonly used data structures for representing and manipulating Boolean functions. A new distributed version of a BDD data structure and a distributed implementation of the basic operator for its manipulation are presented. The algorithm is suitable to work on a MIMD architecture and is based on a message passing masterslave paradigm. A package has been written, which uses the PVM library and is portable on different architectures. Two applications have been developed using the parallel BDD package. In both cases the results show that the new distributed version of the algorithm is able to manage BDDs much larger than the ones managed by monoprocessor tools 
Cellular automata for deterministic sequential test pattern generation
S. Chiusano, F. Corno, P. Prinetto, M. Sonza Reorda 
Exploiting Logic Simulation to Improve Simulationbased Sequential ATPG
F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, M. Violante
DOI: 10.1109/ATS.1997.643922 
Exploiting Symbolic Techniques within Genetic Algorithms for Power Optimization
S. Chiusano, F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda 
Exploiting highlevel descriptions for circuits fault tolerance assessment
A. Benso, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, J. Raik, R. Ubar
DOI: 10.1109/DFTVS.1997.628327 
GAbased Performance Analysis of Network Protocols
M. Baldi, F. Corno, M. Rebaudengo, M. Sonza Reorda, G. Squillero
9th IEEE Proceedings the International Conference on Tools with Artificial Intelligence
DOI: 10.1109/TAI.1997.632245
ABSTRACT: This paper tackles the problem of analyzing the correctness and performance of a computer network protocol. Given the complexity of the problem, no currently used technique is able to achieve good results: formal techniques can discover some bugs but can be applied to oversimplified models, only; on the other hand, statistical techniques relying on simulation often fail to find some critical cases for the protocol. Our proposed approach relies on coupling a genetic algorithm with a simulator of the system under verification. Genetic algorithms recently proved themselves excellent tools for giving good, yet approximate, solution to hardtosolve problems. To prove the effectiveness of our approach, we applied it to the quantitative verification of a network protocol: the complexity of this problem prevents the application of exact techniques, while experimental results show that the verification results we obtained are better than one can achieve with traditional statistical methods. As an example, the approach is applied to the verification of the TCP protocol operating on a given network. A genetic algorithm is able to find a configuration of the traffic over the network that sensitizes a critical problem in the TCP protocol 
Guaranteeing Testability in Reencoding for Low Power
S. Chiusano, F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda 
Hybrid SymbolicExplicit Techniques for the Graph Coloring Problem
S. Chiusano, F. Corno, P. Prinetto, M. Sonza Reorda 
New Static Compaction Techniques of Test Sequences for Sequential Circuits
F. Corno, M. Rebaudengo, P. Prinetto, M. Sonza Reorda 
Optimizing area loss in flat glass cutting
F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, S. Bisotto
DOI: 10.1049/cp:19971222 
SAARA: a simulated annealing algorithm for test pattern generation for digital circuits
F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
DOI: 10.1145/331697.331745 
SimulationBased Verification of Network Protocols Performance
M. Baldi, F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, G. Squillero
Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification
ABSTRACT: Formal verification techniques need to deal with the complexity of the systems being verified. Most often, this problem is solved by taking an abstract model of the system and aiming at a complete verification of an approximation of the system. This paper proposes a complementary verification approach, in which the approximation is introduced into the verification algorithm, instead of the system model: we achieve an approximate verification of a fairly complete and detailed system model. The proposed technique relies on coupling a Genetic Algorithm with a simulator of the system under verification, and is especially suited for verifying performancerelated aspects. To prove the effectiveness of our approach, we applied it to the quantitative verification of a network protocol: the TCP protocol operating on a given network. A Genetic Algorithm is able to find a configuration of the traffic over the network that sensitizes a critical problem in the TCP protocol that would be difficult to find both with exact techniques and stochastic ones 
Testability analysis and ATPG on behavioral RTlevel VHDL
F. Corno, P. Prinetto, M. Sonza Reorda
DOI: 10.1109/TEST.1997.639688 
A cellular genetic algorithm for the Floorplan area optimization problem on a SIMD architecture
S. Rebaudengo M.
Lecture Notes in Computer Science (vol 1067)
DOI: 10.1007/3540611428_675 
A genetic algorithm for automatic generation of test logic for digital circuits
F. Corno, P. Prinetto, M. Sonza Reorda
ICTAI 1996 : 8th IEEE International Conference on Tools with Artificial Intelligence, 1996
DOI: 10.1109/TAI.1996.560394
ABSTRACT: Testing is a key issue in the design and production of digital circuits: the adoption of BIST (Builtin SelfTest) techniques is increasingly popular, but sometimes requires efficient algorithms for the automatic generation of the logic which generates the test vectors applied to the unit under test. This paper addresses the issue of identifying a cellular automaton able to generate input patterns to detect stuckat faults inside a finite state machine (FSM). A suitable hardware structure is first identified. A genetic algorithm is then proposed, which directly identifies a cellular automaton able to reach a very good fault coverage of the stuckat faults. The novelty of the method consists in combining the generation of test patterns with the synthesis of a cellular automaton able to reproduce them. Experimental results are provided, which show that in most of the standard benchmark circuits the cellular automaton selected by the genetic algorithm is able to reach a fault coverage close to the maximum one. Our approach is the first attempt of exploiting evolutionary techniques for identifying the hardware for input pattern generation in BIST structures 
A parallel genetic algorithm for Automatic Generation of Test Sequences for digital circuits
F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
Lecture Notes in Computer Science (vol 1067)
DOI: 10.1007/3540611428_583
ABSTRACT: The paper deals with the problem of Automatic Generation of Test Sequences for digital circuits. Genetic Algorithms have been successfully proposed to solve this industrially critical problem; however, they have some drawbacks, e.g., they are often unable to detect some hard to test faults, and require a careful tuning of the algorithm parameters. In this paper, we describe a new parallel version of an existing GAbased ATPG, which exploits competing subpopulations to overcome these problems. The new approach has been implemented in the PVM environment and has been evaluated on a workstation network using some of the standard benchmark circuits. The results show that it is able to significantly improve the results quality (by testing some critical faults) at the expense of increased CPU time requirements 
Advanced Techniques for GAbased sequential ATPGs
F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, R. Mosca
DOI: 10.1109/EDTC.1996.494328 
Comparing topological, symbolic and GAbased ATPGs: an experimental approach
F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
DOI: 10.1109/TEST.1996.556941 
Exploiting competing subpopulations for automatic generation of test sequences for digital circuits
F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
Parallel Problem Solving from Nature — PPSN IV
DOI: 10.1007/354061723X_1042
ABSTRACT: The paper describes the application of a Parallel Genetic Algorithm to Automatic Test Pattern Generation (ATPG) for digital circuits. Genetic Algorithms have been already proposed to solve this industrially critical problem, both on mono and multiprocessor architectures. Although preliminary results are very encouraging, there are some obstacles which limit their use: in particular, GAs are often unable to detect some hard to test faults, and require a careful tuning of the algorithm parameters. In this paper, we describe a new parallel version of an existing GAbased ATPG, which exploits competing subpopulations to overcome these problems. The new approach has been implemented in the PVM environment and has been evaluated on a workstation network using standard benchmark circuits. Preliminary results show that it is able to improve the results quality (by testing additional critical faults) at the expense of increased CPU time requirements 
Fault Behavior Observation of a Microprocessor System through a VHDL SimulationBased Fault Injection Experiment
A. Amendola, A. Benso, F. Corno, L. Impagliazzo, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
DOI: 10.1109/EURDAC.1996.558255 
Fault Tolerant and BIST design of a FIFO cell
F. Corno, P. Prinetto, M. Sonza Reorda
EuroDAC '96: IEEE European Design Automation Conference with EuroVHDL '96 and Exhibition
DOI: 10.1109/EURDAC.1996.558210 
Online testing of an offtheshelf microprocessor board for safetycritical applications
F. Corno, M. Damiani, L. Impagliazzo, P. Prinetto, M. Rebaudengo, G. Sartore, M. Sonza Reorda
Lecture Notes in Computer Science (vol 1150)
DOI: 10.1007/3540617728_38
ABSTRACT: The paper describes the strategy adopted to implement online test procedures for a commercial microprocessor board used in an automated lightmetro control system. Special care has been devoted to chose the most effective test strategy for memory elements, processors, and caches, while guaranteeing a minimum impact on the normal behavior of the whole system. Implementation of the described techniques will significantly improve the system ability to safely react to possible faults. This will be quantitatively determined in the subsequent dependability evaluation phase 
Partial scan flip flop selection for simulationbased sequential ATPGs
F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
DOI: 10.1109/TEST.1996.557088 
Scan insertion criteria for low design impact
S. Barbagallo, M. Lobetti Bodoni, D. Medina, F. Corno, P. Prinetto, M. Sonza Reorda
VTS 1996 : IEEE VLSI Test Symposium
DOI: 10.1109/VTEST.1996.510831 
Selfchecking and Fault Tolerant approaches can help BIST fault coverage: a case study
F. Corno, P. Prinetto, M. Sonza Reorda
ED&TC 96: IEEE European Conference on Design and Test 1996
DOI: 10.1109/EDTC.1996.494374 
Using parallel genetic algorithms for solving the MinCut problem
G. Godza, M. Rebaudengo, M. Sonza Reorda
Lecture Notes in Computer Science (vol 1067)
DOI: 10.1007/3540611428_674 
A Data Parallel Algorithm for Boolean Function Manipulation
S. Gai, M. Rebaudengo, M. Sonza Reorda
DOI: 10.1109/FMPC.1995.380467 
A PVM tool for automatic test generation on parallel and distributed systems
F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, E. Veiluva
Lecture Notes in Computer Science (vol 919)
DOI: 10.1007/BFb0046607
ABSTRACT: The use of parallel architectures for the solution of CPU and memory critical problems in the Electronic CAD area has been limited up to now by several factors, like the lack of efficient algorithms, the reduced portability of the code, and the cost of hardware. However, portable messagepassing libraries are now available, and the same code runs on highcost supercomputers, as well as on common workstation networks. The paper presents an effective ATPG system for large sequential circuits developed using the PVM library and based on a Genetic Algorithm. The tool, named GATTO *, runs on a DEC Alpha AXP farm and a CM5. Experimental results are provided 
A portable ATPG tool for parallel and distributed systems
F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, E. Veiluva
DOI: 10.1109/VTEST.1995.512613 
An improved data parallel algorithm for Boolean function manipulation using BDDs
S. Gai, M. Rebaudengo, M. Sonza Reorda
DOI: 10.1109/EMPDP.1995.389132 
Exploiting massively parallel architectures for the solution of diffusion and propagation problems
P. Delsanto, S. Biancotto, M. Scalerandi, M. Rebaudengo, M. Sonza Reorda
Lecture Notes in Computer Science (vol 919)
DOI: 10.1007/BFb0046601
ABSTRACT: Many problems in several fields like physics, chemistry, biology and engineering lack an analytical solution able to provide a satisfactory phenomena description. Then a numerical solution becomes the only viable alternative. The use of massively parallel architectures often allows one to obtain in an easy way a comprehensive picture of the behaviour of the solution. We present here a computational model applied to two different physical problems; our work demonstrates the effectiveness of the approach and its extensibility to many classes of problems in different fields 
GARDA: a Diagnostic ATPG for Large Synchronous Sequential Circuits
F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
DOI: 10.1109/EDTC.1995.470385 
Improving topological ATPG with symbolic techniques
F. Corno, U. Gläser, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, T. Vierhaus
DOI: 10.1109/VTEST.1995.512658 
Testing a Switching Memory in a Telecommunication System
S. Barbagallo, F. Corno, P. Prinetto, M. Sonza Reorda
ITC 1995 : IEEE International Test Conference, 1995
DOI: 10.1109/TEST.1995.529941 
Using symbolic techniques to find the maximum clique in very large sparse graphs
F. Corno, P. Prinetto, M. Sonza Reorda
DOI: 10.1109/EDTC.1995.470377 
A Genetic Algorithm for Floorplan Area Optimization
M. Rebaudengo, M. Sonza Reorda
DOI: 10.1109/ICEC.1994.350035 
A data parallel approach to Boolean function manipulation using BDDs
G. Cabodi, S. Gai, M. Rebaudengo, M. Sonza Reorda
DOI: 10.1109/MPCS.1994.367081 
An automatic test pattern generator for large sequential circuits based on Genetic Algorithms
P. Prinetto, M. Rebaudengo, M. Sonza Reorda
DOI: 10.1109/TEST.1994.527955 
An experimental analysis of the effectiveness of the circular selftest path technique
P. Prinetto, F. Corno, M. Sonza Reorda
EURODAC '94: IEEE European design automation Conference
DOI: 10.1145/198174.198254 
An industrial experience in the builtin self test of embedded RAM
P. Camurati, P. Prinetto, M. Sonza Reorda, S. Barbagallo, A. Burri, D. Medina
VTS 1994 : IEEE 12th VLSI Test Symposium
DOI: 10.1109/VTEST.1994.292296 
Exploiting massively parallel architectures for the analysis of growth phenomena
P. Delsanto, G. Kaniadakis, M. Scalerandi, M. Rebaudengo, M. And Sonza Reorda 
Floorplan area optimization using genetic algorithms
M. Rebaudengo, M. Sonza Reorda
DOI: 10.1109/GLSV.1994.290002 
GATTO: an Intelligent Tool for Automatic Test Pattern Generation for Digital Circuits
P. Prinetto, M. Rebaudengo, M. Sonza Reorda, E. Veiluva
DOI: 10.1109/TAI.1994.346463 
Making the circular selftest path technique effective for real circuits
F. Corno, P. Prinetto, M. Sonza Reorda
ITC 1994 : IEEE International Test Conference, 1994
DOI: 10.1109/TEST.1994.528044 
Parallel processing analysis of the 1D KPZ growth equation
P. Delsanto, G. Kaniadakis, M. Scalerandi, M. Rebaudengo, M. And Sonza Reorda
Physics Computing 1994 
An experimental analysis of the effects of migration in parallel genetic algorithms
S. Rebaudengo M.
DOI: 10.1109/EMPDP.1993.336398 
Finding the Maximurn Clique in a Graph Using BDDs
F. Corno, P. Prinetto, M. Sonza Reorda
ICVC93: IEEE 3rd International Conference on VLSI and CAD 
Hybrid Genetic Algorithms for the Travelling Salesman Problem
P. Prinetto, M. Rebaudengo, M. Sonza Reorda
ICANNGA 1993: Artificial Neural Nets and Genetic Algorithms 
A new model for improving symbolic Product Machine traversal
G. Cabodi, P. Camurati, F. Corno, S. Gai, P. Prinetto, M. Sonza Reorda 
A simulationbased approach to test pattern generation for synchronous circuits
P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda
DOI: 10.1109/VTEST.1992.232763 
Boolean Function Manipulation on Massively Parallel Computers
G. Cabodi, S. Gai, M. Sonza Reorda
DOI: 10.1109/FMPC.1992.234869 
Centralized vs. distributed implementation of FSM equivalence verification on a parallel system
P. Camurati, P. Prinetto, M. Rebaudengo, Sonza Reorda M,
EWPC '92 : the European Workshops on Parallel Computing: from theory to sound practic
ABSTRACT: e 
Crossfertilizing FSM Verification Techniques and Sequential Diagnosis
G. Cabodi, P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda
Proceedings of the 1992 IEEE EURODAC 
Efficient Verification of Sequential Circuits on a Parallel System
P. Camurati, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
DOI: 10.1109/EDAC.1992.205895 
Improved techniques for multiple stuckat fault analysis using single stuckat fault test sets
P. Camurati, M. Rebaudengo, P. Prinetto, M. Sonza Reorda
DOI: 10.1109/ISCAS.1992.229933 
Sequential circuit diagnosis based on formal verification techniques
G. Cabodi, P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda
ITC 1992: IEEE International Test Conference 1992 
An Algebraic Approach to Test Generation for Sequential Circuits
A. Lioy, E. Macii, A. Meo, M. Sonza Reorda
DOI: 10.1109/GLSV.1991.143952 
An experimental comparison of different approaches to ROM BIST
S. Barbagallo, A. Burri, D. Medina, P. Camurati, P. Prinetto, M. Sonza Reorda
CompEuro'91: IEEE 5th Annual European Computer Conference on VLSI and Computers
DOI: 10.1109/CMPEUR.1991.257450 
Comparing ATPGs for synchronous sequential circuits
P. Camurati, M. Gilli, A. Meo, P. Prinetto, M. Sonza Reorda
CompEuro'91: IEEE 5th Annual European Computer Conference on VLSI and Computers
DOI: 10.1109/CMPEUR.1991.257386 
Fast Differential Fault Simulation by Dynamic Fault Ordering
G. Cabodi, S. Gai, M. Sonza Reorda 
Proving finite state machines correct with an automatonbased method
P. Camurati, M. Gilli, P. Prinetto, M. Sonza Reorda
IEEE First Great Lakes Symposium on VLSI
DOI: 10.1109/GLSV.1991.143975 
The Product Machine and Implicit Enumeration to prove FSMs correct
P. Camurati, M. Gilli, P. Prinetto, M. Sonza Reorda
Correct Hardware Design Methodologies 
The use of model checking in ATPG for sequential circuits
P. Camurati, M. Gilli, P. Prinetto, M. Sonza Reorda
Lecture Notes in Computer Science (vol 531)
DOI: 10.1007/BFb0023722
ABSTRACT: Some design environments may prevent Design for Testability techniques from reducing testing to a combinational problem: ATPG for sequential devices remains a challenging field. Random and deterministic structureoriented techniques are the stateoftheart, but there is a growing interest in methods where the function implemented by the circuit is known. This paper shows how a test pattern may be generated while trying to disprove the equivalence of a good and a faulty machine. The algorithms are derived from Graph Theory and Model Checking. An example is analyzed to discuss the applicability and the cost of such an approach 
A diagnostic test pattern generation algorithm
P. Camurati, D. Medina, P. Prinetto, M. Sonza Reorda
ITC 1990: IEEE International Test Conference 1990
DOI: 10.1109/TEST.1990.114000 
A new algorithm for diagnosisoriented automatic test pattern generation
P. Camurati, D. Medina, P. Prinetto, M. Sonza Reorda
EuroASIC 1990: IEEE EURO ASIC
DOI: 10.1109/EASIC.1990.207964 
Diagnosis Oriented Test Pattern Generation
P. Camurati, A. Lioy, P. Prinetto, M. Sonza Reorda
DOI: 10.1109/EDAC.1990.136693 
Model Checking and Graph Theory in sequential ATPG
P. Camurati, M. Gilli, P. Prinetto, M. Sonza Reorda
CAV 1990: Workshop on ComputerAided Verification 
Exact probabilistic testability measures for multioutput circuits
P. Camurati, P. Prinetto, Sonza Reorda M,
Robotic systems and AMT: IFIP TC5/WG5.3 International Conference on CAD/CAM and AMT, 1989 
Probabilistic Testability Analysis
P. Camurati, P. Prinetto, Sonza Reorda M,
CAD&CG 1989: International Conference on ComputerAided Design & Computer Graphics 
Testability measures with concurrent good simulation
Cabodi G.P, P. Camurati, P. Prinetto, M. Sonza Reorda
ETC'89: IEEE 1st European Test Conference
DOI: 10.1109/ETC.1989.36236 
Random Testability Analysis: comparing and evaluating existing approaches
P. Camurati, P. Prinetto, M. Sonza Reorda
DOI: 10.1109/ICCD.1988.25662