Publications

  1. A Genetic Algorithm-based System for Generating Test Programs for Microprocessor IP Cores
    F. Corno, M. Sonza Reorda, G. Squillero, M. Violante
    ICTAI2000: The Twelfth IEEE International Conference on Tools with Artificial Intelligence, Vancouver, British Columbia, Canada, November 13-15, 2000, pp. 195-198

  2. An Intelligent User Interface oriented to non-expert users
    F. Corno, L. Farinetti, G. Squillero
    World Conference on the WWW and Internet

  3. An RT-level Fault Model with High Gate Level Correlation
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    Proceedings of the IEEE International High-Level Validation and Test Workshop (HLDVT'00)

  4. An experimental evaluation of the effectiveness of automatic rule-based transformations for safety-critical applications
    M. Rebaudengo, M. Sonza Reorda, M. Torchiano, M. Violante
    DOI: 10.1109/DFTVS.2000.887164

  5. An improved cellular automata-based BIST architecture for sequential circuits
    F. Corno, M. Sonza Reorda, G. Squillero
    DOI: 10.1109/ISCAS.2000.857030
    ABSTRACT: C2BIST (Circular CA BlST) is a Built-In Self Test (BIST) architecture for sequential circuits based on Cellular Automata (CA). When CA cells implement suitable rules, this structure shows good test generation capabilities, reaching high fault coverage. The main characteristic of this approach is that the same CA is used for both generation and compaction, leading to a trade-off between attained fault coverage and area overhead more favorable than other BIST approaches. On the other hand, the main problem is that the circuit, during the test phase, may enter a loop early, reducing the attained fault coverage. The paper analyzes this problem and proposes a solution based on the partial reset technique, that is able to break cycles by exploiting the circuit flip-flops synchronous reset signal with a small area overhead with respect to the basic C2BIST architecture. Experimental results allow a quantitative evaluation of the effectiveness of this approach

  6. Archivi on-line fruibili da utenti inesperti: un'esperienza nel campo della disabilità
    F. Corno, G. Squillero
    Convegno AICA sull'Informatica per la Didattica

  7. Automatic Test Bench Generation for Simulation-based Validation
    M. Lajolo, L. Lavagno, M. Rebaudengo, M. Sonza Reorda, M. Violante

  8. Automatic Validation of Protocol Interfaces Described in VHDL
    F. Corno, M. Sonza Reorda, G. Squillero
    Real-World Applications of Evolutionary Computing
    DOI: 10.1007/3-540-45561-2_20
    ABSTRACT: In present days, most of the design activity is performed at a high level of abstraction, thus designers need to be sure that their designs are syntactically and semantically correct before starting the automatic synthesis process. The goal of this paper is to propose an automatic input pattern generation tool able to assist designers in the generation of a test bench for difficult parts of small- or medium- sized digital protocol interfaces. The proposed approach exploit a Genetic Algorithm connected to a commercial simulator for cultivating a set of input sequence able to execute given statements in the interface description. The proposed approach has been evaluated on the new ITC'99 benchmark set, a collection of circuits offering a wide spectrum of complexity. Experimental results show that some portions of the circuits remained uncovered, and the subsequent manual analysis allowed identifying design redundancies

  9. Automatic test bench generation for validation of RT-level descriptions: an industrial experience
    F. Corno, A. Manzone, A. Pincetti, M. Sonza Reorda, G. Squillero
    DOI: 10.1145/343647.343802
    ABSTRACT: In current microprocessors and systems, an increasingly high silicon portion is derived through automatic synthesis with designers working exclusively at the RT-level, and design productivity is greatly enhanced. However, in the new design flow, validation still remains a challenge: while new technologies based on formal verification are only marginally accepted, standard techniques based on simulation are beginning to fall behind the increased circuit complexity. This paper proposes a new approach to simulation-based validation, in which a genetic algorithm helps the designer in generating useful input sequences to be included in the test bench. The technique has been applied to an industrial circuit, showing that the quality of the validation process is increased

  10. Behavioral-level test vector generation for system-on-chip designs
    M. Lajolo, M. Rebaudengo, M. Sonza-Reorda, M. Violante, L. Lavagno
    Proceedings IEEE International High-Level Design Validation and Test Workshop

  11. CA-CSTP: A new BIST Architecture for Sequential Circuit
    F. Corno, M. Sonza Reorda, G. Squillero, M. Violante
    Proceedings of the IEEE European Test Workshop

  12. Early Power Estimation for System-on-Chip Designs
    M. Lajolo, L. Lavagno, M. Sonza Reorda, M. Violante
    Integrated Circuit Design
    DOI: 10.1007/3-540-45373-3_11
    ABSTRACT: Reduction of chip packaging and cooling costs for deep sub-micron System-On-Chip (SOC) designs is an emerging issue. We present a simulationbased methodology able to realistically model the complex environment in which a SOC design operates in order to provide early and accurate power consumption estimation. We show that a rich functional test bench provided by a designer with a deep knowledge of a complex system is very often not appropriate for power analysis and can lead to power estimation errors of some orders of magnitude. To address this issue, we propose an automatic input sequence generation approach based on a heuristic algorithm able to upgrade a set of test vectors provided by the designer. The obtained sequence closely reflects the worst-case power consumption for the chip and allows looking at how the chip is going to work over time

  13. Evaluating system dependability in a co-design framework
    M. Lajolo, M. Rebaudengo, M. Sonza-Reorda, M. Violante, L. Lavagno
    Proceedings IEEE Design Automation and Test in Europe Conference

  14. Evaluating the effectiveness of a Software Fault-Tolerance technique on RISC- and CISC-based architectures
    M. Rebaudengo, M. Sonza Reorda, M. Violante, P. Cheynet, B. Nicolescu, R. Velazco
    DOI: 10.1109/OLT.2000.856606

  15. Evolving Cellular Automata for Self-Testing Hardware
    F. Corno, M. Sonza Reorda, G. Squillero
    Evolvable Systems: From Biology to Hardware
    DOI: 10.1007/3-540-46406-9_4
    ABSTRACT: Testing is a key issue in the design and production of digital circuits: the adoption of BIST (Built-In Self-Test) techniques is increasingly popular, but requires efficient algorithms for the generation of the logic which generates the test vectors applied to the Unit Under Test. This paper addresses the issue of identifying a Cellular Automaton able to generate input patterns to detect stuckat faults inside a Finite State Machine (FSM) circuit. Previous results already proposed a solution based on a Genetic Algorithm which directly identifies a Cellular Automaton able to reach good Fault Coverage of the stuck-at faults. However, such method requires 2-bit cells in the Cellular Automaton, thus resulting in a high area overhead. This paper presents a new solution, with an area occupation limited to 1 bit per cell; the improved results are possible due to the adoption of a new optimization algorithm, the Selfish Gene algorithm. Experimental results are provided, which show that in most of the standard benchmark circuits the Cellular Automaton selected by the Selfish Gene algorithm is able to reach a Fault Coverage higher that what can be obtained with current engineering practice with comparable area occupation

  16. Exploiting the selfish gene algorithm for evolving cellular automata
    F. Corno, M. Sonza Reorda, G. Squillero
    DOI: 10.1109/IJCNN.2000.859457
    ABSTRACT: This paper shows an application in the field of Electronic CAD of the Selfish Gene algorithm, an evolutionary algorithm based on a recent interpretation of the Darwinian theory. Testing is a key issue in the design and production of digital circuits and the adoption of Built-In Self-Test (BIST) techniques is increasingly popular. In this paper, the Selfish Gene algorithm is adopted for determining the logic for a BIST architecture based on Cellular Automata (CA). A Genetic Algorithm has already been proposed for identifying good BIST architectures based on CA. However, by adopting 2-bit cells, such a method introduced a significant area overhead. Thanks to the adoption of the new and more powerful search engine, we were able to identify simpler BIST structures with a lower area overhead, but still able to obtain the same fault coverage

  17. High-Level Observability for Effective High-Level ATPG
    F. Corno, M. Sonza Reorda, G. Squillero
    VTS2000: 18th IEEE VLSI Test Symposium, Montreal, Canada, May 2000, pp. 411-416

  18. Low Power BIST via Hybrid Cellular Automata
    F. Corno, M. Rebaudengo, M. Sonza Reorda, G. Squillero, M. Violante
    VTS2000: 18th IEEE VLSI Test Symposium, Montreal, Canada, May 2000, pp. 29-34

  19. Low Power BIST via Non-Linear Hybrid Cellular Automata
    F. Corno, M. Rebaudengo, M. Sonza Reorda, G. Squillero, M. Violante
    Proceedings of the 18th IEEE VLSI Test Symposium (VTS'00)

  20. New Techniques for Accelerating Fault Injection in VHDL descriptions
    B. Parrotta, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DOI: 10.1109/OLT.2000.856613

  21. Prediction of Power Requirements for High-Speed Circuits
    F. Corno, M. Rebaudengo, M. Sonza Reorda, M. Violante
    Real-World Applications of Evolutionary Computing
    DOI: 10.1007/3-540-45561-2_24
    ABSTRACT: Modern VLSI design methodologies and manufacturing technologies are making circuits increasingly fast. The quest for higher circuit performance and integration density stems from fields such as the telecommunication one where high speed and capability of dealing with large data sets is mandatory. The design of high-speed circuits is a challenging task, and can be carried out only if designers can exploit suitable CAD tools. Among the several aspects of high-speed circuit design, controlling power consumption is today a major issue for ensuring that circuits can operate at full speed without damages. In particular, tools for fast and accurate estimation of power consumption of highspeed circuits are required. In this paper we focus on the problem of predicting the maximum power consumption of sequential circuits. We formulate the problem as a constrained optimization problem, and solve it resorting to an evolutionary algorithm. Moreover, we empirically assess the effectiveness of our problem formulation with respect to the classical unconstrained formulation. Finally, we report experimental results assessing the effectiveness of the prototypical tool we implemented

  22. RT-level Fault Simulation Techniques based on Simulation Command Scripts
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    DCIS2000: XV Conference on Design of Circuits and Integrated Systems, Le Corum, Montpellier, November 21-24, 2000, pp. 825-830

  23. Speeding-up Fault Injection Campaigns in VHDL models
    B. Parrotta, M. Rebaudengo, M. Sonza Reorda, M. Violante
    Lecture Notes in Computer Science (vol 1943)
    DOI: 10.1007/3-540-40891-6_3
    ABSTRACT: Simulation-based Fault Injection in VHDL descriptions is increasingly common due to the popularity of top-down design flows exploiting this language. This paper presents some techniques for reducing the time to perform the required simulation experiments. Static and dynamic methods are proposed to analyze the list of faults to be injected, removing faults as soon as their behavior is known. Common features available in most VHDL simulation environments are also exploited. Experimental results show that the proposed techniques are able to reduce the time required by a typical Fault Injection campaign by a factor ranging from 43.9% to 96.6%

  24. System-level test bench generation in a co-design framework
    M. Lajolo, M. Rebaudengo, M. Sonza-Reorda, M. Violante, L. Lavagno
    Proceedings IEEE European Test Workshop