Publications

  1. A P1500 compliant BIST-based approach to embedded RAM diagnosis
    D. Appello, F. Corno, M. Giovinetto, M. Rebaudengo, M. Sonza Reorda

  2. A genetic algorithm for the computation of initialization sequences for synchronous sequential circuits
    F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, G. Squillero
    10th anniversary compendium of papers from Asian Test Symposium : proceedings : 1992-2001
    DOI: 10.1109/ATS.2001.10066
    ABSTRACT: [Riedizione] Testing circuits which do not include a global reset signal requires either complex ATPG algorithms based on 9- or even 256-valued algebras, or some suitable method to generate initialization sequences. This paper follows the latter approach, and presents a new method to the automated generation of an initialization sequence for synchronous sequential circuits. We propose a Genetic Algorithm providing a sequence that aims at initializing the highest number of flip flops with the lowest number of vectors. The experimental results show that the approach is feasible to be applied even to the largest benchmark circuits and that it compares well to other known approaches in terms of initialized flip flops and sequence length. Finally, this paper shows how the initialization sequences can be fruitfully exploited by simplifying the ATPG process

  3. A source-to-source compiler for generating dependable software
    M. Rebaudengo, M. Sonza Reorda, M. Torchiano, M. Violante
    Proc. First IEEE International Workshop on Source Code Analysis and Manipulation, SCAM
    DOI: 10.1109/SCAM.2001.972664
    ABSTRACT: Over the last years, an increasing number of safety-critical tasks have been demanded for computer systems. In particular, safety-critical computer-based applications are hitting market areas where cost is a major issue, and thus solutions are required which conjugate fault tolerance with low costs. A source-to-source compiler supporting a software-implemented hardware fault tolerance approach is proposed, based on a set of source code transformation rules. The proposed approach hardens a program against transient memory errors by introducing software redundancy: every computation is performed twice and results are compared, and control flow invariants are checked explicitly. By exploiting the tool's capabilities, several benchmark applications have been hardened against transient errors. Fault injection campaigns have been performed to evaluate the fault detection capability of the hardened applications. In addition, we analyzed the proposed approach in terms of space and time overheads

  4. ARPIA: a High-Level Evolutionary Test Signal Generator
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    Applications of Evolutionary Computing
    DOI: 10.1007/3-540-45365-2_31
    ABSTRACT: The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective fault models and test signals generators are still missing. This paper proposes ARPIA, a new simulation-based evolutionary test generator. ARPIA adopts an innovative high-level fault model that enables efficient fault simulation and guarantees good correlation with gate-level results. The approach exploits an evolutionary algorithm to drive the search of effective patterns within the gigantic space of all possible signal sequences. ARPIA operates on register-transfer level VHDL descriptions and generates effective test patterns. Experimental results show that the achieved results are comparable or better than those obtained by high-level similar approaches or even by gate-level ones

  5. An Interpretation Framework for Evaluating High-Level Fault Models and ATPG Capabilities
    F. Corno, M. Sonza Reorda, G. Squillero

  6. Coping with SEUs/SETs in microprocessors by means of low-cost solutions: a comparison study
    M. Rebaudengo, M. Sonza Reorda, M. Violante, B. Nicolescu, R. Velasco
    DOI: 10.1109/RADECS.2001.1159312

  7. Devising an RT-Level ATPG for uProcessor Cores
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    WRTLT2001: 2nd Worshop on RTL, ATPG & DFT

  8. Effective Techniques for High-Level ATPG
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    Proceedings of the 10th Asian Test Symposium

  9. Evolving Effective CA/CSTP BIST Architectures for Sequential Circuits
    F. Corno, M. Sonza Reorda, G. Squillero
    Proceedings of the 2001 ACM symposium on Applied computing
    DOI: 10.1145/372202.372361

  10. Exploiting FPGA for accelerating Fault Injection Experiments
    P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante

  11. Exploiting FPGA-based Techniques for Fault Injection Campaigns on VLSI Circuits
    P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante

  12. FPGA-based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits
    P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante
    Lecture Notes in Computer Science (vol 2147)
    DOI: 10.1007/3-540-44687-7_51
    ABSTRACT: Designers of safety-critical VLSI systems are asking for effective tools for evaluating and validating their designs. Fault Injection is commonly adopted for this task, and its effectiveness is therefore a key factor. In this paper we propose to exploit FPGAs to speed-up Fault Injection for fault tolerance evaluation of VLSI circuits. A complete Fault Injection environment is described, relying on FPGA-based emulation of the circuit for fault effect analysis. The proposed approach allows combining the efficiency of hardware-based techniques, and the flexibility of simulation-based techniques. Experimental results are provided to support the feasibility and effectiveness of the approach. The work is partially funded by the Italian Ministry for University through the project "Sistemi di elaborazione reattivi ed affidabili per applicazioni industriali", the Italian Space Agency through the basic research project "Definizione e valutazione di tecniche software per la realizzazione di sistemi di elaborazione tolleranti ai guasti a basso costo", and by Politecnico di Torino through the Giovani Ricercatori project

  13. FPGA-based Fault Injection for Microprocessor Systems
    P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante

  14. On the Test of Microprocessor IP Cores
    F. Corno, M. Sonza Reorda, M. Violante, G. Squillero
    Proceedings of the conference on Design, automation and test in Europe

  15. System Safety through Automatic High-level Code Transformations: an Experimental Evaluation
    M. Rebaudengo, M. Sonza Reorda, M. Violante, P. Cheynet, B. Nicolescu, R. Velazco