Publications

  1. A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques
    D. Appello, A. Fudoli, V. Tancorre, F. Corno, M. Rebaudengo, M. Sonza Reorda

  2. A Hierarchical Approach for Designing Dependable Systems
    M. Sonza Reorda, M. Violante, N. Mazzocca, S. Venticinque, A. Bobbio, G. Franceschinis

  3. A New Methodology for Debugging Embedded Cores
    D. Appello, L. Bouzaida, A. Fudoli, R. Mattiuzzo, R. Kapur, M. Rebaudengo, M. Sonza Reorda

  4. A Software Fault Tolerance Method for Safety-Critical Systems: Effectiveness and Drawbacks
    B. Nicolescu, R. Velazco, M. Sonza Reorda, M. Rebaudengo, M. Violante

  5. A Transparent Search Agent for Closed Collections
    F. Bota, F. Corno, L. Farinetti, G. Squillero

  6. A new approach to software-implemented fault tolerance
    M. Rebaudengo, M. Sonza Reorda, M. Violante

  7. A new functional fault model for FPGA Application-Oriented testing
    M. Rebaudengo, M. Sonza Reorda, M. Violante

  8. A simplified gate-level fault model for crosstalk effects analysis
    P. Civera, L. Macchiarulo, M. Violante
    Proceedings. 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002
    DOI: 10.1109/DFTVS.2002.1173499

  9. An Evolutionary Algorithm for Reducing Integrated-Circuit Test Application Time
    F. Corno, M. Sonza Reorda, G. Squillero
    Proceedings of the 2002 ACM symposium on Applied computing
    DOI: 10.1145/508791.508908

  10. An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation
    L. Berrojo, F. Corno, L. Entrena, I. Gonzlez, C. Lopez, M. Sonza Reorda, G. Squillero

  11. Analysis of SEU effects in a pipelined processor
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    DOI: 10.1109/OLT.2002.1030193
    ABSTRACT: Modern processors embed features such as pipelined execution units and cache memories that can hardly be controlled by programmers through the processor instruction set. As a result, software-based fault injection approaches are no longer suitable for assessing the effects of SEUs in modern processors, since they are not able to evaluate the effects of SEUs affecting pipelines and caches. In this paper we report an analysis of a commercial processor core where the effects of SEUs located in the processor pipeline and cache memories are studied. Moreover the obtained results are compared with those software-based approaches provide. Experimental results show that software-based approaches may lead to errors during the failure rate estimation of up to 400%

  12. Analysis of the Equivalences and Dominances of Transient Faults at the Register-Transfer Level
    L. Errojo, I. Gonzlez, F. Corno, M. Sonza Reorda, G. Squillero, L. Entrena, C. Lopez
    Proceedings of the Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02)

  13. Automatic Test Program Generation from RT-level MicroprocessorDescriptions
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero

  14. Efficient Machine-Code Test-Program Induction
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero

  15. Evolutionary Techniques for Minimizing Test Signals Application Time
    F. Corno, M. Sonza Reorda, G. Squillero
    Lecture Notes in Computer Science (vol 2279)
    DOI: 10.1007/3-540-46004-7_19
    ABSTRACT: Reducing production-test application time is a key problem for modern industries. Several different hardware solutions have been proposed in the literature to ease such process. However, each hardware architecture must be coupled with an effective test signals generation algorithm. This paper propose an evolutionary approach for minimizing the application time of a test set by opportunely extending it and exploiting a new hardware architecture, named interleaved scan. The peculiarities of the problem suggest the use of a slightly modified genetic algorithm with concurrent populations. Experimental results show the effectiveness of the approach against the traditional ones

  16. Evolutionary Test Program Induction for Microprocessor Design Verification
    F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero
    Proceedings of the 11th Asian Test Symposium

  17. Fault list compaction through static timing analysis for efficient fault injection experiments
    V. Sonza Reorda M.
    DOI: 10.1109/DFTVS.2002.1173523

  18. High-level and hierarchical test sequence generation
    G. Jervan, Z. Peng, O. Goloubeva, M. Sonza Reorda, M. Violante
    DOI: 10.1109/HLDVT.2002.1224448

  19. New Techniques for Speeding-up Fault-injection Campaigns
    L. Berrojo, I. Gonzlez, F. Corno, M. Sonza Reorda, G. Squillero, L. Entrena, C. Lopez
    Proceedings of the conference on Design, automation and test in Europe

  20. Reducing Test Application Time through Interleaved Scan
    F. Corno, M. Sonza Reorda, G. Squillero
    Proceedings of the 15th symposium on Integrated circuits and systems design

  21. Simulation-based analysis of SEU effects on SRAM-based FPGAs
    M. Rebaudengo, M. Sonza Reorda, M. Violante

  22. Simulation-based analysis of SEU effects on SRAM-based FPGAs
    M. Rebaudengo, M. Sonza Reorda, M. Violante
    Lecture Notes in Computer Science (vol 2438)
    DOI: 10.1007/3-540-46117-5_63