Publications

  1. A Local Analysis of the Genotype-Fitness Mapping in Hardware Optimization Problems
    E. Sanchez, G. Squillero, M. Violante
    DOI: 10.1109/CEC.2004.1330952

  2. A multi-level approach to the dependability analysis of CAN networks for automotive applications
    F. Corno, J. Perez, M. Ramasso, M. Sonza Reorda, M. Violante

  3. A multi-level approach to the dependability analysis of networked systems based on the CAN protocol
    F. Corno, J. Perez, M. Sonza Reorda, M. Violante

  4. An Infrastructure IP for Soft Error Detection
    L. Bolzani, M. Rebaudengo, M. Sonza Reorda, F. Vargas, M. Violante

  5. Approaching production diagnostic for BIST-based testing
    D. Appello, P. Bernardi, D. Chindamo, M. Rebaudengo, M. Sonza Reorda, V. Tancorre

  6. Automatic Generation of Validation Stimuli for Application-Specific Processors
    O. Goloubeva, M. Sonza Reorda, M. Violante
    DOI: 10.1109/DATE.2004.1268847

  7. Automatic Test Programs Generation Driven by Internal Performance Counters
    W. Lindsay, E. Sanchez, M. Sonza Reorda, G. Squillero
    Proceedings of the Fifth International Workshop on Microprocessor Test and Verification
    DOI: 10.1109/MTV.2004.5

  8. Automatic Verification of RT-Level Microprocessor Cores Using Behavioral Specifications: a Case Study
    L. Anghel, E. Sanchez, M. Sonza Reorda, G. Squillero, R. Velazco

  9. Automatic generation of validation stimuli for application-specific processors
    O. Goloubeva, M. Sonza Reorda, M. Violante
    DOI: 10.1109/DATE.2004.1268847

  10. Cerberus I-IP: an HW/SW approach to Control Flow Checking
    P. Bernardi, L. Bolzani, M. Rebaudengo, M. Sonza Reorda, F. Vargas, M. Violante

  11. Coupling different methodologies to validate obsolete microprocessors
    L. Anghel, E. Sanchez, M. Sonza Reorda, G. Squillero, R. Velazco
    Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium on (DFT'04)
    DOI: 10.1109/DFTVS.2004.1347846

  12. Dynamic Optimization of Semantic Annotation Relevance
    D. Bonino, F. Corno, G. Squillero
    Proceedings of CEC2004, Congress on Evolutionary Computation

  13. Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA
    M. Bellato, P. Bernardi, D. Bortolato, A. Candelori, M. Ceschia, A. Paccagnella, M. Rebaudengo, M. Sonza Reorda, M. Violante, P. Zambolin
    DOI: 10.1109/DATE.2004.1268908

  14. Evaluating the effects of transient faults on vehicle dynamic performance in automotive systems
    F. Corno, F. Esposito, M. Sonza Reorda, S. Tosato

  15. Exploiting HW Acceleration for Classifying Complex Test Program Generation Problems
    E. Sanchez, G. Squillero, M. Violante
    Lecture Notes in Computer Science (vol 3005)
    DOI: 10.1007/978-3-540-24653-4_24

  16. Exploiting an I-IP for In-field SOC test
    P. Bernardi, M. Rebaudengo, M. Sonza Reorda
    DOI: 10.1109/DFTVS.2004.1347865

  17. Hybrid Soft Error Detection by means of Infrastructure IP cores
    L. Bolzani, M. Rebaudengo, M. Sonza Reorda, F. Vargas, M. Violante

  18. On the diagnosis of embedded memory cores through Programmable BIST
    D. Appello, P. Bernardi, M. Rebaudengo, M. Sonza Reorda, V. Tancorre

  19. On the evaluation of SEU sensitiveness in SRAM-based FPGAs
    P. Bernardi, M. Sonza Reorda, L. Sterpone, M. Violante

  20. On the evolution of corewar warriors
    F. Corno, E. Sanchez, G. Squillero
    DOI: 10.1109/CEC.2004.1330848

  21. On-line Analysis and Perturbation of CAN Networks
    M. Sonza Reorda, M. Violante
    DOI: 10.1109/DFTVS.2004.1347867

  22. Using Infrastructure IPs to support SW-based Self-Test of Processor Cores
    P. Bernardi, M. Rebaudengo, M. Sonza Reorda

  23. Validation of the dependability of CAN-based networked systems
    F. Corno, J. Perez, M. Ramasso, M. Sonza Reorda, M. Violante
    DOI: 10.1109/HLDVT.2004.1431262