Publications

  1. A Tool for Supporting and Automating the Test of Complex System-on-Chips
    P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda, D. Appello, R. Mattiuzzo, V. Tancorre

  2. A design flow for protecting FPGA-based systems against single event upsets
    L. Sterpone, M. Violante
    DOI: 10.1109/DFTVS.2005.5

  3. A modular Architecture for a Populationless Evolutionary Algorithm for MIP
    E. Sanchez, M. Schillaci, G. Squillero

  4. A new DFM-proactive technique
    D. Appello, P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda, V. Tancorre

  5. An I-IP for the Debug of Microprocessor Cores
    D. Appello, M. Grosso, M. Rebaudengo, M. Sonza Reorda

  6. An experimental analysis of hardening techniques for SRAM-based FPGAs
    L. Sterpone, S. Rezgui, M. Violante
    DOI: 10.1109/RADECS.2005.4365639

  7. An experimental analysis of hardening techniques for SRAM-based FPGAs
    L. Sterpone, M. Violante, S. Rezgui
    8th IEEE European Conference on Radiation and Its Effects on Component and Systems

  8. An integrated approach for increasing the soft-error detection capabilities in SoCs processors
    P. Bernardi, L. Bolzani, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DOI: 10.1109/DFTVS.2005.17

  9. Automatic Completion and Refinement of Verification Sets for Microprocessor Cores
    E. Sanchez, G. Squillero, M. Sonza Reorda
    LECTURE NOTES IN COMPUTER SCIENCE
    DOI: 10.110.1007/978-3-540-32003-6_21007/b106856
    ABSTRACT: In the design cycle of a microprocessor core, the unit is usually refined through a series of subsequent steps. To deliver a flaw free unit at the end of the process, in each stage a verification step is required. While it would be useful to automatically develop the set of test programs for verification concurrently to the design, in most of the existing approach verification is performed manually and starting from scratch. This paper presented a methodology for the automatic completion and refinement of existing verification programs. It shows a new technique for allowing a Genetic Programming-based framework to import an existing test-program set and assimilate it for further test generation. A case study is considered, in which a sample pipelined processor is used, and new test programs are generated starting from existing functional ones. Different metrics are targeted, and preliminary results are reported, showing the effectiveness of the method with respect to a pure random approach

  10. Automatic Generation of Test Sets for SBST of Microprocessor IP Cores
    E. Sanchez, M. Sonza Reorda, G. Squillero, M. Violante
    DOI: 10.1145/1081081.1081105

  11. Automatic completion and refinement of verification sets for microprocessor cores
    E. Sánchez, M. Sonza Reorda, G. Squillero
    DOI: 10.1007/978-3-540-32003-6_21

  12. Diagnosing faulty functional units in processors by using automatically generated test sets
    P. Bernardi, E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero
    DOI: 10.1109/MTV.2005.10
    ABSTRACT: Microprocessor technology is increasingly used for many applications; the large market volumes call for cost containment in the production phase. Process yield for processor production is, however, far from ideal. To increase it fault diagnosis is an important means, since it can allow both process characterization and product repair by the usage of backup resources. This paper presents a novel methodology to discriminate faulty modules, rather than gates, in a microprocessor based on the automatic construction of diagnostic software-based test sets. The approach exploits a post-production test set, designed for software-based self-test, and an infrastructure IP to perform the diagnosis. An initial diagnostic test set is built, and then iteratively refined resorting to an evolutionary method. Experimental results are reported in the paper showing the feasibility and effectiveness of the approach for an Intel i8051 processor core

  13. Efficient estimation of SEU effects in SRAM-based FPGAs
    M. Sonza Reorda, L. Sterpone, M. Violante
    DOI: 10.1109/IOLTS.2005.26

  14. Exploiting an I-IP for both test and silicon debug of microprocessor cores
    P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda
    Microprocessor Test and Verification, 2005. MTV '05. Sixth International Workshop on
    DOI: 10.1109/MTV.2005.11

  15. Exploiting an Infrastructure-IP to reduce memory diagnosis costs in SoCs
    P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda
    Test Symposium, 2005. European
    DOI: 10.1109/ETS.2005.23

  16. Improved Software-Based Processor Control-Flow Errors Detection Technique
    O. Goloubeva, M. Rebaudengo, M. Sonza Reorda, M. Violante
    DOI: 10.1109/RAMS.2005.1408426

  17. Integrating BIST techniques for on-line SoC testing
    P. Bernardi, M. Grosso, A. Manzone, M. Rebaudengo, E. Sanchez, M. Sonza Reorda
    On-Line Testing Symposium, 2005. IOLTS 2005. 11th IEEE International
    DOI: 10.1109/IOLTS.2005.38

  18. Multiple errors produced by single upsets in FPGA configuration memory: a possible solution
    M. Sonza Reorda, L. Sterpone, M. Violante
    DOI: 10.1109/ETS.2005.29

  19. New Evolutionary Techniques for Test-Program Generation for Complex Microprocessor Cores
    E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero, L. Sterpone, M. Violante
    Proceedings of the 2005 conference on Genetic and evolutionary computation
    DOI: 10.1145/1068009.1068370

  20. On the diagnosis of SoCs including multiple memory cores
    P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda
    Design and Diagnostics of Electronic Circuits and Systems. IEEE Workshop on
    DOI: 10.1109/DDECS.2006.1649622

  21. On the optimal design of triple modular redundancy logic for SRAM-based FPGAs
    F. Kastensmidt, L. Sterpone, M. Sonza Reorda, L. Carro
    DOI: 10.1109/DATE.2005.229

  22. On the transformation of manufacturing test sets into on-line test sets for microprocessors
    E. Sanchez, Reorda M.S, G. Squillero
    roceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)
    DOI: 10.1109/DFTVS.2005.53

  23. On-line Detection of Control-Flow Errors in SoCs by means of an Infrastructure IP core
    P. Bernardi, L. Bolzani, M. Rebaudengo, M. Sonza Reorda, F. Vargas, M. Violante
    DOI: 10.1109/DSN.2005.74

  24. Pandora I-IP: an HW/SW approach to Control Flow Checking
    P. Bernardi, L. Bolzani, M. Rebaudengo, M. Sonza Reorda, F. Vargas, M. Violante

  25. RoRA: a reliability-oriented place and route algorithm for SRAM-based FPGAs
    L. Sterpone, M. Sonza Reorda, M. Violante
    Research in Microelectronics and Electronics
    DOI: 10.1109/RME.2005.1543031

  26. Testing logic cores using a BIST P1500 compliant approach: a case of study
    P. Bernardi, G. Masera, F. Quaglio, M. Sonza Reorda
    Proceedings of DATE2005
    DOI: 10.1109/DATE.2005.305