Publications

  1. A Hybrid Approach to Fault Detection and Correction in SoCs
    P. Bernardi, L. Bolzani, M. Sonza Reorda

  2. A Software-based Methodology for the Generation of Peripheral Test Sets Based on High-level Descriptions
    L. Bolzani, E. Sanchez, M. Sonza Reorda
    Proceedings of the 20th annual conference on Integrated circuits and systems design

  3. A local analysis of an incremental evolutionary tool for processor diagnosis
    D. Ravotto, E. Sanchez, M. Schillaci, G. Squillero
    DOI: 10.1109/CEC.2007.4424921
    ABSTRACT: This paper details an evolutionary tool targeted at increasing the diagnostic power of a set of assembly programs. The underlying evolutionary scheme is quite peculiar in some aspect and present interesting characteristics The effectiveness of the generated set has recently been demonstrated. Here the use of the tool is further motivated through a deep experimental analysis that provides insight on the obtainable results and better explains the design choices. The use of the tool is validated against a widely used microprocessor core and results are provided

  4. A new FPGA-based edge detection system for the gridding of DNA microarray images
    L. Sterpone, M. Violante

  5. A new decompression system for the configuration process of SRAM-based FPGAs
    L. Sterpone, M. Violante

  6. A new hardware architecture for performing the gridding of DNA microarray images
    L. Sterpone, M. Violante

  7. A new hardware/software platform for the soft-error sensitivity evaluation of FPGA devices
    M. Violante, M. Sonza Reorda, L. Sterpone, A. Manuzzato, S. Gerardin, P. Rech, M. Bagatin, A. Paccagnella, C. Andreani, G. Gorini, A. Pietropaolo, G. Cardarilli, A. Salsano, S. Pontarelli, C. Frost

  8. A new mitigation approach for soft errors in embedded processors
    F. Abate, L. Sterpone, M. Violante
    DOI: 10.1109/RADECS.2007.5205504

  9. Agri-Food Traceability Management using a RFID System with Privacy Protection
    P. Bernardi, C. Demartini, F. Gandino, B. Montrucchio, M. Rebaudengo, Sanchez E.R
    DOI: 10.1109/AINA.2007.29
    ABSTRACT: In this paper an agri-food traceability system based on public key cryptography and Radio Frequency Identification (RFID) technology is proposed. In order to guarantee safety in food, an efficient tracking and tracing system is required. RFID devices allow recording all useful information for traceability directly on the commodity. The security issues are discussed and two different methods based on public cryptography are proposed and evaluated. The first algorithm uses a nested RSA based structure to improve security, while the second also provides authenticity of data. An experimental analysis demonstrated that the proposed system is well suitable on PDAs too

  10. An Analysis of SEU Effects in Embedded Operating Systems for Real-Time Applications
    L. Sterpone, M. Violante
    International Symposium on Industrial Electronics
    DOI: 10.1109/ISIE.2007.4375152

  11. An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores
    L. Bolzani, E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero
    DOI: 10.1109/IOLTS.2007.14

  12. An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains
    J. Lagos-Benites, D. Appello, P. Bernardi, M. Grosso, D. Ravotto, E. Sanchez, M. Sonza Reorda

  13. An Enhanced Technique for the Automatic Generation of Effective Diagnosis-oriented Test Programs for Processors
    E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero
    DOI: 10.1109/DATE.2007.364451

  14. An Extensible Evolutionary-based General-purpose Optimizer
    E. Sanchez, M. Schillaci, G. Squillero

  15. An experimental analysis of SEU sensitiveness of recursive-oriented hardening techniques
    L. Sterpone, P. Reyes Moreno, J. Maestro, O. Ruano, P. Reviriego

  16. An optimized hybrid approach to provide fault detection and correction in SoCs
    L. Bolzani, P. Bernardi, M. Sonza Reorda

  17. Analysis of an RFID-based Information System for Tracking and Tracing in an Agri-Food chain
    F. Gandino, B. Montrucchio, M. Rebaudengo, E. Sanchez Sanchez
    IEEE RFID Eurasia Conference

  18. Analytical analysis of the MCUs sensitiveness of TMR architectures in SRAM-based FPGAs
    L. Sterpone, M. Violante
    DOI: 10.1109/RADECS.2007.5205501

  19. Automotive Microcontroller End-of-Line Test via Software-Based Methodologies
    W. Di Palma, D. Ravotto, E. Sanchez, M. Schillaci, M. Sonza Reorda, G. Squillero
    Eighth International Workshop on Microprocessor Test and Verification, 2007. MTV '07
    DOI: 10.1109/MTV.2007.15

  20. Co-evolution of Test Programs and Stimuli Vectors for Testing of Embedded Peripheral Cores
    L. Bolzani, E. Sanchez, M. Schillaci, G. Squillero

  21. Coupling EA and High-Level Metrics for the Automatic Generation of Test Blocks for Peripheral Cores
    L. Bolzani, E. Sanchez, M. Schillaci, G. Squillero
    GECCO'07
    DOI: 10.1145/1276958.1277342

  22. Design of an UHF RFID Transponder for Secure Authentication
    P. Bernardi, F. Gandino, B. Montrucchio, M. Rebaudengo, Sanchez E.R
    ABSTRACT: RFID technology increases rapidly its applicability in new areas of interest without guaranteeing security and privacy issues. This paper presents a new architecture of an RFID transponder with cryptographic capabilities. Other than being compatible with the EPC Class-1 Gen-2 communication protocol, our tag implements an asymmetric ciphering module that proved useful in authentication and anti-counterfeit schemes, particularly critical in many application fields. Experimental results concerning area requirements and power consumption indicate its feasibility

  23. Effectiveness of TMR-based techniques to mitigate alpha-induced SEU accumulation in commercial SRAM-based FPGAs
    A. Manuzzato, S. Gerardin, A. Paccagnella, L. Sterpone, M. Violante
    DOI: 10.1109/RADECS.2007.5205499

  24. Extended Fault Detection Techniques for Systems-on-Chip
    P. Bernardi, L. Bolzani, M. Sonza Reorda

  25. Hardware-Accelerated Path-Delay Fault Grading of Functional Test Programs for Processor-based Systems
    P. Bernardi, M. Grosso, M. Sonza Reorda
    Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI
    DOI: 10.1145/1228784.1228881

  26. Increasing Effective Radiated Power in Wireless Sensor Networks with Channel Coding Techniques
    Sanchez E.R, F. Gandino, B. Montrucchio, M. Rebaudengo
    IEEE International Conference on Electromagnetics in Advanced Applications, ICEAA '07
    DOI: 10.1109/ICEAA.2007.4387323
    ABSTRACT: In this paper we analyzed classical forward error correction (FEC) algorithms implemented in wireless sensor networks (WSNs). We adopted FEC algorithms in sensor network nodes and evaluated performance and cost related to their covered area. Experimental results show how FEC adoption increases bit error tolerance in additive white Gaussian noise channels while rising computational costs in an acceptable fashion; coding gains reach values higher than 1 dB with a time latency that is negligible when compared with WSN data rates

  27. On Test Program Generation for Peripheral Components in a SoC Resorting to High-Level Metrics
    L. Bolzani, E. Sanchez, M. Sonza Reorda

  28. On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores
    P. Bernardi, M. Grosso, E. Sanchez, M. Sonza Reorda
    European Test Symposium, 2007. ETS '07. 12th IEEE
    DOI: 10.1109/ETS.2007.28

  29. Optimization of Self Checking FIR filters by means of Fault Injection Analysis
    S. Pontarelli, L. Sterpone, G. Cardarilli, M. Re, M. Sonza Reorda, A. Salsano, M. Violante
    22th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

  30. Safety Evaluation of NanoFabrics
    M. Grosso, M. Rebaudengo, M. Sonza Reorda
    22th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2007

  31. Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders
    S. Pontarelli, L. Sterpone, G. Cardarilli, M. Re, M. Sonza Reorda, A. Salsano, M. Violante

  32. Sensitivity evaluation of TMR-hardened circuits to multiple SEUs induced by alpha particles in commercial SRAM-based FPGAs
    A. Manuzzato, P. Rech, S. Gerardin, A. Paccagnella, L. Sterpone, M. Violante
    International Symposium on Defect and Fault Tolerance in VLSI Systems

  33. Soft errors in SRAM-FPGAs: A comparison of two complementary approaches
    M. Alderighi, F. Casini, S. D'Angelo, M. Mancini, S. Pastore, L. Sterpone, M. Violante
    DOI: 10.1109/RADECS.2007.5205521

  34. Static and Dynamic Analysis of SEU effects in SRAM-based FPGAs
    L. Sterpone, M. Violante

  35. Validating the Dependability of Embedded Systems through Fault Injection by Means of Loadable Kernel Modules
    M. Murciano, M. Violante
    Proceedings of the 2007 IEEE International High Level Design Validation and Test Workshop